1 /*
2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/fdt_wrappers.h>
10 #include <common/runtime_svc.h>
11 #include <libfdt.h>
12 #include <smccc_helpers.h>
13
14 /* default platform version is 0.0 */
15 static int platform_version_major;
16 static int platform_version_minor;
17
18 #define SMC_FASTCALL 0x80000000
19 #define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000)
20 #define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000)
21 #define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n))
22
23 /*
24 * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform
25 * which uses SoC present in QEMU. And they can change on their own while we
26 * need version of whole 'virtual hardware platform'.
27 */
28 #define SIP_SVC_VERSION SIP_FUNCTION_ID(1)
29 #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100)
30 #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101)
31 #define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200)
32 #define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201)
33 #define SIP_SVC_GET_MEMORY_NODE_COUNT SIP_FUNCTION_ID(300)
34 #define SIP_SVC_GET_MEMORY_NODE SIP_FUNCTION_ID(301)
35
36 static uint64_t gic_its_addr;
37
38 typedef struct {
39 uint32_t nodeid;
40 uint32_t mpidr;
41 } cpu_data;
42
43 typedef struct{
44 uint32_t nodeid;
45 uint64_t addr_base;
46 uint64_t addr_size;
47 } memory_data;
48
49 static struct {
50 uint32_t num_cpus;
51 uint32_t num_memnodes;
52 cpu_data cpu[PLATFORM_CORE_COUNT];
53 memory_data memory[PLAT_MAX_MEM_NODES];
54 } dynamic_platform_info;
55
56 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
57 uintptr_t sbsa_get_gicd(void);
58 uintptr_t sbsa_get_gicr(void);
59
60 /*
61 * QEMU provides us with minimal information about hardware platform using
62 * minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
63 * a firmware DeviceTree.
64 *
65 * It is information passed from QEMU to describe the information a hardware
66 * platform would have other mechanisms to discover at runtime, that are
67 * affected by the QEMU command line.
68 *
69 * Ultimately this device tree will be replaced by IPC calls to an emulated SCP.
70 * And when we do that, we won't then have to rewrite Normal world firmware to
71 * cope.
72 */
73
read_cpuinfo_from_dt(void * dtb)74 void read_cpuinfo_from_dt(void *dtb)
75 {
76 int node;
77 int prev;
78 int cpu = 0;
79 uint32_t nodeid = 0;
80 uintptr_t mpidr;
81
82 /*
83 * QEMU gives us this DeviceTree node:
84 * numa-node-id entries are only when NUMA config is used
85 *
86 * cpus {
87 * #size-cells = <0x00>;
88 * #address-cells = <0x02>;
89 *
90 * cpu@0 {
91 * numa-node-id = <0x00>;
92 * reg = <0x00 0x00>;
93 * };
94 *
95 * cpu@1 {
96 * numa-node-id = <0x03>;
97 * reg = <0x00 0x01>;
98 * };
99 * };
100 */
101 node = fdt_path_offset(dtb, "/cpus");
102 if (node < 0) {
103 ERROR("No information about cpus in DeviceTree.\n");
104 panic();
105 }
106
107 /*
108 * QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we
109 * cannot use fdt_first_subnode() here
110 */
111 node = fdt_path_offset(dtb, "/cpus/cpu@0");
112
113 while (node > 0) {
114 if (fdt_getprop(dtb, node, "reg", NULL)) {
115 fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL);
116 } else {
117 ERROR("Incomplete information for cpu %d in DeviceTree.\n", cpu);
118 panic();
119 }
120
121 if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
122 fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
123 }
124
125 dynamic_platform_info.cpu[cpu].nodeid = nodeid;
126 dynamic_platform_info.cpu[cpu].mpidr = mpidr;
127
128 INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, nodeid, mpidr);
129
130 cpu++;
131
132 prev = node;
133 node = fdt_next_subnode(dtb, prev);
134 }
135
136 dynamic_platform_info.num_cpus = cpu;
137 INFO("Found %d cpus\n", dynamic_platform_info.num_cpus);
138 }
139
read_meminfo_from_dt(void * dtb)140 void read_meminfo_from_dt(void *dtb)
141 {
142 const fdt32_t *prop;
143 const char *type;
144 int prev, node;
145 int len;
146 uint32_t nodeid = 0;
147 uint32_t memnode = 0;
148 uint32_t higher_value, lower_value;
149 uint64_t cur_base, cur_size;
150
151 /*
152 * QEMU gives us this DeviceTree node:
153 *
154 * memory@100c0000000 {
155 * numa-node-id = <0x01>;
156 * reg = <0x100 0xc0000000 0x00 0x40000000>;
157 * device_type = "memory";
158 * };
159 *
160 * memory@10000000000 {
161 * numa-node-id = <0x00>;
162 * reg = <0x100 0x00 0x00 0xc0000000>;
163 * device_type = "memory";
164 * }
165 */
166
167 for (prev = 0;; prev = node) {
168 node = fdt_next_node(dtb, prev, NULL);
169 if (node < 0) {
170 break;
171 }
172
173 type = fdt_getprop(dtb, node, "device_type", &len);
174 if (type && strncmp(type, "memory", len) == 0) {
175 if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
176 fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
177 }
178
179 dynamic_platform_info.memory[memnode].nodeid = nodeid;
180
181 /*
182 * Get the 'reg' property of this node and
183 * assume two 8 bytes for base and size.
184 */
185 prop = fdt_getprop(dtb, node, "reg", &len);
186 if (prop != 0 && len == (2 * sizeof(int64_t))) {
187 higher_value = fdt32_to_cpu(*prop);
188 lower_value = fdt32_to_cpu(*(prop + 1));
189 cur_base = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32);
190
191 higher_value = fdt32_to_cpu(*(prop + 2));
192 lower_value = fdt32_to_cpu(*(prop + 3));
193 cur_size = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32);
194
195 dynamic_platform_info.memory[memnode].addr_base = cur_base;
196 dynamic_platform_info.memory[memnode].addr_size = cur_size;
197
198 INFO("RAM %d: node-id: %d, address: 0x%lx - 0x%lx\n",
199 memnode,
200 dynamic_platform_info.memory[memnode].nodeid,
201 dynamic_platform_info.memory[memnode].addr_base,
202 dynamic_platform_info.memory[memnode].addr_base +
203 dynamic_platform_info.memory[memnode].addr_size - 1);
204 }
205
206 memnode++;
207 }
208 }
209
210 dynamic_platform_info.num_memnodes = memnode;
211 }
212
read_platform_config_from_dt(void * dtb)213 void read_platform_config_from_dt(void *dtb)
214 {
215 int node;
216 const fdt64_t *data;
217 int err;
218 uintptr_t gicd_base;
219 uintptr_t gicr_base;
220
221 /*
222 * QEMU gives us this DeviceTree node:
223 *
224 * intc {
225 * reg = < 0x00 0x40060000 0x00 0x10000
226 * 0x00 0x40080000 0x00 0x4000000>;
227 * its {
228 * reg = <0x00 0x44081000 0x00 0x20000>;
229 * };
230 * };
231 */
232 node = fdt_path_offset(dtb, "/intc");
233 if (node < 0) {
234 return;
235 }
236
237 data = fdt_getprop(dtb, node, "reg", NULL);
238 if (data == NULL) {
239 return;
240 }
241
242 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL);
243 if (err < 0) {
244 ERROR("Failed to read GICD reg property of GIC node\n");
245 return;
246 }
247 INFO("GICD base = 0x%lx\n", gicd_base);
248
249 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL);
250 if (err < 0) {
251 ERROR("Failed to read GICR reg property of GIC node\n");
252 return;
253 }
254 INFO("GICR base = 0x%lx\n", gicr_base);
255
256 sbsa_set_gic_bases(gicd_base, gicr_base);
257
258 node = fdt_path_offset(dtb, "/intc/its");
259 if (node < 0) {
260 return;
261 }
262
263 err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL);
264 if (err < 0) {
265 ERROR("Failed to read GICI reg property of GIC node\n");
266 return;
267 }
268 INFO("GICI base = 0x%lx\n", gic_its_addr);
269 }
270
read_platform_version(void * dtb)271 void read_platform_version(void *dtb)
272 {
273 int node;
274
275 node = fdt_path_offset(dtb, "/");
276 if (node >= 0) {
277 platform_version_major = fdt32_ld(fdt_getprop(dtb, node,
278 "machine-version-major", NULL));
279 platform_version_minor = fdt32_ld(fdt_getprop(dtb, node,
280 "machine-version-minor", NULL));
281 }
282 }
283
sip_svc_init(void)284 void sip_svc_init(void)
285 {
286 /* Read DeviceTree data before MMU is enabled */
287
288 void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
289 int err;
290
291 err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE);
292 if (err < 0) {
293 ERROR("Invalid Device Tree at %p: error %d\n", dtb, err);
294 return;
295 }
296
297 err = fdt_check_header(dtb);
298 if (err < 0) {
299 ERROR("Invalid DTB file passed\n");
300 return;
301 }
302
303 read_platform_version(dtb);
304 INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor);
305
306 read_platform_config_from_dt(dtb);
307 read_cpuinfo_from_dt(dtb);
308 read_meminfo_from_dt(dtb);
309 }
310
311 /*
312 * This function is responsible for handling all SiP calls from the NS world
313 */
sbsa_sip_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)314 uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid,
315 u_register_t x1,
316 u_register_t x2,
317 u_register_t x3,
318 u_register_t x4,
319 void *cookie,
320 void *handle,
321 u_register_t flags)
322 {
323 uint32_t ns;
324 uint64_t index;
325
326 /* Determine which security state this SMC originated from */
327 ns = is_caller_non_secure(flags);
328 if (!ns) {
329 ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid);
330 SMC_RET1(handle, SMC_UNK);
331 }
332
333 switch (smc_fid) {
334 case SIP_SVC_VERSION:
335 INFO("Platform version requested\n");
336 SMC_RET3(handle, NULL, platform_version_major, platform_version_minor);
337
338 case SIP_SVC_GET_GIC:
339 SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr());
340
341 case SIP_SVC_GET_GIC_ITS:
342 SMC_RET2(handle, NULL, gic_its_addr);
343
344 case SIP_SVC_GET_CPU_COUNT:
345 SMC_RET2(handle, NULL, dynamic_platform_info.num_cpus);
346
347 case SIP_SVC_GET_CPU_NODE:
348 index = x1;
349 if (index < PLATFORM_CORE_COUNT) {
350 SMC_RET3(handle, NULL,
351 dynamic_platform_info.cpu[index].nodeid,
352 dynamic_platform_info.cpu[index].mpidr);
353 } else {
354 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
355 }
356
357 case SIP_SVC_GET_MEMORY_NODE_COUNT:
358 SMC_RET2(handle, NULL, dynamic_platform_info.num_memnodes);
359
360 case SIP_SVC_GET_MEMORY_NODE:
361 index = x1;
362 if (index < PLAT_MAX_MEM_NODES) {
363 SMC_RET4(handle, NULL,
364 dynamic_platform_info.memory[index].nodeid,
365 dynamic_platform_info.memory[index].addr_base,
366 dynamic_platform_info.memory[index].addr_size);
367 } else {
368 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
369 }
370
371 default:
372 ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid,
373 smc_fid - SIP_FUNCTION);
374 SMC_RET1(handle, SMC_UNK);
375 }
376 }
377
sbsa_sip_smc_setup(void)378 int sbsa_sip_smc_setup(void)
379 {
380 return 0;
381 }
382
383 /* Define a runtime service descriptor for fast SMC calls */
384 DECLARE_RT_SVC(
385 sbsa_sip_svc,
386 OEN_SIP_START,
387 OEN_SIP_END,
388 SMC_TYPE_FAST,
389 sbsa_sip_smc_setup,
390 sbsa_sip_smc_handler
391 );
392