1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_PMIF_SPI_H__ 4 #define __SOC_MEDIATEK_PMIF_SPI_H__ 5 6 #include <soc/addressmap.h> 7 #include <soc/pmif.h> 8 #include <types.h> 9 10 struct mtk_pmicspi_mst_regs { 11 u32 reserved1[4]; 12 u32 other_busy_sta_0; 13 u32 wrap_en; 14 u32 reserved2[2]; 15 u32 man_en; 16 u32 man_acc; 17 u32 reserved3[3]; 18 u32 mux_sel; 19 u32 reserved4[3]; 20 u32 dio_en; 21 u32 rddmy; 22 u32 cslext_write; 23 u32 cslext_read; 24 u32 cshext_write; 25 u32 cshext_read; 26 u32 ext_ck_write; 27 u32 ext_ck_read; 28 u32 si_sampling_ctrl; 29 }; 30 31 check_member(mtk_pmicspi_mst_regs, other_busy_sta_0, 0x10); 32 check_member(mtk_pmicspi_mst_regs, man_en, 0x20); 33 check_member(mtk_pmicspi_mst_regs, mux_sel, 0x34); 34 check_member(mtk_pmicspi_mst_regs, dio_en, 0x44); 35 36 static struct mtk_pmicspi_mst_regs * const mtk_pmicspi_mst = (void *)PMICSPI_MST_BASE; 37 38 /* PMIC registers */ 39 enum { 40 PMIC_BASE = 0x0000, 41 PMIC_SMT_CON1 = PMIC_BASE + 0x0032, 42 PMIC_DRV_CON1 = PMIC_BASE + 0x003a, 43 PMIC_FILTER_CON0 = PMIC_BASE + 0x0042, 44 PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, 45 PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, 46 PMIC_DEW_DIO_EN = PMIC_BASE + 0x040c, 47 PMIC_DEW_READ_TEST = PMIC_BASE + 0x040e, 48 PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, 49 PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, 50 PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, 51 PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0424, 52 PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0426, 53 PMIC_SPISLV_KEY = PMIC_BASE + 0x044a, 54 PMIC_INT_STA = PMIC_BASE + 0x0452, 55 PMIC_AUXADC_ADC7 = PMIC_BASE + 0x1096, 56 PMIC_AUXADC_ADC10 = PMIC_BASE + 0x109c, 57 PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, 58 }; 59 60 #define PMIF_SPI_HW_INF 0x307F 61 #define PMIF_SPI_MD BIT(8) 62 #define PMIF_SPI_AP_SECURE BIT(9) 63 #define PMIF_SPI_AP BIT(10) 64 #define PMIF_SPI_STAUPD BIT(14) 65 #define PMIF_SPI_TSX_HW BIT(19) 66 #define PMIF_SPI_DCXO_HW BIT(20) 67 68 #define DEFAULT_SLVID 0 69 70 #define PMIF_CMD_STA BIT(2) 71 #define SPIMST_STA BIT(9) 72 73 enum { 74 SPI_CLK = 0x1, 75 SPI_CSN = 0x1 << 1, 76 SPI_MOSI = 0x1 << 2, 77 SPI_MISO = 0x1 << 3, 78 SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, 79 SPI_SMT = SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO, 80 SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, 81 }; 82 83 enum { 84 SLV_IO_4_MA = 0x8, 85 }; 86 87 enum { 88 SPI_CLK_SHIFT = 0, 89 SPI_CSN_SHIFT = 4, 90 SPI_MOSI_SHIFT = 8, 91 SPI_MISO_SHIFT = 12, 92 SPI_DRIVING = SLV_IO_4_MA << SPI_CLK_SHIFT | SLV_IO_4_MA << SPI_CSN_SHIFT | 93 SLV_IO_4_MA << SPI_MOSI_SHIFT | SLV_IO_4_MA << SPI_MISO_SHIFT, 94 }; 95 96 enum { 97 OP_WR = 0x1, 98 OP_CSH = 0x0, 99 OP_CSL = 0x1, 100 OP_OUTS = 0x8, 101 }; 102 103 enum { 104 DEFAULT_VALUE_READ_TEST = 0x5aa5, 105 WRITE_TEST_VALUE = 0xa55a, 106 }; 107 108 enum { 109 DUMMY_READ_CYCLES = 0x8, 110 }; 111 112 enum { 113 E_CLK_EDGE = 1, 114 E_CLK_LAST_SETTING, 115 }; 116 117 int pmif_spi_init(struct pmif *arb); 118 void pmif_spi_iocfg(void); 119 #endif /* __SOC_MEDIATEK_PMIF_SPI_H__ */ 120