1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_H 4 #define SOC_MEDIATEK_COMMON_DP_DP_INTF_H 5 6 #include <edid.h> 7 #include <types.h> 8 9 #define DPINTF_EN 0x00 10 #define EN BIT(0) 11 12 #define DPINTF_RET 0x04 13 #define RST BIT(0) 14 #define RST_SEL BIT(16) 15 16 #define DPINTF_INTEN 0x08 17 #define INT_VSYNC_EN BIT(0) 18 #define INT_VDE_EN BIT(1) 19 #define INT_UNDERFLOW_EN BIT(2) 20 #define INT_TARGET_LINE_EN BIT(3) 21 22 #define DPINTF_INTSTA 0x0C 23 #define INT_VSYNC_STA BIT(0) 24 #define INT_VDE_STA BIT(1) 25 #define INT_UNDERFLOW_STA BIT(2) 26 #define INT_TARGET_LINE_STA BIT(3) 27 28 #define DPINTF_CON 0x10 29 #define BG_ENABLE BIT(0) 30 #define INTL_EN BIT(2) 31 #define TDFP_EN BIT(3) 32 #define VS_LODD_EN BIT(16) 33 #define VS_LEVEN_EN BIT(17) 34 #define VS_RODD_EN BIT(18) 35 #define VS_REVEN BIT(19) 36 #define FAKE_DE_LODD BIT(20) 37 #define FAKE_DE_LEVEN BIT(21) 38 #define FAKE_DE_RODD BIT(22) 39 #define FAKE_DE_REVEN BIT(23) 40 #define YUV422_EN BIT(24) 41 #define CLPF_EN BIT(25) 42 #define MATRIX_EN BIT(26) 43 #define INTERNAL_CG_EN BIT(27) 44 #define LOWPOWER_EN BIT(28) 45 #define INPUT_2P_EN BIT(29) 46 #define EXT_VSYNC_EN BIT(30) 47 48 #define DPINTF_OUTPUT_SETTING 0x14 49 #define PIXEL_SWAP BIT(0) 50 #define CH_SWAP BIT(1) 51 #define CH_SWAP_MASK (0x7 << 1) 52 #define SWAP_RGB (0x00 << 1) 53 #define SWAP_GBR (0x01 << 1) 54 #define SWAP_BRG (0x02 << 1) 55 #define SWAP_RBG (0x03 << 1) 56 #define SWAP_GRB (0x04 << 1) 57 #define SWAP_BGR (0x05 << 1) 58 #define B_MASK BIT(4) 59 #define G_MASK BIT(5) 60 #define R_MASK BIT(6) 61 #define DE_MASK BIT(8) 62 #define HS_MASK BIT(9) 63 #define VS_MASK BIT(10) 64 #define HSYNC_POL BIT(13) 65 #define VSYNC_POL BIT(14) 66 #define OUT_BIT BIT(16) 67 #define OUT_BIT_MASK (0x3 << 18) 68 #define OUT_BIT_8 (0x00 << 18) 69 #define OUT_BIT_10 (0x01 << 18) 70 #define OUT_BIT_12 (0x02 << 18) 71 #define OUT_BIT_16 (0x03 << 18) 72 73 #define DPINTF_SIZE 0x18 74 #define HSIZE 0 75 #define HSIZE_MASK (0xffff << 0) 76 #define VSIZE 16 77 #define VSIZE_MASK (0xffff << 16) 78 79 #define DPINTF_TGEN_HWIDTH 0x20 80 #define HPW 0 81 #define HPW_MASK (0xffff << 0) 82 83 #define DPINTF_TGEN_HPORCH 0x24 84 #define HBP 0 85 #define HBP_MASK (0xffff << 0) 86 #define HFP 16 87 #define HFP_MASK (0xffff << 16) 88 89 #define DPINTF_TGEN_VWIDTH 0x28 90 #define VSYNC_WIDTH_SHIFT 0 91 #define VSYNC_WIDTH_MASK (0xffff << 0) 92 #define VSYNC_HALF_LINE_SHIFT 16 93 #define VSYNC_HALF_LINE_MASK BIT(16) 94 95 96 #define DPINTF_TGEN_VPORCH 0x2C 97 #define VSYNC_BACK_PORCH_SHIFT 0 98 #define VSYNC_BACK_PORCH_MASK (0xffff << 0) 99 #define VSYNC_FRONT_PORCH_SHIFT 16 100 #define VSYNC_FRONT_PORCH_MASK (0xffff << 16) 101 102 #define DPINTF_BG_HCNTL 0x30 103 #define BG_RIGHT (0xffff << 0) 104 #define BG_LEFT (0xffff << 16) 105 106 #define DPINTF_BG_VCNTL 0x34 107 #define BG_BOT (0xffff << 0) 108 #define BG_TOP (0xffff << 16) 109 110 #define DPINTF_BG_COLOR 0x38 111 #define BG_B (0x3ff << 0) 112 #define BG_G (0x3ff << 10) 113 #define BG_R (0x3ff << 20) 114 115 #define DPINTF_FIFO_CTL 0x3C 116 #define FIFO_VALID_SET (0x1F << 0) 117 #define FIFO_RST_SEL BIT(8) 118 #define FIFO_RD_MASK BIT(12) 119 120 #define DPINTF_STATUS 0x40 121 #define VCOUNTER (0x3ffff << 0) 122 #define DPINTF_BUSY BIT(24) 123 #define FIELD BIT(28) 124 #define TDLR BIT(29) 125 126 #define DPINTF_TGEN_VWIDTH_LEVEN 0x68 127 #define DPINTF_TGEN_VPORCH_LEVEN 0x6C 128 #define DPINTF_TGEN_VWIDTH_RODD 0x70 129 #define DPINTF_TGEN_VPORCH_RODD 0x74 130 #define DPINTF_TGEN_VWIDTH_REVEN 0x78 131 #define DPINTF_TGEN_VPORCH_REVEN 0x7C 132 133 #define DPINTF_CLPF_SETTING 0x94 134 #define CLPF_TYPE (0x3 << 0) 135 #define ROUND_EN BIT(4) 136 137 #define DPINTF_Y_LIMIT 0x98 138 #define Y_LIMINT_BOT 0 139 #define Y_LIMINT_BOT_MASK (0xFFF << 0) 140 #define Y_LIMINT_TOP 16 141 #define Y_LIMINT_TOP_MASK (0xFFF << 16) 142 143 #define DPINTF_C_LIMIT 0x9C 144 #define C_LIMIT_BOT 0 145 #define C_LIMIT_BOT_MASK (0xFFF << 0) 146 #define C_LIMIT_TOP 16 147 #define C_LIMIT_TOP_MASK (0xFFF << 16) 148 149 #define DPINTF_YUV422_SETTING 0xA0 150 #define UV_SWAP BIT(0) 151 #define CR_DELSEL BIT(4) 152 #define CB_DELSEL BIT(5) 153 #define Y_DELSEL BIT(6) 154 #define DE_DELSEL BIT(7) 155 156 #define DPINTF_MATRIX_SET 0xB4 157 #define INT_MATRIX_SEL_MASK 0x1f 158 #define RGB_TO_JPEG 0x00 159 #define RGB_TO_FULL709 0x01 160 #define RGB_TO_BT601 0x02 161 #define RGB_TO_BT709 0x03 162 #define JPEG_TO_RGB 0x04 163 #define FULL709_TO_RGB 0x05 164 #define BT601_TO_RGB 0x06 165 #define BT709_TO_RGB 0x07 166 #define JPEG_TO_BT601 0x08 167 #define JPEG_TO_BT709 0x09 168 #define BT601_TO_JPEG 0xA 169 #define BT709_TO_JPEG 0xB 170 #define BT709_TO_BT601 0xC 171 #define BT601_TO_BT709 0xD 172 #define JPEG_TO_CERGB 0x14 173 #define FULL709_TO_CERGB 0x15 174 #define BT601_TO_CERGB 0x16 175 #define BT709_TO_CERGB 0x17 176 #define RGB_TO_CERGB 0x1C 177 178 #define MATRIX_BIT_MASK (0x3 << 8) 179 #define EXT_MATRIX_EN BIT(12) 180 181 enum mtk_dpintf_out_bit_num { 182 MTK_DPINTF_OUT_BIT_NUM_8BITS, 183 MTK_DPINTF_OUT_BIT_NUM_10BITS, 184 MTK_DPINTF_OUT_BIT_NUM_12BITS, 185 MTK_DPINTF_OUT_BIT_NUM_16BITS, 186 }; 187 188 enum mtk_dpintf_out_yc_map { 189 MTK_DPINTF_OUT_YC_MAP_RGB, 190 MTK_DPINTF_OUT_YC_MAP_CYCY, 191 MTK_DPINTF_OUT_YC_MAP_YCYC, 192 MTK_DPINTF_OUT_YC_MAP_CY, 193 MTK_DPINTF_OUT_YC_MAP_YC, 194 }; 195 196 enum mtk_dpintf_out_channel_swap { 197 MTK_DPINTF_OUT_CHANNEL_SWAP_RGB, 198 MTK_DPINTF_OUT_CHANNEL_SWAP_GBR, 199 MTK_DPINTF_OUT_CHANNEL_SWAP_BRG, 200 MTK_DPINTF_OUT_CHANNEL_SWAP_RBG, 201 MTK_DPINTF_OUT_CHANNEL_SWAP_GRB, 202 MTK_DPINTF_OUT_CHANNEL_SWAP_BGR, 203 }; 204 205 enum mtk_dpintf_out_color_format { 206 MTK_DPINTF_COLOR_FORMAT_RGB, 207 MTK_DPINTF_COLOR_FORMAT_RGB_FULL, 208 MTK_DPINTF_COLOR_FORMAT_YCBCR_444, 209 MTK_DPINTF_COLOR_FORMAT_YCBCR_422, 210 MTK_DPINTF_COLOR_FORMAT_XV_YCC, 211 MTK_DPINTF_COLOR_FORMAT_YCBCR_444_FULL, 212 MTK_DPINTF_COLOR_FORMAT_YCBCR_422_FULL, 213 }; 214 215 enum mtk_dpintf_input_mode { 216 MTK_DPINTF_INPUT_MODE_1P = 0, 217 MTK_DPINTF_INPUT_MODE_2P = INPUT_2P_EN, 218 }; 219 220 enum TVDPLL_CLK { 221 TVDPLL_PLL = 0, 222 TVDPLL_D2 = 1, 223 TVDPLL_D4 = 3, 224 TVDPLL_D8 = 5, 225 TVDPLL_D16 = 7, 226 }; 227 228 struct mtk_dpintf { 229 void *regs; 230 enum mtk_dpintf_out_color_format color_format; 231 enum mtk_dpintf_out_yc_map yc_map; 232 enum mtk_dpintf_out_bit_num bit_num; 233 enum mtk_dpintf_out_channel_swap channel_swap; 234 enum mtk_dpintf_input_mode input_mode; 235 }; 236 237 enum mtk_dpintf_polarity { 238 MTK_DPINTF_POLARITY_RISING, 239 MTK_DPINTF_POLARITY_FALLING, 240 }; 241 242 struct mtk_dpintf_polarities { 243 enum mtk_dpintf_polarity de_pol; 244 enum mtk_dpintf_polarity ck_pol; 245 enum mtk_dpintf_polarity hsync_pol; 246 enum mtk_dpintf_polarity vsync_pol; 247 }; 248 249 struct mtk_dpintf_sync_param { 250 u32 sync_width; 251 u32 front_porch; 252 u32 back_porch; 253 bool shift_half_line; 254 }; 255 256 struct mtk_dpintf_yc_limit { 257 u16 y_top; 258 u16 y_bottom; 259 u16 c_top; 260 u16 c_bottom; 261 }; 262 263 extern const struct mtk_dpintf dpintf_data; 264 265 void dp_intf_config(const struct edid *edid); 266 267 #endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */ 268