1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <amdblocks/cpu.h> 4 #include <arch/cpuid.h> 5 #include <cpu/cpu.h> 6 #include <cpu/x86/msr.h> 7 #include <cpu/amd/cpuid.h> 8 #include <cpu/amd/msr.h> 9 #include <cpu/amd/mtrr.h> 10 #include <smbios.h> 11 #include <soc/iomap.h> 12 #include <types.h> 13 get_pstate_0_reg(void)14uint32_t get_pstate_0_reg(void) 15 { 16 return 0; 17 } 18 get_pstate_latency(void)19uint32_t get_pstate_latency(void) 20 { 21 return 0; 22 } 23 smbios_processor_family(struct cpuid_result res)24unsigned int smbios_processor_family(struct cpuid_result res) 25 { 26 return 0x6b; /* Zen */ 27 } 28 set_cstate_io_addr(void)29void set_cstate_io_addr(void) 30 { 31 msr_t cst_addr; 32 33 cst_addr.hi = 0; 34 cst_addr.lo = ACPI_CSTATE_CONTROL; 35 wrmsr(MSR_CSTATE_ADDRESS, cst_addr); 36 } 37 38 /* Number of most significant physical address bits reserved for secure memory encryption */ get_reserved_phys_addr_bits(void)39unsigned int get_reserved_phys_addr_bits(void) 40 { 41 if (!(rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE)) 42 return 0; 43 44 return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >> 45 CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT; 46 } 47