1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _COMMON_QUPV3_CONFIG_H_ 4 #define _COMMON_QUPV3_CONFIG_H_ 5 6 #include <assert.h> 7 #include <soc/clock.h> 8 #include <soc/qcom_qup_se.h> 9 10 #define QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK 0x00000001 11 #define QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK 0x00000001 12 13 #define GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK 0x00000200 14 #define GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK 0x00000100 15 16 #define GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK 0x00000001 17 18 #define DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008 19 #define DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004 20 #define DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001 21 22 #define DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK 0x00000010 23 #define DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008 24 #define DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004 25 #define DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001 26 27 #define DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK 0x00000008 28 #define DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK 0x00000004 29 #define DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK 0x00000002 30 #define DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK 0x00000001 31 32 #define GENI_CLK_CTRL_SER_CLK_SEL_BMSK 0x00000001 33 #define DMA_IF_EN_DMA_IF_EN_BMSK 0x00000001 34 #define SE_GSI_EVENT_EN_BMSK 0x0000000f 35 #define SE_IRQ_EN_RMSK 0x0000000f 36 37 #define SIZE_GENI_FW_RAM 0x00000200 38 #define SEFW_MAGIC_HEADER 0x57464553 39 40 #define GSI_FW_MAGIC_HEADER 0x20495351 41 #define GSI_REG_BASE_SIZE 0x5000 42 #define GSI_INST_RAM_n_MAX_n 4095 43 #define GSI_FW_BYTES_PER_LINE 8 44 #define GSI_MCS_CFG_MCS_ENABLE_BMSK 0x1 45 #define GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 46 #define GSI_CFG_GSI_ENABLE_BMSK 0x1 47 #define GSI_CGC_CTRL_REGION_2_HW_CGC_EN_BMSK 0x2 48 49 50 struct elf_se_hdr { 51 uint32_t magic; /* = 'SEFW' */ 52 uint32_t version; /* Structure version number */ 53 uint32_t core_version; /* QUPV3_HW_VERSION */ 54 uint16_t serial_protocol; /* Programmed into GENI_FW_REVISION */ 55 uint16_t fw_version; /* Programmed into GENI_FW_REVISION */ 56 uint16_t cfg_version; /* Programmed into GENI_INIT_CFG_REVISION */ 57 uint16_t fw_size_in_items; /* Number of (uint32_t) GENI_FW_RAM words */ 58 uint16_t fw_offset; /* Byte offset of GENI_FW_RAM array */ 59 uint16_t cfg_size_in_items;/* Number of GENI_FW_CFG index/value pairs */ 60 uint16_t cfg_idx_offset; /* Byte offset of GENI_FW_CFG index array */ 61 uint16_t cfg_val_offset; /* Byte offset of GENI_FW_CFG values array */ 62 }; 63 64 struct gsi_fw_hdr { 65 uint32_t magic; /* = 'QSI' */ 66 uint32_t version; /* Structure version number */ 67 uint32_t core_version; /* QUPV3_HW_VERSION */ 68 uint32_t fw_version; /* Programmed into GSI_FW_REVISION */ 69 uint16_t fw_size_in_items; /* Number of GSI FW lines (each 8 bytes) */ 70 uint16_t fw_offset; /* Byte offset of GENI_FW_RAM array */ 71 uint16_t iep_size_in_items;/* Number of IEP items */ 72 uint16_t iep_offset; /* Byte offset of first IEP entry */ 73 }; 74 75 struct gsi_fw_iram { 76 uint32_t iram_dword0; /* word 0 of a single IRAM firmware entry */ 77 uint32_t iram_dword1; /* word 1 of a single IRAM firmware entry */ 78 }; 79 80 struct gsi_fw_iep { 81 uint32_t offset; /* offset from QUPV3_GSI_TOP */ 82 uint32_t value ; /* value to be written into above offset */ 83 }; 84 85 struct qupv3_common_reg { 86 u8 reserved_1[0x118]; 87 u32 qupv3_se_ahb_m_cfg_reg; 88 u8 reserved_2[0x4]; 89 u32 qupv3_common_cfg_reg; 90 }; 91 92 void qupv3_fw_init(void); 93 void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, 94 unsigned int mode); 95 void gpi_firmware_load(int addr); 96 97 #endif /* _COMMON_QUPV3_CONFIG_H_ */ 98