1 /*
2 * Copyright © 2022 Imagination Technologies Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef PVR_PDS_H
25 #define PVR_PDS_H
26
27 #include <stdbool.h>
28
29 #include "pvr_device_info.h"
30 #include "pvr_limits.h"
31 #include "pds/pvr_rogue_pds_defs.h"
32 #include "util/macros.h"
33
34 #ifdef __cplusplus
35 # define restrict __restrict__
36 #endif
37
38 /*****************************************************************************
39 Macro definitions
40 *****************************************************************************/
41
42 /* Based on Maximum number of passes that may emit DOUTW x Maximum number that
43 * might be emitted.
44 */
45 #define PVR_PDS_MAX_TOTAL_NUM_DWORD_DOUTW 6
46 /* Based on Maximum number of passes that may emit DOUTW x Maximum number that
47 * might be emitted.
48 */
49 #define PVR_PDS_MAX_TOTAL_NUM_QWORD_DOUTW 3
50 /* Based on max(max(UBOs,cbuffers), numTextures). */
51 #define PVR_PDS_MAX_NUM_DMA_KICKS 32
52 #define PVR_PDS_NUM_VERTEX_STREAMS 32
53 #define PVR_PDS_NUM_VERTEX_ELEMENTS 32
54 #define PVR_MAXIMUM_ITERATIONS 128
55
56 #define PVR_PDS_NUM_COMPUTE_INPUT_REGS 3
57
58 #define PVR_NEED_SW_COMPUTE_PDS_BARRIER(dev_info) \
59 PVR_HAS_FEATURE(dev_info, compute_morton_capable) && \
60 !PVR_HAS_ERN(dev_info, 45493)
61
62 /* FIXME: Change BIL to SPV. */
63 /* Any variable location can have at most 4 32-bit components. */
64 #define BIL_COMPONENTS_PER_LOCATION 4
65
66 /* Maximum number of DDMAD's that may be performed (Num attribs * Num DMA's per
67 * attribute).
68 */
69 #define PVR_MAX_VERTEX_ATTRIB_DMAS \
70 (PVR_MAX_VERTEX_INPUT_BINDINGS * BIL_COMPONENTS_PER_LOCATION)
71
72 /*****************************************************************************
73 Typedefs
74 *****************************************************************************/
75
76 /* FIXME: We might need to change some bools to this. */
77 typedef uint32_t PVR_PDS_BOOL;
78
79 /*****************************************************************************
80 Enums
81 *****************************************************************************/
82
83 enum pvr_pds_generate_mode {
84 PDS_GENERATE_SIZES,
85 PDS_GENERATE_CODE_SEGMENT,
86 PDS_GENERATE_DATA_SEGMENT,
87 PDS_GENERATE_CODEDATA_SEGMENTS
88 };
89
90 enum pvr_pds_store_type { PDS_COMMON_STORE, PDS_UNIFIED_STORE };
91
92 enum pvr_pds_vertex_attrib_program_type {
93 PVR_PDS_VERTEX_ATTRIB_PROGRAM_BASIC,
94 PVR_PDS_VERTEX_ATTRIB_PROGRAM_BASE_INSTANCE,
95 PVR_PDS_VERTEX_ATTRIB_PROGRAM_DRAW_INDIRECT,
96 PVR_PDS_VERTEX_ATTRIB_PROGRAM_COUNT
97 };
98
99 enum pvr_pds_addr_literal_type {
100 PVR_PDS_ADDR_LITERAL_DESC_SET_ADDRS_TABLE,
101 PVR_PDS_ADDR_LITERAL_PUSH_CONSTS,
102 PVR_PDS_ADDR_LITERAL_BLEND_CONSTANTS,
103 };
104
105 /*****************************************************************************
106 Structure definitions
107 *****************************************************************************/
108
109 struct pvr_psc_register {
110 uint32_t num;
111
112 unsigned int size; /* size of each element. */
113 unsigned int dim : 4; /* max number of elements. */
114 unsigned int index; /* offset into array. */
115
116 unsigned int cast;
117
118 unsigned int type;
119 uint64_t name;
120 bool auto_assign;
121 unsigned int original_type;
122 };
123
124 struct pvr_psc_program_output {
125 const uint32_t *code;
126
127 struct pvr_psc_register *data;
128 unsigned int data_count;
129
130 unsigned int data_size_aligned;
131 unsigned int code_size_aligned;
132 unsigned int temp_size_aligned;
133
134 unsigned int data_size;
135 unsigned int code_size;
136 unsigned int temp_size;
137
138 void (*write_data)(void *data, uint32_t *buffer);
139 };
140
141 struct pvr_pds_usc_task_control {
142 uint64_t src0;
143 };
144
145 /* Up to 4 64-bit state words currently supported. */
146 #define PVR_PDS_MAX_NUM_DOUTW_CONSTANTS 4
147
148 /* Structure for DOUTW. */
149 struct pvr_pds_doutw_control {
150 enum pvr_pds_store_type dest_store;
151 uint32_t num_const64;
152 uint64_t doutw_data[PVR_PDS_MAX_NUM_DOUTW_CONSTANTS];
153 bool last_instruction;
154
155 uint32_t *data_segment;
156 uint32_t data_size;
157 uint32_t code_size;
158 };
159
160 /* Structure representing the PDS pixel event program.
161 *
162 * data_segment - pointer to the data segment
163 * task_control - USC task control words
164 * emit_words - array of Emit words
165 * data_size - size of data segment
166 * code_size - size of code segment
167 */
168 struct pvr_pds_event_program {
169 uint32_t *data_segment;
170 struct pvr_pds_usc_task_control task_control;
171
172 uint32_t num_emit_word_pairs;
173 uint32_t *emit_words;
174
175 uint32_t data_size;
176 uint32_t code_size;
177 };
178
179 /*
180 * Structure representing the PDS pixel shader secondary attribute program.
181 *
182 * data_segment - pointer to the data segment
183 *
184 * num_uniform_dma_kicks - number of Uniform DMA kicks
185 * uniform_dma_control - array of Uniform DMA control words
186 * uniform_dma_address - array of Uniform DMA address words
187 *
188 * num_texture_dma_kicks - number of Texture State DMA kicks
189 * texture_dma_control - array of Texture State DMA control words
190 * texture_dma_address - array of Texture State DMA address words
191 *
192 * data_size - size of data segment
193 * code_size - size of code segment
194 *
195 * temps_used - PDS Temps
196 */
197 struct pvr_pds_pixel_shader_sa_program {
198 uint32_t *data_segment;
199
200 uint32_t num_dword_doutw;
201 uint32_t dword_doutw_value[PVR_PDS_MAX_TOTAL_NUM_DWORD_DOUTW];
202 uint32_t dword_doutw_control[PVR_PDS_MAX_TOTAL_NUM_DWORD_DOUTW];
203
204 uint32_t num_q_word_doutw;
205 uint32_t q_word_doutw_value[2 * PVR_PDS_MAX_TOTAL_NUM_QWORD_DOUTW];
206 uint32_t q_word_doutw_control[PVR_PDS_MAX_TOTAL_NUM_QWORD_DOUTW];
207
208 uint32_t num_uniform_dma_kicks;
209 uint64_t uniform_dma_address[PVR_PDS_MAX_NUM_DMA_KICKS];
210 uint32_t uniform_dma_control[PVR_PDS_MAX_NUM_DMA_KICKS];
211
212 uint32_t num_texture_dma_kicks;
213 uint64_t texture_dma_address[PVR_PDS_MAX_NUM_DMA_KICKS];
214 uint32_t texture_dma_control[PVR_PDS_MAX_NUM_DMA_KICKS];
215
216 bool kick_usc;
217 bool write_tile_position;
218 uint32_t tile_position_attr_dest;
219 struct pvr_pds_usc_task_control usc_task_control;
220
221 bool clear;
222 uint32_t *clear_color;
223 uint32_t clear_color_dest_reg;
224 bool packed_clear;
225
226 uint32_t data_size;
227 uint32_t code_size;
228
229 uint32_t temps_used;
230 };
231
232 /* Structure representing the PDS pixel shader program.
233 *
234 * data_segment - pointer to the data segment
235 * usc_task_control - array of USC task control words
236 *
237 * data_size - size of data segment
238 * code_size - size of code segment
239 */
240 struct pvr_pds_kickusc_program {
241 uint32_t *data_segment;
242 struct pvr_pds_usc_task_control usc_task_control;
243
244 uint32_t data_size;
245 uint32_t code_size;
246 };
247
248 /* Structure representing the PDS fence/doutc program.
249 *
250 * data_segment - pointer to the data segment
251 * data_size - size of data segment
252 * code_size - size of code segment
253 */
254 struct pvr_pds_fence_program {
255 uint32_t *data_segment;
256 uint32_t fence_constant_word;
257 uint32_t data_size;
258 uint32_t code_size;
259 };
260
261 /* Structure representing the PDS coefficient loading.
262 *
263 * data_segment - pointer to the data segment
264 * num_fpu_iterators - number of FPU iterators
265 * FPU_iterators - array of FPU iterator control words
266 * destination - array of Common Store destinations
267 *
268 * data_size - size of data segment
269 * code_size - size of code segment
270 */
271 struct pvr_pds_coeff_loading_program {
272 uint32_t *data_segment;
273 uint32_t num_fpu_iterators;
274 uint32_t FPU_iterators[PVR_MAXIMUM_ITERATIONS];
275 uint32_t destination[PVR_MAXIMUM_ITERATIONS];
276
277 uint32_t data_size;
278 uint32_t code_size;
279
280 uint32_t temps_used;
281 };
282
283 /* Structure representing the PDS vertex shader secondary attribute program.
284 *
285 * data_segment - pointer to the data segment
286 * num_dma_kicks - number of DMA kicks
287 * dma_control - array of DMA control words
288 * dma_address - array of DMA address words
289 *
290 * data_size - size of data segment
291 * code_size - size of code segment
292 */
293 struct pvr_pds_vertex_shader_sa_program {
294 uint32_t *data_segment;
295
296 /* num_uniform_dma_kicks, uniform_dma_address, uniform_dma_control, are not
297 * used for generating PDS data section and code section, they are currently
298 * only used to simpler the driver implementation. The driver should correct
299 * these information into num_dma_kicks, dma_address and dma_control to get
300 * the PDS properly generated.
301 */
302
303 uint32_t num_dword_doutw;
304 uint32_t dword_doutw_value[PVR_PDS_MAX_TOTAL_NUM_DWORD_DOUTW];
305 uint32_t dword_doutw_control[PVR_PDS_MAX_TOTAL_NUM_DWORD_DOUTW];
306
307 uint32_t num_q_word_doutw;
308 uint32_t q_word_doutw_value[2 * PVR_PDS_MAX_TOTAL_NUM_QWORD_DOUTW];
309 uint32_t q_word_doutw_control[PVR_PDS_MAX_TOTAL_NUM_QWORD_DOUTW];
310
311 uint32_t num_uniform_dma_kicks;
312 uint64_t uniform_dma_address[PVR_PDS_MAX_NUM_DMA_KICKS];
313 uint32_t uniform_dma_control[PVR_PDS_MAX_NUM_DMA_KICKS];
314
315 uint32_t num_texture_dma_kicks;
316 uint64_t texture_dma_address[PVR_PDS_MAX_NUM_DMA_KICKS];
317 uint32_t texture_dma_control[PVR_PDS_MAX_NUM_DMA_KICKS];
318
319 uint32_t num_dma_kicks;
320 uint64_t dma_address[PVR_PDS_MAX_NUM_DMA_KICKS];
321 uint32_t dma_control[PVR_PDS_MAX_NUM_DMA_KICKS];
322
323 bool kick_usc;
324 struct pvr_pds_usc_task_control usc_task_control;
325
326 /* Shared register buffer base address (VDM/CDM context load case only). */
327 bool clear_pds_barrier;
328
329 uint32_t data_size;
330 uint32_t code_size;
331 };
332
333 /* Structure representing a PDS vertex stream element.
334 *
335 * There are two types of element, repeat DMA and non-repeat DMA.
336 *
337 * Non repeat DMA are the classic DMA of some number of bytes from an offset
338 * into contiguous registers. It is assumed the address and size are dword
339 * aligned. To use this, specify 0 for the component size. Each four bytes read
340 * will go to the next HW register.
341 *
342 * Repeat DMA enables copying of sub dword amounts at non dword aligned
343 * addresses. To use this, specify the component size as either 1,2,3 or 4
344 * bytes. Size specifies the number of components, and each component read
345 * will go to the next HW register.
346 *
347 * In both cases, HW registers are written contiguously.
348 *
349 * offset - offset of the vertex stream element
350 * size - size of the vertex stream element in bytes for non repeat DMA, or
351 * number of components for repeat DMA.
352 * reg - first vertex stream element register to DMA to.
353 * component_size - Size of component for repeat DMA, or 0 for non repeat dma.
354 */
355 struct pvr_pds_vertex_element {
356 uint32_t offset;
357 uint32_t size;
358 uint16_t reg;
359 uint16_t component_size;
360 };
361
362 /* Structure representing a PDS vertex stream.
363 *
364 * instance_data - flag whether the vertex stream is indexed or instance data
365 * read_back - If True, vertex is reading back data output by GPU earlier in
366 * same kick. This will enable MCU coherency if relevant.
367 * multiplier - vertex stream frequency multiplier
368 * shift - vertex stream frequency shift
369 * address - vertex stream address in bytes
370 * buffer_size_in_bytes - buffer size in bytes if vertex attribute is sourced
371 * from buffer object
372 * stride - vertex stream stride in bytes
373 * num_vertices - number of vertices in buffer. Used for OOB checking.
374 - 0 = disable oob checking.
375 * num_elements - number of vertex stream elements
376 * elements - array of vertex stream elements
377 * use_ddmadt - When the has_pds_ddmadt feature is enabled. Boolean allowing
378 * DDMADT to be use per stream element.
379 */
380 struct pvr_pds_vertex_stream {
381 bool current_state;
382 bool instance_data;
383 bool read_back;
384 uint32_t multiplier;
385 uint32_t shift;
386 uint64_t address;
387 uint32_t buffer_size_in_bytes;
388 uint32_t stride;
389 uint32_t num_vertices;
390 uint32_t num_elements;
391 struct pvr_pds_vertex_element elements[PVR_PDS_NUM_VERTEX_ELEMENTS];
392
393 bool use_ddmadt;
394 };
395
396 /* Structure representing the PDS vertex shader program.
397 *
398 * This structure describes the USC code and vertex buffers required
399 * by the PDS vertex loading program.
400 *
401 * data_segment - Pointer to the data segment.
402 * usc_task_control - Description of USC task for vertex shader program.
403 * num_streams - Number of vertex streams.
404 * iterate_vtx_id - If set, the vertex id should be iterated.
405 * vtx_id_register - The register to iterate the VertexID into (if applicable)
406 * vtx_id_modifier - Value to pvr_add/SUB from index value received by PDS.
407 * This is used because the index value received by PDS has
408 * INDEX_OFFSET added, and generally VertexID wouldn't.
409 * vtx_id_sub_modifier - If true, vtx_id_modifier is subtracted, else added.
410 * iterate_instance_id - If set, the instance id should be iterated.
411 * instance_id_register - The register to iterate the InstanceID into (if
412 * applicable). The vertex and instance id will both be
413 * iterated as unsigned ints
414 *
415 * iterate_remap_id - Should be set to true if vertex shader needs
416 * VS_REMAPPED_INDEX_ID (e.g. Another TA shader runs after
417 * it).
418 * null_idx - Indicates no index buffer is bound, so every index should be
419 * null_idx_value.
420 * null_idx_value - The value to use as index if null_idx set.
421 * data_size - Size of data segment, in dwords. Output by call to
422 * pvr_pds_vertex_shader, and used as input when generating data.
423 * code_size - Size of code segment. Output by call to pvr_pds_vertex_shader.
424 * This is the number of dword instructions that are/were generated.
425 * temps_used - Number of temporaries used. Output by call to
426 * pvr_pds_vertex_shader.
427 */
428 struct pvr_pds_vertex_shader_program {
429 uint32_t *data_segment;
430 struct pvr_pds_usc_task_control usc_task_control;
431 uint32_t num_streams;
432
433 bool iterate_vtx_id;
434 uint32_t vtx_id_register;
435 uint32_t vtx_id_modifier;
436 bool vtx_id_sub_modifier;
437
438 bool iterate_instance_id;
439 uint32_t instance_id_register;
440 uint32_t instance_id_modifier;
441 uint32_t base_instance;
442
443 bool iterate_remap_id;
444
445 bool null_idx;
446 uint32_t null_idx_value;
447
448 uint32_t *stream_patch_offsets;
449 uint32_t num_stream_patches;
450
451 uint32_t data_size;
452 uint32_t code_size;
453 uint32_t temps_used;
454 uint32_t ddmadt_enables;
455 uint32_t skip_stream_flag;
456
457 bool draw_indirect;
458 bool indexed;
459
460 struct pvr_pds_vertex_stream streams[PVR_PDS_NUM_VERTEX_STREAMS];
461 };
462
463 /* Structure representing PDS shared reg storing program. */
464 struct pvr_pds_shared_storing_program {
465 struct pvr_pds_doutw_control doutw_control; /*!< DOUTW state */
466 struct pvr_pds_kickusc_program usc_task; /*!< DOUTU state */
467 bool cc_enable; /*!< cc bit is set on the doutu instruction. */
468 uint32_t data_size; /*!< total data size, non-aligned. */
469 uint32_t code_size; /*!< total code size, non-aligned. */
470 };
471
472 #define PVR_MAX_STREAMOUT_BUFFERS 4
473
474 /* Structure representing stream out init PDS programs. */
475 struct pvr_pds_stream_out_init_program {
476 /* --- Input to PDS_STREAM_OUT_INT_PROGRAM --- */
477
478 /* Number of buffers to load/store.
479 * This indicates the number of entries in the next two arrays.
480 * Data is loaded/stored contiguously to persistent temps.
481 */
482 uint32_t num_buffers;
483
484 /* Number of persistent temps in dword to load/store for each buffer. */
485 uint32_t pds_buffer_data_size[PVR_MAX_STREAMOUT_BUFFERS];
486 /* The device address for loading/storing persistent temps for each buffer.
487 * If address is zero, then no data is loaded/stored
488 * into pt registers for the buffer.
489 */
490 uint64_t dev_address_for_buffer_data[PVR_MAX_STREAMOUT_BUFFERS];
491
492 /* PDS state update Stream Out Init Programs. */
493 uint32_t stream_out_init_pds_data_size;
494 uint32_t stream_out_init_pds_code_size;
495 };
496
497 /* Structure representing stream out terminate PDS program. */
498 struct pvr_pds_stream_out_terminate_program {
499 /* Input to PDS_STREAM_OUT_TERMINATE_PROGRAM.
500 *
501 * Number of persistent temps in dword used in stream out PDS programs needs
502 * to be stored.
503 * The terminate program writes pds_persistent_temp_size_to_store number
504 * persistent temps to dev_address_for_storing_persistent_temp.
505 */
506 uint32_t pds_persistent_temp_size_to_store;
507
508 /* The device address for storing persistent temps. */
509 uint64_t dev_address_for_storing_persistent_temp;
510
511 /* PPP state update Stream Out Program for stream out terminate. */
512 uint32_t stream_out_terminate_pds_data_size;
513 uint32_t stream_out_terminate_pds_code_size;
514 };
515
516 /* Structure representing the PDS compute shader program.
517 * This structure describes the USC code and compute buffers required
518 * by the PDS compute task loading program
519 *
520 * data_segment
521 * pointer to the data segment
522 * usc_task_control
523 * Description of USC task for compute shader program.
524 * data_size
525 * Size of data segment, in dwords.
526 * Output by call to pvr_pds_compute_shader, and used as input when
527 * generating data. code_size Size of code segment. Output by call to
528 * pvr_pds_compute_shader. This is the number of dword instructions that
529 * are/were generated. temps_used Number of temporaries used. Output by call
530 *to pvr_pds_compute_shader. highest_temp The highest temp number used. Output
531 *by call to pvr_pds_compute_shader coeff_update_task_branch_size The number of
532 * instructions we need to branch over to skip the coefficient update task.
533 */
534
535 struct pvr_pds_compute_shader_program {
536 uint32_t *data_segment;
537 struct pvr_pds_usc_task_control usc_task_control;
538 struct pvr_pds_usc_task_control usc_task_control_coeff_update;
539
540 uint32_t data_size;
541 uint32_t code_size;
542
543 uint32_t temps_used;
544 uint32_t highest_temp;
545
546 uint32_t local_input_regs[3];
547 uint32_t work_group_input_regs[3];
548 uint32_t global_input_regs[3];
549
550 uint32_t barrier_coefficient;
551
552 bool fence;
553
554 bool flattened_work_groups;
555
556 bool clear_pds_barrier;
557
558 bool has_coefficient_update_task;
559
560 uint32_t coeff_update_task_branch_size;
561
562 bool add_base_workgroup;
563 uint32_t base_workgroup_constant_offset_in_dwords[3];
564
565 bool kick_usc;
566
567 bool conditional_render;
568 uint32_t cond_render_const_offset_in_dwords;
569 uint32_t cond_render_pred_temp;
570 };
571 struct pvr_pds_ldst_control {
572 uint64_t cache_control_const;
573 };
574
575 /* Define a value we can use as a register number in the driver to denote that
576 * the value is unused.
577 */
578 #define PVR_PDS_COMPUTE_INPUT_REG_UNUSED 0xFFFFFFFFU
579
pvr_pds_compute_shader_program_init(struct pvr_pds_compute_shader_program * program)580 static inline void pvr_pds_compute_shader_program_init(
581 struct pvr_pds_compute_shader_program *program)
582 {
583 *program = (struct pvr_pds_compute_shader_program){
584 .local_input_regs = {
585 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
586 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
587 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
588 },
589 .work_group_input_regs = {
590 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
591 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
592 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
593 },
594 .global_input_regs = {
595 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
596 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
597 PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
598 },
599 .barrier_coefficient = PVR_PDS_COMPUTE_INPUT_REG_UNUSED,
600 };
601 }
602
603 /*****************************************************************************
604 function declarations
605 *****************************************************************************/
606
607 /*****************************************************************************
608 Constructors
609 *****************************************************************************/
610
611 void pvr_pds_pixel_shader_sa_initialize(
612 struct pvr_pds_pixel_shader_sa_program *program);
613 void pvr_pds_compute_shader_initialize(
614 struct pvr_pds_compute_shader_program *program);
615
616 /* Utility */
617
618 uint32_t pvr_pds_append_constant64(uint32_t *constants,
619 uint64_t constant_value,
620 uint32_t *data_size);
621
622 uint32_t pvr_pds_encode_dma_burst(uint32_t *dma_control,
623 uint64_t *dma_address,
624 uint32_t dest_offset,
625 uint32_t dma_size,
626 uint64_t src_address,
627 bool last,
628 const struct pvr_device_info *dev_info);
629
630 void pvr_pds_setup_doutu(struct pvr_pds_usc_task_control *usc_task_control,
631 uint64_t execution_address,
632 uint32_t usc_temps,
633 uint32_t sample_rate,
634 bool phase_rate_change);
635
636 /* Pixel */
637 #define pvr_pds_set_sizes_pixel_shader(X) \
638 pvr_pds_kick_usc(X, NULL, 0, false, PDS_GENERATE_SIZES)
639 #define pvr_pds_generate_pixel_shader_program(X, Y) \
640 pvr_pds_kick_usc(X, Y, 0, false, PDS_GENERATE_CODEDATA_SEGMENTS)
641
642 #define pvr_pds_generate_VDM_sync_program(X, Y) \
643 pvr_pds_kick_usc(X, Y, 0, false, PDS_GENERATE_CODEDATA_SEGMENTS)
644
645 uint32_t *pvr_pds_generate_doutc(struct pvr_pds_fence_program *restrict program,
646 uint32_t *restrict buffer,
647 enum pvr_pds_generate_mode gen_mode);
648
649 uint32_t *
650 pvr_pds_generate_doutw(struct pvr_pds_doutw_control *restrict psControl,
651 uint32_t *restrict buffer,
652 enum pvr_pds_generate_mode gen_mode,
653 const struct pvr_device_info *dev_info);
654
655 uint32_t *pvr_pds_kick_usc(struct pvr_pds_kickusc_program *restrict program,
656 uint32_t *restrict buffer,
657 uint32_t start_next_constant,
658 bool cc_enabled,
659 enum pvr_pds_generate_mode gen_mode);
660
661 /* Pixel Secondary */
662 #define pvr_pds_set_sizes_pixel_shader_sa_uniform_data(X, Y) \
663 pvr_pds_pixel_shader_uniform_texture_data(X, \
664 NULL, \
665 PDS_GENERATE_SIZES, \
666 true, \
667 Y)
668 #define pvr_pds_set_sizes_pixel_shader_sa_texture_data(X, Y) \
669 pvr_pds_pixel_shader_uniform_texture_data(X, \
670 NULL, \
671 PDS_GENERATE_SIZES, \
672 false, \
673 Y)
674 #define pvr_pds_set_sizes_pixel_shader_uniform_texture_code(X) \
675 pvr_pds_pixel_shader_uniform_texture_code(X, NULL, PDS_GENERATE_SIZES)
676
677 #define pvr_pds_generate_pixel_shader_sa_texture_state_data(X, Y, Z) \
678 pvr_pds_pixel_shader_uniform_texture_data(X, \
679 Y, \
680 PDS_GENERATE_DATA_SEGMENT, \
681 false, \
682 Z)
683
684 #define pvr_pds_generate_pixel_shader_sa_code_segment(X, Y) \
685 pvr_pds_pixel_shader_uniform_texture_code(X, Y, PDS_GENERATE_CODE_SEGMENT)
686
687 uint32_t *pvr_pds_pixel_shader_uniform_texture_data(
688 struct pvr_pds_pixel_shader_sa_program *restrict program,
689 uint32_t *restrict buffer,
690 enum pvr_pds_generate_mode gen_mode,
691 bool uniform,
692 const struct pvr_device_info *dev_info);
693
694 uint32_t *pvr_pds_pixel_shader_uniform_texture_code(
695 struct pvr_pds_pixel_shader_sa_program *restrict program,
696 uint32_t *restrict buffer,
697 enum pvr_pds_generate_mode gen_mode);
698
699 /* Vertex */
700 #define pvr_pds_set_sizes_vertex_shader(X, Y) \
701 pvr_pds_vertex_shader(X, NULL, PDS_GENERATE_SIZES, Y)
702
703 #define pvr_pds_generate_vertex_shader_data_segment(X, Y, Z) \
704 pvr_pds_vertex_shader(X, Y, PDS_GENERATE_DATA_SEGMENT, Z)
705
706 #define pvr_pds_generate_vertex_shader_code_segment(X, Y, Z) \
707 pvr_pds_vertex_shader(X, Y, PDS_GENERATE_CODE_SEGMENT, Z)
708
709 uint32_t *
710 pvr_pds_vertex_shader(struct pvr_pds_vertex_shader_program *restrict program,
711 uint32_t *restrict buffer,
712 enum pvr_pds_generate_mode gen_mode,
713 const struct pvr_device_info *dev_info);
714
715 /* Compute */
716 uint32_t *
717 pvr_pds_compute_shader(struct pvr_pds_compute_shader_program *restrict program,
718 uint32_t *restrict buffer,
719 enum pvr_pds_generate_mode gen_mode,
720 const struct pvr_device_info *dev_info);
721
722 /* Vertex Secondary */
723 #define pvr_pds_set_sizes_vertex_shader_sa(X, Y) \
724 pvr_pds_vertex_shader_sa(X, NULL, PDS_GENERATE_SIZES, Y)
725
726 #define pvr_pds_generate_vertex_shader_sa_data_segment(X, Y, Z) \
727 pvr_pds_vertex_shader_sa(X, Y, PDS_GENERATE_DATA_SEGMENT, Z)
728
729 #define pvr_pds_generate_vertex_shader_sa_code_segment(X, Y, Z) \
730 pvr_pds_vertex_shader_sa(X, Y, PDS_GENERATE_CODE_SEGMENT, Z)
731
732 uint32_t *pvr_pds_vertex_shader_sa(
733 struct pvr_pds_vertex_shader_sa_program *restrict program,
734 uint32_t *restrict buffer,
735 enum pvr_pds_generate_mode gen_mode,
736 const struct pvr_device_info *dev_info);
737
738 /* Pixel Event */
739 #define pvr_pds_set_sizes_pixel_event(X, Y) \
740 pvr_pds_generate_pixel_event(X, NULL, PDS_GENERATE_SIZES, Y)
741
742 #define pvr_pds_generate_pixel_event_data_segment(X, Y, Z) \
743 pvr_pds_generate_pixel_event(X, Y, PDS_GENERATE_DATA_SEGMENT, Z)
744
745 #define pvr_pds_generate_pixel_event_code_segment(X, Y, Z) \
746 pvr_pds_generate_pixel_event(X, Y, PDS_GENERATE_CODE_SEGMENT, Z)
747
748 uint32_t *
749 pvr_pds_generate_pixel_event(struct pvr_pds_event_program *restrict program,
750 uint32_t *restrict buffer,
751 enum pvr_pds_generate_mode gen_mode,
752 const struct pvr_device_info *dev_info);
753
754 /* Coefficient Loading */
755 #define pvr_pds_set_sizes_coeff_loading(X) \
756 pvr_pds_coefficient_loading(X, NULL, PDS_GENERATE_SIZES)
757
758 #define pvr_pds_generate_coeff_loading_program(X, Y) \
759 pvr_pds_coefficient_loading(X, Y, PDS_GENERATE_CODE_SEGMENT)
760
761 uint32_t *pvr_pds_coefficient_loading(
762 struct pvr_pds_coeff_loading_program *restrict program,
763 uint32_t *restrict buffer,
764 enum pvr_pds_generate_mode gen_mode);
765
766 /* Compute DM barrier-specific conditional code */
767 uint32_t *pvr_pds_generate_compute_barrier_conditional(
768 uint32_t *buffer,
769 enum pvr_pds_generate_mode gen_mode);
770
771 /* Shared register storing */
772 uint32_t *pvr_pds_generate_shared_storing_program(
773 struct pvr_pds_shared_storing_program *restrict program,
774 uint32_t *restrict buffer,
775 enum pvr_pds_generate_mode gen_mode,
776 const struct pvr_device_info *dev_info);
777
778 /*Shared register loading */
779 uint32_t *pvr_pds_generate_fence_terminate_program(
780 struct pvr_pds_fence_program *restrict program,
781 uint32_t *restrict buffer,
782 enum pvr_pds_generate_mode gen_mode,
783 const struct pvr_device_info *dev_info);
784
785 /* CDM Shared register loading */
786 uint32_t *pvr_pds_generate_compute_shared_loading_program(
787 struct pvr_pds_shared_storing_program *restrict program,
788 uint32_t *restrict buffer,
789 enum pvr_pds_generate_mode gen_mode,
790 const struct pvr_device_info *dev_info);
791
792 /* Stream out */
793 uint32_t *pvr_pds_generate_stream_out_init_program(
794 struct pvr_pds_stream_out_init_program *restrict program,
795 uint32_t *restrict buffer,
796 bool store_mode,
797 enum pvr_pds_generate_mode gen_mode,
798 const struct pvr_device_info *dev_info);
799
800 uint32_t *pvr_pds_generate_stream_out_terminate_program(
801 struct pvr_pds_stream_out_terminate_program *restrict program,
802 uint32_t *restrict buffer,
803 enum pvr_pds_generate_mode gen_mode,
804 const struct pvr_device_info *dev_info);
805
806 /* Structure representing DrawIndirect PDS programs. */
807 struct pvr_pds_drawindirect_program {
808 /* --- Input to pvr_pds_drawindirect_program --- */
809
810 /* Address of the index list block in the VDM control stream.
811 * This must point to a 128-bit aligned index list header.
812 */
813 uint64_t index_list_addr_buffer;
814 /* Address of arguments for Draw call. Layout is defined by eArgFormat. */
815 uint64_t arg_buffer;
816
817 /* Address of index buffer. */
818 uint64_t index_buffer;
819
820 /* The raw (without addr msb in [7:0]) index block header. */
821 uint32_t index_block_header;
822
823 /* Number of bytes per index. */
824 uint32_t index_stride;
825
826 /* Used during/after compilation to fill in constant buffer. */
827 struct pvr_psc_register data[32];
828
829 /* Results of compilation. */
830 struct pvr_psc_program_output program;
831
832 /* This is used for ARB_multi_draw_indirect. */
833 unsigned int count;
834 unsigned int stride;
835
836 /* Internal stuff. */
837 unsigned int num_views;
838
839 bool support_base_instance;
840 bool increment_draw_id;
841 };
842
843 void pvr_pds_generate_draw_arrays_indirect(
844 struct pvr_pds_drawindirect_program *restrict program,
845 uint32_t *restrict buffer,
846 enum pvr_pds_generate_mode gen_mode,
847 const struct pvr_device_info *dev_info);
848 void pvr_pds_generate_draw_elements_indirect(
849 struct pvr_pds_drawindirect_program *restrict program,
850 uint32_t *restrict buffer,
851 enum pvr_pds_generate_mode gen_mode,
852 const struct pvr_device_info *dev_info);
853
854 uint64_t pvr_pds_encode_st_src0(uint64_t src,
855 uint64_t count4,
856 uint64_t dst_add,
857 bool write_through,
858 const struct pvr_device_info *dev_info);
859
860 uint64_t pvr_pds_encode_ld_src0(uint64_t dest,
861 uint64_t count8,
862 uint64_t src_add,
863 bool cached,
864 const struct pvr_device_info *dev_info);
865
866 uint32_t *pvr_pds_generate_single_ldst_instruction(
867 bool ld,
868 const struct pvr_pds_ldst_control *control,
869 uint32_t temp_index,
870 uint64_t address,
871 uint32_t count,
872 uint32_t *next_constant,
873 uint32_t *total_data_size,
874 uint32_t *total_code_size,
875 uint32_t *buffer,
876 bool data_fence,
877 enum pvr_pds_generate_mode gen_mode,
878 const struct pvr_device_info *dev_info);
879 struct pvr_pds_descriptor_set {
880 unsigned int descriptor_set; /* id of the descriptor set. */
881 unsigned int size_in_dwords; /* Number of dwords to transfer. */
882 unsigned int destination; /* Destination shared register to which
883 * descriptor entries should be loaded.
884 */
885 bool primary; /* Primary or secondary? */
886 unsigned int offset_in_dwords; /* Offset from the start of the descriptor
887 * set to start DMA'ing from.
888 */
889 };
890
891 struct pvr_pds_addr_literal {
892 enum pvr_pds_addr_literal_type type;
893 unsigned int destination;
894 };
895
896 #define PVR_BUFFER_TYPE_UBO (0)
897 #define PVR_BUFFER_TYPE_COMPILE_TIME (1)
898 #define PVR_BUFFER_TYPE_BLEND_CONSTS (2)
899 #define PVR_BUFFER_TYPE_PUSH_CONSTS (3)
900 #define PVR_BUFFER_TYPE_BUFFER_LENGTHS (4)
901 #define PVR_BUFFER_TYPE_DYNAMIC (5)
902 #define PVR_BUFFER_TYPE_UBO_ZEROING (6)
903 #define PVR_BUFFER_TYPE_INVALID (~0)
904
905 struct pvr_pds_buffer {
906 uint16_t type;
907
908 uint16_t size_in_dwords;
909 uint32_t destination;
910
911 union {
912 uint32_t *data;
913 struct {
914 uint32_t buffer_id;
915 uint16_t desc_set;
916 uint16_t binding;
917 uint32_t source_offset;
918 };
919 };
920 };
921
922 #define PVR_PDS_MAX_BUFFERS (24)
923
924 struct pvr_pds_descriptor_program_input {
925 /* User-specified descriptor sets. */
926 unsigned int descriptor_set_count;
927 struct pvr_pds_descriptor_set descriptor_sets[8];
928
929 unsigned int addr_literal_count;
930 struct pvr_pds_addr_literal addr_literals[8];
931
932 /* "State" buffers, including:
933 * compile-time constants
934 * blend constants
935 * push constants
936 * UBOs that have been hoisted.
937 */
938 uint32_t buffer_count;
939 struct pvr_pds_buffer buffers[PVR_PDS_MAX_BUFFERS];
940
941 uint32_t blend_constants_used_mask;
942
943 bool secondary_program_present;
944 struct pvr_pds_usc_task_control secondary_task_control;
945
946 bool must_not_be_empty;
947 };
948
949 #define PVR_PDS_VERTEX_FLAGS_VERTEX_ID_REQUIRED BITFIELD_BIT(0U)
950 #define PVR_PDS_VERTEX_FLAGS_INSTANCE_ID_REQUIRED BITFIELD_BIT(1U)
951 #define PVR_PDS_VERTEX_FLAGS_DRAW_INDIRECT_VARIANT BITFIELD_BIT(2U)
952 #define PVR_PDS_VERTEX_FLAGS_BASE_INSTANCE_VARIANT BITFIELD_BIT(3U)
953 #define PVR_PDS_VERTEX_FLAGS_BASE_INSTANCE_REQUIRED BITFIELD_BIT(4U)
954
955 /* BaseVertex is used in shader. */
956 #define PVR_PDS_VERTEX_FLAGS_BASE_VERTEX_REQUIRED BITFIELD_BIT(5U)
957
958 #define PVR_PDS_VERTEX_FLAGS_DRAW_INDEX_REQUIRED BITFIELD_BIT(6U)
959
960 #define PVR_PDS_VERTEX_DMA_FLAGS_INSTANCE_RATE BITFIELD_BIT(0U)
961
962 struct pvr_pds_vertex_dma {
963 /* Try and keep this structure packing as small as possible. */
964 uint16_t offset;
965 uint16_t stride;
966
967 uint8_t flags;
968 uint8_t size_in_dwords;
969 uint8_t component_size_in_bytes;
970 uint8_t destination;
971 uint8_t binding_index;
972 uint32_t divisor;
973
974 uint16_t robustness_buffer_offset;
975 };
976
977 struct pvr_pds_vertex_primary_program_input {
978 /* Control for the DOUTU that kicks the vertex USC shader. */
979 struct pvr_pds_usc_task_control usc_task_control;
980 /* List of DMAs (of size dma_count). */
981 const struct pvr_pds_vertex_dma *dma_list;
982 uint32_t dma_count;
983
984 /* ORd bitfield of PVR_PDS_VERTEX_FLAGS_* */
985 uint32_t flags;
986
987 uint16_t vertex_id_register;
988 uint16_t instance_id_register;
989
990 /* API provided baseInstance (i.e. not from drawIndirect). */
991 uint32_t base_instance;
992
993 uint16_t base_instance_register;
994 uint16_t base_vertex_register;
995 uint16_t draw_index_register;
996 };
997
998 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_NULL (0)
999 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_LITERAL64 (1)
1000 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_LITERAL32 (2)
1001 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_DESCRIPTOR_SET (3)
1002 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_CONSTANT_BUFFER (4)
1003 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_SPECIAL_BUFFER (5)
1004 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_DOUTU_ADDRESS (6)
1005 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_VERTEX_ATTRIBUTE_ADDRESS (7)
1006 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_ROBUST_VERTEX_ATTRIBUTE_ADDRESS (8)
1007
1008 /* Use if pds_ddmadt is enabled. */
1009 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_VERTEX_ATTR_DDMADT_OOB_BUFFER_SIZE (9)
1010
1011 /* Use if pds_ddmadt is not enabled. */
1012 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_VERTEX_ATTRIBUTE_MAX_INDEX (9)
1013
1014 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_BASE_INSTANCE (10)
1015 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_CONSTANT_BUFFER_ZEROING (11)
1016 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_BASE_VERTEX (12)
1017 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_BASE_WORKGROUP (13)
1018 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_COND_RENDER (14)
1019
1020 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_ADDR_LITERAL_BUFFER (15)
1021 #define PVR_PDS_CONST_MAP_ENTRY_TYPE_ADDR_LITERAL (16)
1022
1023 /* We pack all the following structs tightly into a buffer using += sizeof(x)
1024 * offsets, this can lead to data that is not native aligned. Supplying the
1025 * packed attribute indicates that unaligned accesses may be required, and the
1026 * aligned attribute causes the size of the structure to be aligned to a
1027 * specific boundary.
1028 */
1029 #define PVR_ALIGNED __attribute__((packed, aligned(1)))
1030
1031 struct pvr_const_map_entry {
1032 uint8_t type;
1033 uint8_t const_offset;
1034 } PVR_ALIGNED;
1035
1036 struct pvr_const_map_entry_literal32 {
1037 uint8_t type;
1038 uint8_t const_offset;
1039
1040 uint32_t literal_value;
1041 } PVR_ALIGNED;
1042
1043 struct pvr_const_map_entry_literal64 {
1044 uint8_t type;
1045 uint8_t const_offset;
1046
1047 uint64_t literal_value;
1048 } PVR_ALIGNED;
1049
1050 struct pvr_const_map_entry_descriptor_set {
1051 uint8_t type;
1052 uint8_t const_offset;
1053
1054 uint32_t descriptor_set;
1055 PVR_PDS_BOOL primary;
1056 uint32_t offset_in_dwords;
1057 } PVR_ALIGNED;
1058
1059 struct pvr_const_map_entry_constant_buffer {
1060 uint8_t type;
1061 uint8_t const_offset;
1062
1063 uint16_t buffer_id;
1064 uint16_t desc_set;
1065 uint16_t binding;
1066 uint32_t offset;
1067 uint32_t size_in_dwords;
1068 } PVR_ALIGNED;
1069
1070 struct pvr_const_map_entry_constant_buffer_zeroing {
1071 uint8_t type;
1072 uint8_t const_offset;
1073
1074 uint16_t buffer_id;
1075 uint32_t offset;
1076 uint32_t size_in_dwords;
1077 } PVR_ALIGNED;
1078
1079 struct pvr_const_map_entry_special_buffer {
1080 uint8_t type;
1081 uint8_t const_offset;
1082
1083 uint8_t buffer_type;
1084 uint32_t buffer_index;
1085 } PVR_ALIGNED;
1086
1087 struct pvr_const_map_entry_doutu_address {
1088 uint8_t type;
1089 uint8_t const_offset;
1090
1091 uint64_t doutu_control;
1092 } PVR_ALIGNED;
1093
1094 struct pvr_const_map_entry_vertex_attribute_address {
1095 uint8_t type;
1096 uint8_t const_offset;
1097
1098 uint16_t offset;
1099 uint16_t stride;
1100 uint8_t binding_index;
1101 uint8_t size_in_dwords;
1102 } PVR_ALIGNED;
1103
1104 struct pvr_const_map_entry_robust_vertex_attribute_address {
1105 uint8_t type;
1106 uint8_t const_offset;
1107
1108 uint16_t offset;
1109 uint16_t stride;
1110 uint8_t binding_index;
1111 uint8_t size_in_dwords;
1112 uint16_t robustness_buffer_offset;
1113 uint8_t component_size_in_bytes;
1114 } PVR_ALIGNED;
1115
1116 struct pvr_const_map_entry_vertex_attribute_max_index {
1117 uint8_t type;
1118 uint8_t const_offset;
1119
1120 uint8_t binding_index;
1121 uint8_t size_in_dwords;
1122 uint16_t offset;
1123 uint16_t stride;
1124 uint8_t component_size_in_bytes;
1125 } PVR_ALIGNED;
1126
1127 struct pvr_const_map_entry_base_instance {
1128 uint8_t type;
1129 uint8_t const_offset;
1130 } PVR_ALIGNED;
1131
1132 struct pvr_const_map_entry_base_vertex {
1133 uint8_t type;
1134 uint8_t const_offset;
1135 };
1136
1137 struct pvr_pds_const_map_entry_base_workgroup {
1138 uint8_t type;
1139 uint8_t const_offset;
1140 uint8_t workgroup_component;
1141 } PVR_ALIGNED;
1142
1143 struct pvr_pds_const_map_entry_vertex_attr_ddmadt_oob_buffer_size {
1144 uint8_t type;
1145 uint8_t const_offset;
1146 uint8_t binding_index;
1147 } PVR_ALIGNED;
1148
1149 struct pvr_pds_const_map_entry_cond_render {
1150 uint8_t type;
1151 uint8_t const_offset;
1152
1153 uint32_t cond_render_pred_temp;
1154 } PVR_ALIGNED;
1155
1156 struct pvr_pds_const_map_entry_addr_literal_buffer {
1157 uint8_t type;
1158 uint8_t const_offset;
1159
1160 uint32_t size;
1161 } PVR_ALIGNED;
1162
1163 struct pvr_pds_const_map_entry_addr_literal {
1164 uint8_t type;
1165 enum pvr_pds_addr_literal_type addr_type;
1166 } PVR_ALIGNED;
1167
1168 struct pvr_pds_info {
1169 uint32_t temps_required;
1170 uint32_t code_size_in_dwords;
1171 uint32_t data_size_in_dwords;
1172
1173 uint32_t entry_count;
1174 size_t entries_size_in_bytes;
1175 size_t entries_written_size_in_bytes;
1176 struct pvr_const_map_entry *entries;
1177 };
1178
1179 void pvr_pds_generate_descriptor_upload_program(
1180 struct pvr_pds_descriptor_program_input *input_program,
1181 uint32_t *code_section,
1182 struct pvr_pds_info *info);
1183 void pvr_pds_generate_vertex_primary_program(
1184 struct pvr_pds_vertex_primary_program_input *input_program,
1185 uint32_t *code,
1186 struct pvr_pds_info *info,
1187 bool use_robust_vertex_fetch,
1188 const struct pvr_device_info *dev_info);
1189
1190 /**
1191 * Generate USC address.
1192 *
1193 * \param doutu Location to write the generated address.
1194 * \param execution_address Address to generate from.
1195 */
1196 static ALWAYS_INLINE void
pvr_set_usc_execution_address64(uint64_t * doutu,uint64_t execution_address)1197 pvr_set_usc_execution_address64(uint64_t *doutu, uint64_t execution_address)
1198 {
1199 doutu[0] |= (((execution_address >>
1200 PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_ALIGNSHIFT)
1201 << PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_SHIFT) &
1202 ~PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_CLRMSK);
1203 }
1204
1205 #endif /* PVR_PDS_H */
1206