1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ 4 #define __SOC_ROCKCHIP_RK3288_GRF_H__ 5 6 #include <soc/addressmap.h> 7 #include <soc/soc.h> 8 #include <types.h> 9 10 struct rk3288_grf_gpio_lh { 11 u32 l; 12 u32 h; 13 }; 14 check_member(rk3288_grf_gpio_lh, h, 0x4); 15 16 struct rk3288_grf_regs { 17 u32 reserved[3]; 18 union { 19 u32 gpio1d_iomux; 20 u32 iomux_lcdc; 21 }; 22 u32 gpio2a_iomux; 23 u32 gpio2b_iomux; 24 union { 25 u32 gpio2c_iomux; 26 u32 iomux_i2c3; 27 }; 28 u32 reserved2; 29 union { 30 u32 gpio3a_iomux; 31 u32 iomux_emmcdata; 32 }; 33 union { 34 u32 gpio3b_iomux; 35 u32 iomux_emmcpwren; 36 }; 37 union { 38 u32 gpio3c_iomux; 39 u32 iomux_emmccmd; 40 }; 41 u32 gpio3dl_iomux; 42 u32 gpio3dh_iomux; 43 u32 gpio4al_iomux; 44 u32 gpio4ah_iomux; 45 u32 gpio4bl_iomux; 46 u32 reserved3; 47 u32 gpio4c_iomux; 48 u32 gpio4d_iomux; 49 u32 reserved4; 50 union { 51 u32 gpio5b_iomux; 52 u32 iomux_spi0; 53 }; 54 u32 gpio5c_iomux; 55 u32 reserved5; 56 union { 57 u32 gpio6a_iomux; 58 u32 iomux_i2s; 59 }; 60 union { 61 u32 gpio6b_iomux; 62 u32 iomux_i2c2; 63 u32 iomux_i2sclk; 64 }; 65 union { 66 u32 gpio6c_iomux; 67 u32 iomux_sdmmc0; 68 }; 69 u32 reserved6; 70 union { 71 u32 gpio7a_iomux; 72 u32 iomux_pwm0; 73 u32 iomux_pwm1; 74 }; 75 union { 76 u32 gpio7b_iomux; 77 u32 iomux_edp_hotplug; 78 }; 79 union { 80 u32 gpio7cl_iomux; 81 u32 iomux_i2c5sda; 82 u32 iomux_i2c4; 83 }; 84 union { 85 u32 gpio7ch_iomux; 86 u32 iomux_uart2; 87 u32 iomux_i2c5scl; 88 }; 89 u32 reserved7; 90 union { 91 u32 gpio8a_iomux; 92 u32 iomux_spi2csclk; 93 u32 iomux_i2c1; 94 }; 95 union { 96 u32 gpio8b_iomux; 97 u32 iomux_spi2txrx; 98 }; 99 u32 reserved8[30]; 100 struct rk3288_grf_gpio_lh gpio_sr[8]; 101 u32 gpio1_p[8][4]; 102 u32 gpio1_e[8][4]; 103 u32 gpio_smt; 104 u32 soc_con0; 105 u32 soc_con1; 106 u32 soc_con2; 107 u32 soc_con3; 108 u32 soc_con4; 109 u32 soc_con5; 110 u32 soc_con6; 111 u32 soc_con7; 112 u32 soc_con8; 113 u32 soc_con9; 114 u32 soc_con10; 115 u32 soc_con11; 116 u32 soc_con12; 117 u32 soc_con13; 118 u32 soc_con14; 119 u32 soc_status[22]; 120 u32 reserved9[2]; 121 u32 peridmac_con[4]; 122 u32 ddrc0_con0; 123 u32 ddrc1_con0; 124 u32 cpu_con[5]; 125 u32 reserved10[3]; 126 u32 cpu_status0; 127 u32 reserved11; 128 u32 uoc0_con[5]; 129 u32 uoc1_con[5]; 130 u32 uoc2_con[4]; 131 u32 uoc3_con[2]; 132 u32 uoc4_con[2]; 133 u32 pvtm_con[3]; 134 u32 pvtm_status[3]; 135 u32 io_vsel; 136 u32 saradc_testbit; 137 u32 tsadc_testbit_l; 138 u32 tsadc_testbit_h; 139 u32 os_reg[4]; 140 u32 reserved12; 141 u32 soc_con15; 142 u32 soc_con16; 143 }; 144 check_member(rk3288_grf_regs, soc_con16, 0x3a8); 145 146 struct rk3288_sgrf_regs { 147 u32 soc_con0; 148 u32 soc_con1; 149 u32 soc_con2; 150 u32 soc_con3; 151 u32 soc_con4; 152 u32 soc_con5; 153 u32 reserved1[(0x20-0x18)/4]; 154 u32 busdmac_con[2]; 155 u32 reserved2[(0x40-0x28)/4]; 156 u32 cpu_con[3]; 157 u32 reserved3[(0x50-0x4c)/4]; 158 u32 soc_con6; 159 u32 soc_con7; 160 u32 soc_con8; 161 u32 soc_con9; 162 u32 soc_con10; 163 u32 soc_con11; 164 u32 soc_con12; 165 u32 soc_con13; 166 u32 soc_con14; 167 u32 soc_con15; 168 u32 soc_con16; 169 u32 soc_con17; 170 u32 soc_con18; 171 u32 soc_con19; 172 u32 soc_con20; 173 u32 soc_con21; 174 u32 reserved4[(0x100-0x90)/4]; 175 u32 soc_status[2]; 176 u32 reserved5[(0x120-0x108)/4]; 177 u32 fast_boot_addr; 178 }; 179 check_member(rk3288_sgrf_regs, fast_boot_addr, 0x0120); 180 181 static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; 182 static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; 183 184 #define IOMUX_I2C1 RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8) 185 #define IOMUX_I2C2 RK_SETBITS(1 << 4 | 1 << 2) 186 #define IOMUX_I2C3 RK_SETBITS(1 << 2 | 1 << 0) 187 #define IOMUX_I2C4 RK_SETBITS(1 << 8 | 1 << 4) 188 #define IOMUX_I2C5SDA RK_CLRSETBITS(3 << 12, 1 << 12) 189 #define IOMUX_I2C5SCL RK_CLRSETBITS(3 << 0, 1 << 0) 190 #define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \ 191 1 << 10 | 1 << 8) 192 #define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12) 193 #define IOMUX_SPI2_TXRX RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0) 194 #define IOMUX_I2S RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) 195 #define IOMUX_I2SCLK RK_SETBITS(1 << 0) 196 #define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) 197 #define IOMUX_LCDC RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) 198 #define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\ 199 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) 200 #define IOMUX_EMMCDATA RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\ 201 2 << 8 | 2 << 6 | 2 << 4 |\ 202 2 << 2 | 2 << 0) 203 #define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) 204 #define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) 205 #define IOMUX_PWM1 RK_SETBITS(1 << 2) 206 #define IOMUX_EDP_HOTPLUG RK_CLRSETBITS(0x3 << 6, 0x2 << 6) 207 #define IOMUX_HDMI_EDP_I2C_SDA RK_CLRSETBITS(0x3 << 12, 2 << 12) 208 #define IOMUX_HDMI_EDP_I2C_SCL RK_CLRSETBITS(0x3 << 0, 2 << 0) 209 210 /* Use to mux a pin back to GPIO function. Since the selector for that is always 211 * 0, we can just reuse RK mask/value patterns and mask out the "value" part. */ 212 #define IOMUX_GPIO(iomux_clrsetbits) ((iomux_clrsetbits) & (0xffff << 16)) 213 214 #endif /* __SOC_ROCKCHIP_RK3288_GRF_H__ */ 215