1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Resource Director Technology(RDT)
4 * - Cache Allocation code.
5 *
6 * Copyright (C) 2016 Intel Corporation
7 *
8 * Authors:
9 * Fenghua Yu <[email protected]>
10 * Tony Luck <[email protected]>
11 * Vikas Shivappa <[email protected]>
12 *
13 * More information about RDT be found in the Intel (R) x86 Architecture
14 * Software Developer Manual June 2016, volume 3, section 17.17.
15 */
16
17 #define pr_fmt(fmt) "resctrl: " fmt
18
19 #include <linux/cpu.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/cpuhotplug.h>
23
24 #include <asm/cpu_device_id.h>
25 #include <asm/resctrl.h>
26 #include "internal.h"
27
28 /*
29 * rdt_domain structures are kfree()d when their last CPU goes offline,
30 * and allocated when the first CPU in a new domain comes online.
31 * The rdt_resource's domain list is updated when this happens. Readers of
32 * the domain list must either take cpus_read_lock(), or rely on an RCU
33 * read-side critical section, to avoid observing concurrent modification.
34 * All writers take this mutex:
35 */
36 static DEFINE_MUTEX(domain_list_lock);
37
38 /*
39 * The cached resctrl_pqr_state is strictly per CPU and can never be
40 * updated from a remote CPU. Functions which modify the state
41 * are called with interrupts disabled and no preemption, which
42 * is sufficient for the protection.
43 */
44 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state);
45
46 /*
47 * Used to store the max resource name width and max resource data width
48 * to display the schemata in a tabular format
49 */
50 int max_name_width, max_data_width;
51
52 /*
53 * Global boolean for rdt_alloc which is true if any
54 * resource allocation is enabled.
55 */
56 bool rdt_alloc_capable;
57
58 static void mba_wrmsr_intel(struct msr_param *m);
59 static void cat_wrmsr(struct msr_param *m);
60 static void mba_wrmsr_amd(struct msr_param *m);
61
62 #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains)
63 #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains)
64
65 struct rdt_hw_resource rdt_resources_all[] = {
66 [RDT_RESOURCE_L3] =
67 {
68 .r_resctrl = {
69 .rid = RDT_RESOURCE_L3,
70 .name = "L3",
71 .ctrl_scope = RESCTRL_L3_CACHE,
72 .mon_scope = RESCTRL_L3_CACHE,
73 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3),
74 .mon_domains = mon_domain_init(RDT_RESOURCE_L3),
75 .parse_ctrlval = parse_cbm,
76 .format_str = "%d=%0*x",
77 .fflags = RFTYPE_RES_CACHE,
78 },
79 .msr_base = MSR_IA32_L3_CBM_BASE,
80 .msr_update = cat_wrmsr,
81 },
82 [RDT_RESOURCE_L2] =
83 {
84 .r_resctrl = {
85 .rid = RDT_RESOURCE_L2,
86 .name = "L2",
87 .ctrl_scope = RESCTRL_L2_CACHE,
88 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2),
89 .parse_ctrlval = parse_cbm,
90 .format_str = "%d=%0*x",
91 .fflags = RFTYPE_RES_CACHE,
92 },
93 .msr_base = MSR_IA32_L2_CBM_BASE,
94 .msr_update = cat_wrmsr,
95 },
96 [RDT_RESOURCE_MBA] =
97 {
98 .r_resctrl = {
99 .rid = RDT_RESOURCE_MBA,
100 .name = "MB",
101 .ctrl_scope = RESCTRL_L3_CACHE,
102 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA),
103 .parse_ctrlval = parse_bw,
104 .format_str = "%d=%*u",
105 .fflags = RFTYPE_RES_MB,
106 },
107 },
108 [RDT_RESOURCE_SMBA] =
109 {
110 .r_resctrl = {
111 .rid = RDT_RESOURCE_SMBA,
112 .name = "SMBA",
113 .ctrl_scope = RESCTRL_L3_CACHE,
114 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA),
115 .parse_ctrlval = parse_bw,
116 .format_str = "%d=%*u",
117 .fflags = RFTYPE_RES_MB,
118 },
119 },
120 };
121
resctrl_arch_system_num_rmid_idx(void)122 u32 resctrl_arch_system_num_rmid_idx(void)
123 {
124 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
125
126 /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */
127 return r->num_rmid;
128 }
129
130 /*
131 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
132 * as they do not have CPUID enumeration support for Cache allocation.
133 * The check for Vendor/Family/Model is not enough to guarantee that
134 * the MSRs won't #GP fault because only the following SKUs support
135 * CAT:
136 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
137 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
138 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
139 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
140 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
141 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
142 *
143 * Probe by trying to write the first of the L3 cache mask registers
144 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
145 * is always 20 on hsw server parts. The minimum cache bitmask length
146 * allowed for HSW server is always 2 bits. Hardcode all of them.
147 */
cache_alloc_hsw_probe(void)148 static inline void cache_alloc_hsw_probe(void)
149 {
150 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
151 struct rdt_resource *r = &hw_res->r_resctrl;
152 u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0;
153
154 if (wrmsrl_safe(MSR_IA32_L3_CBM_BASE, max_cbm))
155 return;
156
157 rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
158
159 /* If all the bits were set in MSR, return success */
160 if (l3_cbm_0 != max_cbm)
161 return;
162
163 hw_res->num_closid = 4;
164 r->default_ctrl = max_cbm;
165 r->cache.cbm_len = 20;
166 r->cache.shareable_bits = 0xc0000;
167 r->cache.min_cbm_bits = 2;
168 r->cache.arch_has_sparse_bitmasks = false;
169 r->alloc_capable = true;
170
171 rdt_alloc_capable = true;
172 }
173
is_mba_sc(struct rdt_resource * r)174 bool is_mba_sc(struct rdt_resource *r)
175 {
176 if (!r)
177 return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc;
178
179 /*
180 * The software controller support is only applicable to MBA resource.
181 * Make sure to check for resource type.
182 */
183 if (r->rid != RDT_RESOURCE_MBA)
184 return false;
185
186 return r->membw.mba_sc;
187 }
188
189 /*
190 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
191 * exposed to user interface and the h/w understandable delay values.
192 *
193 * The non-linear delay values have the granularity of power of two
194 * and also the h/w does not guarantee a curve for configured delay
195 * values vs. actual b/w enforced.
196 * Hence we need a mapping that is pre calibrated so the user can
197 * express the memory b/w as a percentage value.
198 */
rdt_get_mb_table(struct rdt_resource * r)199 static inline bool rdt_get_mb_table(struct rdt_resource *r)
200 {
201 /*
202 * There are no Intel SKUs as of now to support non-linear delay.
203 */
204 pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
205 boot_cpu_data.x86, boot_cpu_data.x86_model);
206
207 return false;
208 }
209
__get_mem_config_intel(struct rdt_resource * r)210 static __init bool __get_mem_config_intel(struct rdt_resource *r)
211 {
212 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
213 union cpuid_0x10_3_eax eax;
214 union cpuid_0x10_x_edx edx;
215 u32 ebx, ecx, max_delay;
216
217 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
218 hw_res->num_closid = edx.split.cos_max + 1;
219 max_delay = eax.split.max_delay + 1;
220 r->default_ctrl = MAX_MBA_BW;
221 r->membw.arch_needs_linear = true;
222 if (ecx & MBA_IS_LINEAR) {
223 r->membw.delay_linear = true;
224 r->membw.min_bw = MAX_MBA_BW - max_delay;
225 r->membw.bw_gran = MAX_MBA_BW - max_delay;
226 } else {
227 if (!rdt_get_mb_table(r))
228 return false;
229 r->membw.arch_needs_linear = false;
230 }
231 r->data_width = 3;
232
233 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA))
234 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD;
235 else
236 r->membw.throttle_mode = THREAD_THROTTLE_MAX;
237
238 resctrl_file_fflags_init("thread_throttle_mode",
239 RFTYPE_CTRL_INFO | RFTYPE_RES_MB);
240
241 r->alloc_capable = true;
242
243 return true;
244 }
245
__rdt_get_mem_config_amd(struct rdt_resource * r)246 static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r)
247 {
248 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
249 u32 eax, ebx, ecx, edx, subleaf;
250
251 /*
252 * Query CPUID_Fn80000020_EDX_x01 for MBA and
253 * CPUID_Fn80000020_EDX_x02 for SMBA
254 */
255 subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1;
256
257 cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx);
258 hw_res->num_closid = edx + 1;
259 r->default_ctrl = 1 << eax;
260
261 /* AMD does not use delay */
262 r->membw.delay_linear = false;
263 r->membw.arch_needs_linear = false;
264
265 /*
266 * AMD does not use memory delay throttle model to control
267 * the allocation like Intel does.
268 */
269 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED;
270 r->membw.min_bw = 0;
271 r->membw.bw_gran = 1;
272 /* Max value is 2048, Data width should be 4 in decimal */
273 r->data_width = 4;
274
275 r->alloc_capable = true;
276
277 return true;
278 }
279
rdt_get_cache_alloc_cfg(int idx,struct rdt_resource * r)280 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
281 {
282 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
283 union cpuid_0x10_1_eax eax;
284 union cpuid_0x10_x_ecx ecx;
285 union cpuid_0x10_x_edx edx;
286 u32 ebx;
287
288 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full);
289 hw_res->num_closid = edx.split.cos_max + 1;
290 r->cache.cbm_len = eax.split.cbm_len + 1;
291 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
292 r->cache.shareable_bits = ebx & r->default_ctrl;
293 r->data_width = (r->cache.cbm_len + 3) / 4;
294 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
295 r->cache.arch_has_sparse_bitmasks = ecx.split.noncont;
296 r->alloc_capable = true;
297 }
298
rdt_get_cdp_config(int level)299 static void rdt_get_cdp_config(int level)
300 {
301 /*
302 * By default, CDP is disabled. CDP can be enabled by mount parameter
303 * "cdp" during resctrl file system mount time.
304 */
305 rdt_resources_all[level].cdp_enabled = false;
306 rdt_resources_all[level].r_resctrl.cdp_capable = true;
307 }
308
rdt_get_cdp_l3_config(void)309 static void rdt_get_cdp_l3_config(void)
310 {
311 rdt_get_cdp_config(RDT_RESOURCE_L3);
312 }
313
rdt_get_cdp_l2_config(void)314 static void rdt_get_cdp_l2_config(void)
315 {
316 rdt_get_cdp_config(RDT_RESOURCE_L2);
317 }
318
mba_wrmsr_amd(struct msr_param * m)319 static void mba_wrmsr_amd(struct msr_param *m)
320 {
321 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom);
322 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
323 unsigned int i;
324
325 for (i = m->low; i < m->high; i++)
326 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
327 }
328
329 /*
330 * Map the memory b/w percentage value to delay values
331 * that can be written to QOS_MSRs.
332 * There are currently no SKUs which support non linear delay values.
333 */
delay_bw_map(unsigned long bw,struct rdt_resource * r)334 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
335 {
336 if (r->membw.delay_linear)
337 return MAX_MBA_BW - bw;
338
339 pr_warn_once("Non Linear delay-bw map not supported but queried\n");
340 return r->default_ctrl;
341 }
342
mba_wrmsr_intel(struct msr_param * m)343 static void mba_wrmsr_intel(struct msr_param *m)
344 {
345 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom);
346 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
347 unsigned int i;
348
349 /* Write the delay values for mba. */
350 for (i = m->low; i < m->high; i++)
351 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res));
352 }
353
cat_wrmsr(struct msr_param * m)354 static void cat_wrmsr(struct msr_param *m)
355 {
356 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom);
357 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
358 unsigned int i;
359
360 for (i = m->low; i < m->high; i++)
361 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
362 }
363
get_ctrl_domain_from_cpu(int cpu,struct rdt_resource * r)364 struct rdt_ctrl_domain *get_ctrl_domain_from_cpu(int cpu, struct rdt_resource *r)
365 {
366 struct rdt_ctrl_domain *d;
367
368 lockdep_assert_cpus_held();
369
370 list_for_each_entry(d, &r->ctrl_domains, hdr.list) {
371 /* Find the domain that contains this CPU */
372 if (cpumask_test_cpu(cpu, &d->hdr.cpu_mask))
373 return d;
374 }
375
376 return NULL;
377 }
378
get_mon_domain_from_cpu(int cpu,struct rdt_resource * r)379 struct rdt_mon_domain *get_mon_domain_from_cpu(int cpu, struct rdt_resource *r)
380 {
381 struct rdt_mon_domain *d;
382
383 lockdep_assert_cpus_held();
384
385 list_for_each_entry(d, &r->mon_domains, hdr.list) {
386 /* Find the domain that contains this CPU */
387 if (cpumask_test_cpu(cpu, &d->hdr.cpu_mask))
388 return d;
389 }
390
391 return NULL;
392 }
393
resctrl_arch_get_num_closid(struct rdt_resource * r)394 u32 resctrl_arch_get_num_closid(struct rdt_resource *r)
395 {
396 return resctrl_to_arch_res(r)->num_closid;
397 }
398
rdt_ctrl_update(void * arg)399 void rdt_ctrl_update(void *arg)
400 {
401 struct rdt_hw_resource *hw_res;
402 struct msr_param *m = arg;
403
404 hw_res = resctrl_to_arch_res(m->res);
405 hw_res->msr_update(m);
406 }
407
408 /*
409 * rdt_find_domain - Search for a domain id in a resource domain list.
410 *
411 * Search the domain list to find the domain id. If the domain id is
412 * found, return the domain. NULL otherwise. If the domain id is not
413 * found (and NULL returned) then the first domain with id bigger than
414 * the input id can be returned to the caller via @pos.
415 */
rdt_find_domain(struct list_head * h,int id,struct list_head ** pos)416 struct rdt_domain_hdr *rdt_find_domain(struct list_head *h, int id,
417 struct list_head **pos)
418 {
419 struct rdt_domain_hdr *d;
420 struct list_head *l;
421
422 list_for_each(l, h) {
423 d = list_entry(l, struct rdt_domain_hdr, list);
424 /* When id is found, return its domain. */
425 if (id == d->id)
426 return d;
427 /* Stop searching when finding id's position in sorted list. */
428 if (id < d->id)
429 break;
430 }
431
432 if (pos)
433 *pos = l;
434
435 return NULL;
436 }
437
setup_default_ctrlval(struct rdt_resource * r,u32 * dc)438 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc)
439 {
440 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
441 int i;
442
443 /*
444 * Initialize the Control MSRs to having no control.
445 * For Cache Allocation: Set all bits in cbm
446 * For Memory Allocation: Set b/w requested to 100%
447 */
448 for (i = 0; i < hw_res->num_closid; i++, dc++)
449 *dc = r->default_ctrl;
450 }
451
ctrl_domain_free(struct rdt_hw_ctrl_domain * hw_dom)452 static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom)
453 {
454 kfree(hw_dom->ctrl_val);
455 kfree(hw_dom);
456 }
457
mon_domain_free(struct rdt_hw_mon_domain * hw_dom)458 static void mon_domain_free(struct rdt_hw_mon_domain *hw_dom)
459 {
460 kfree(hw_dom->arch_mbm_total);
461 kfree(hw_dom->arch_mbm_local);
462 kfree(hw_dom);
463 }
464
domain_setup_ctrlval(struct rdt_resource * r,struct rdt_ctrl_domain * d)465 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d)
466 {
467 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d);
468 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
469 struct msr_param m;
470 u32 *dc;
471
472 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val),
473 GFP_KERNEL);
474 if (!dc)
475 return -ENOMEM;
476
477 hw_dom->ctrl_val = dc;
478 setup_default_ctrlval(r, dc);
479
480 m.res = r;
481 m.dom = d;
482 m.low = 0;
483 m.high = hw_res->num_closid;
484 hw_res->msr_update(&m);
485 return 0;
486 }
487
488 /**
489 * arch_domain_mbm_alloc() - Allocate arch private storage for the MBM counters
490 * @num_rmid: The size of the MBM counter array
491 * @hw_dom: The domain that owns the allocated arrays
492 */
arch_domain_mbm_alloc(u32 num_rmid,struct rdt_hw_mon_domain * hw_dom)493 static int arch_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_mon_domain *hw_dom)
494 {
495 size_t tsize;
496
497 if (is_mbm_total_enabled()) {
498 tsize = sizeof(*hw_dom->arch_mbm_total);
499 hw_dom->arch_mbm_total = kcalloc(num_rmid, tsize, GFP_KERNEL);
500 if (!hw_dom->arch_mbm_total)
501 return -ENOMEM;
502 }
503 if (is_mbm_local_enabled()) {
504 tsize = sizeof(*hw_dom->arch_mbm_local);
505 hw_dom->arch_mbm_local = kcalloc(num_rmid, tsize, GFP_KERNEL);
506 if (!hw_dom->arch_mbm_local) {
507 kfree(hw_dom->arch_mbm_total);
508 hw_dom->arch_mbm_total = NULL;
509 return -ENOMEM;
510 }
511 }
512
513 return 0;
514 }
515
get_domain_id_from_scope(int cpu,enum resctrl_scope scope)516 static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope)
517 {
518 switch (scope) {
519 case RESCTRL_L2_CACHE:
520 case RESCTRL_L3_CACHE:
521 return get_cpu_cacheinfo_id(cpu, scope);
522 case RESCTRL_L3_NODE:
523 return cpu_to_node(cpu);
524 default:
525 break;
526 }
527
528 return -EINVAL;
529 }
530
domain_add_cpu_ctrl(int cpu,struct rdt_resource * r)531 static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r)
532 {
533 int id = get_domain_id_from_scope(cpu, r->ctrl_scope);
534 struct rdt_hw_ctrl_domain *hw_dom;
535 struct list_head *add_pos = NULL;
536 struct rdt_domain_hdr *hdr;
537 struct rdt_ctrl_domain *d;
538 int err;
539
540 lockdep_assert_held(&domain_list_lock);
541
542 if (id < 0) {
543 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n",
544 cpu, r->ctrl_scope, r->name);
545 return;
546 }
547
548 hdr = rdt_find_domain(&r->ctrl_domains, id, &add_pos);
549 if (hdr) {
550 if (WARN_ON_ONCE(hdr->type != RESCTRL_CTRL_DOMAIN))
551 return;
552 d = container_of(hdr, struct rdt_ctrl_domain, hdr);
553
554 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
555 if (r->cache.arch_has_per_cpu_cfg)
556 rdt_domain_reconfigure_cdp(r);
557 return;
558 }
559
560 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu));
561 if (!hw_dom)
562 return;
563
564 d = &hw_dom->d_resctrl;
565 d->hdr.id = id;
566 d->hdr.type = RESCTRL_CTRL_DOMAIN;
567 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
568
569 rdt_domain_reconfigure_cdp(r);
570
571 if (domain_setup_ctrlval(r, d)) {
572 ctrl_domain_free(hw_dom);
573 return;
574 }
575
576 list_add_tail_rcu(&d->hdr.list, add_pos);
577
578 err = resctrl_online_ctrl_domain(r, d);
579 if (err) {
580 list_del_rcu(&d->hdr.list);
581 synchronize_rcu();
582 ctrl_domain_free(hw_dom);
583 }
584 }
585
domain_add_cpu_mon(int cpu,struct rdt_resource * r)586 static void domain_add_cpu_mon(int cpu, struct rdt_resource *r)
587 {
588 int id = get_domain_id_from_scope(cpu, r->mon_scope);
589 struct list_head *add_pos = NULL;
590 struct rdt_hw_mon_domain *hw_dom;
591 struct rdt_domain_hdr *hdr;
592 struct rdt_mon_domain *d;
593 int err;
594
595 lockdep_assert_held(&domain_list_lock);
596
597 if (id < 0) {
598 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n",
599 cpu, r->mon_scope, r->name);
600 return;
601 }
602
603 hdr = rdt_find_domain(&r->mon_domains, id, &add_pos);
604 if (hdr) {
605 if (WARN_ON_ONCE(hdr->type != RESCTRL_MON_DOMAIN))
606 return;
607 d = container_of(hdr, struct rdt_mon_domain, hdr);
608
609 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
610 return;
611 }
612
613 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu));
614 if (!hw_dom)
615 return;
616
617 d = &hw_dom->d_resctrl;
618 d->hdr.id = id;
619 d->hdr.type = RESCTRL_MON_DOMAIN;
620 d->ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);
621 if (!d->ci) {
622 pr_warn_once("Can't find L3 cache for CPU:%d resource %s\n", cpu, r->name);
623 mon_domain_free(hw_dom);
624 return;
625 }
626 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
627
628 arch_mon_domain_online(r, d);
629
630 if (arch_domain_mbm_alloc(r->num_rmid, hw_dom)) {
631 mon_domain_free(hw_dom);
632 return;
633 }
634
635 list_add_tail_rcu(&d->hdr.list, add_pos);
636
637 err = resctrl_online_mon_domain(r, d);
638 if (err) {
639 list_del_rcu(&d->hdr.list);
640 synchronize_rcu();
641 mon_domain_free(hw_dom);
642 }
643 }
644
domain_add_cpu(int cpu,struct rdt_resource * r)645 static void domain_add_cpu(int cpu, struct rdt_resource *r)
646 {
647 if (r->alloc_capable)
648 domain_add_cpu_ctrl(cpu, r);
649 if (r->mon_capable)
650 domain_add_cpu_mon(cpu, r);
651 }
652
domain_remove_cpu_ctrl(int cpu,struct rdt_resource * r)653 static void domain_remove_cpu_ctrl(int cpu, struct rdt_resource *r)
654 {
655 int id = get_domain_id_from_scope(cpu, r->ctrl_scope);
656 struct rdt_hw_ctrl_domain *hw_dom;
657 struct rdt_domain_hdr *hdr;
658 struct rdt_ctrl_domain *d;
659
660 lockdep_assert_held(&domain_list_lock);
661
662 if (id < 0) {
663 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n",
664 cpu, r->ctrl_scope, r->name);
665 return;
666 }
667
668 hdr = rdt_find_domain(&r->ctrl_domains, id, NULL);
669 if (!hdr) {
670 pr_warn("Can't find control domain for id=%d for CPU %d for resource %s\n",
671 id, cpu, r->name);
672 return;
673 }
674
675 if (WARN_ON_ONCE(hdr->type != RESCTRL_CTRL_DOMAIN))
676 return;
677
678 d = container_of(hdr, struct rdt_ctrl_domain, hdr);
679 hw_dom = resctrl_to_arch_ctrl_dom(d);
680
681 cpumask_clear_cpu(cpu, &d->hdr.cpu_mask);
682 if (cpumask_empty(&d->hdr.cpu_mask)) {
683 resctrl_offline_ctrl_domain(r, d);
684 list_del_rcu(&d->hdr.list);
685 synchronize_rcu();
686
687 /*
688 * rdt_ctrl_domain "d" is going to be freed below, so clear
689 * its pointer from pseudo_lock_region struct.
690 */
691 if (d->plr)
692 d->plr->d = NULL;
693 ctrl_domain_free(hw_dom);
694
695 return;
696 }
697 }
698
domain_remove_cpu_mon(int cpu,struct rdt_resource * r)699 static void domain_remove_cpu_mon(int cpu, struct rdt_resource *r)
700 {
701 int id = get_domain_id_from_scope(cpu, r->mon_scope);
702 struct rdt_hw_mon_domain *hw_dom;
703 struct rdt_domain_hdr *hdr;
704 struct rdt_mon_domain *d;
705
706 lockdep_assert_held(&domain_list_lock);
707
708 if (id < 0) {
709 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n",
710 cpu, r->mon_scope, r->name);
711 return;
712 }
713
714 hdr = rdt_find_domain(&r->mon_domains, id, NULL);
715 if (!hdr) {
716 pr_warn("Can't find monitor domain for id=%d for CPU %d for resource %s\n",
717 id, cpu, r->name);
718 return;
719 }
720
721 if (WARN_ON_ONCE(hdr->type != RESCTRL_MON_DOMAIN))
722 return;
723
724 d = container_of(hdr, struct rdt_mon_domain, hdr);
725 hw_dom = resctrl_to_arch_mon_dom(d);
726
727 cpumask_clear_cpu(cpu, &d->hdr.cpu_mask);
728 if (cpumask_empty(&d->hdr.cpu_mask)) {
729 resctrl_offline_mon_domain(r, d);
730 list_del_rcu(&d->hdr.list);
731 synchronize_rcu();
732 mon_domain_free(hw_dom);
733
734 return;
735 }
736 }
737
domain_remove_cpu(int cpu,struct rdt_resource * r)738 static void domain_remove_cpu(int cpu, struct rdt_resource *r)
739 {
740 if (r->alloc_capable)
741 domain_remove_cpu_ctrl(cpu, r);
742 if (r->mon_capable)
743 domain_remove_cpu_mon(cpu, r);
744 }
745
clear_closid_rmid(int cpu)746 static void clear_closid_rmid(int cpu)
747 {
748 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
749
750 state->default_closid = RESCTRL_RESERVED_CLOSID;
751 state->default_rmid = RESCTRL_RESERVED_RMID;
752 state->cur_closid = RESCTRL_RESERVED_CLOSID;
753 state->cur_rmid = RESCTRL_RESERVED_RMID;
754 wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID,
755 RESCTRL_RESERVED_CLOSID);
756 }
757
resctrl_arch_online_cpu(unsigned int cpu)758 static int resctrl_arch_online_cpu(unsigned int cpu)
759 {
760 struct rdt_resource *r;
761
762 mutex_lock(&domain_list_lock);
763 for_each_capable_rdt_resource(r)
764 domain_add_cpu(cpu, r);
765 mutex_unlock(&domain_list_lock);
766
767 clear_closid_rmid(cpu);
768 resctrl_online_cpu(cpu);
769
770 return 0;
771 }
772
resctrl_arch_offline_cpu(unsigned int cpu)773 static int resctrl_arch_offline_cpu(unsigned int cpu)
774 {
775 struct rdt_resource *r;
776
777 resctrl_offline_cpu(cpu);
778
779 mutex_lock(&domain_list_lock);
780 for_each_capable_rdt_resource(r)
781 domain_remove_cpu(cpu, r);
782 mutex_unlock(&domain_list_lock);
783
784 clear_closid_rmid(cpu);
785
786 return 0;
787 }
788
789 /*
790 * Choose a width for the resource name and resource data based on the
791 * resource that has widest name and cbm.
792 */
rdt_init_padding(void)793 static __init void rdt_init_padding(void)
794 {
795 struct rdt_resource *r;
796
797 for_each_alloc_capable_rdt_resource(r) {
798 if (r->data_width > max_data_width)
799 max_data_width = r->data_width;
800 }
801 }
802
803 enum {
804 RDT_FLAG_CMT,
805 RDT_FLAG_MBM_TOTAL,
806 RDT_FLAG_MBM_LOCAL,
807 RDT_FLAG_L3_CAT,
808 RDT_FLAG_L3_CDP,
809 RDT_FLAG_L2_CAT,
810 RDT_FLAG_L2_CDP,
811 RDT_FLAG_MBA,
812 RDT_FLAG_SMBA,
813 RDT_FLAG_BMEC,
814 };
815
816 #define RDT_OPT(idx, n, f) \
817 [idx] = { \
818 .name = n, \
819 .flag = f \
820 }
821
822 struct rdt_options {
823 char *name;
824 int flag;
825 bool force_off, force_on;
826 };
827
828 static struct rdt_options rdt_options[] __initdata = {
829 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC),
830 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
831 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
832 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3),
833 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3),
834 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2),
835 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2),
836 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
837 RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA),
838 RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC),
839 };
840 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
841
set_rdt_options(char * str)842 static int __init set_rdt_options(char *str)
843 {
844 struct rdt_options *o;
845 bool force_off;
846 char *tok;
847
848 if (*str == '=')
849 str++;
850 while ((tok = strsep(&str, ",")) != NULL) {
851 force_off = *tok == '!';
852 if (force_off)
853 tok++;
854 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
855 if (strcmp(tok, o->name) == 0) {
856 if (force_off)
857 o->force_off = true;
858 else
859 o->force_on = true;
860 break;
861 }
862 }
863 }
864 return 1;
865 }
866 __setup("rdt", set_rdt_options);
867
rdt_cpu_has(int flag)868 bool __init rdt_cpu_has(int flag)
869 {
870 bool ret = boot_cpu_has(flag);
871 struct rdt_options *o;
872
873 if (!ret)
874 return ret;
875
876 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
877 if (flag == o->flag) {
878 if (o->force_off)
879 ret = false;
880 if (o->force_on)
881 ret = true;
882 break;
883 }
884 }
885 return ret;
886 }
887
get_mem_config(void)888 static __init bool get_mem_config(void)
889 {
890 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA];
891
892 if (!rdt_cpu_has(X86_FEATURE_MBA))
893 return false;
894
895 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
896 return __get_mem_config_intel(&hw_res->r_resctrl);
897 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
898 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
899
900 return false;
901 }
902
get_slow_mem_config(void)903 static __init bool get_slow_mem_config(void)
904 {
905 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA];
906
907 if (!rdt_cpu_has(X86_FEATURE_SMBA))
908 return false;
909
910 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
911 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
912
913 return false;
914 }
915
get_rdt_alloc_resources(void)916 static __init bool get_rdt_alloc_resources(void)
917 {
918 struct rdt_resource *r;
919 bool ret = false;
920
921 if (rdt_alloc_capable)
922 return true;
923
924 if (!boot_cpu_has(X86_FEATURE_RDT_A))
925 return false;
926
927 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
928 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
929 rdt_get_cache_alloc_cfg(1, r);
930 if (rdt_cpu_has(X86_FEATURE_CDP_L3))
931 rdt_get_cdp_l3_config();
932 ret = true;
933 }
934 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
935 /* CPUID 0x10.2 fields are same format at 0x10.1 */
936 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl;
937 rdt_get_cache_alloc_cfg(2, r);
938 if (rdt_cpu_has(X86_FEATURE_CDP_L2))
939 rdt_get_cdp_l2_config();
940 ret = true;
941 }
942
943 if (get_mem_config())
944 ret = true;
945
946 if (get_slow_mem_config())
947 ret = true;
948
949 return ret;
950 }
951
get_rdt_mon_resources(void)952 static __init bool get_rdt_mon_resources(void)
953 {
954 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
955
956 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
957 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID);
958 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL))
959 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID);
960 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))
961 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID);
962
963 if (!rdt_mon_features)
964 return false;
965
966 if (is_mbm_local_enabled())
967 mba_mbps_default_event = QOS_L3_MBM_LOCAL_EVENT_ID;
968 else if (is_mbm_total_enabled())
969 mba_mbps_default_event = QOS_L3_MBM_TOTAL_EVENT_ID;
970
971 return !rdt_get_mon_l3_config(r);
972 }
973
__check_quirks_intel(void)974 static __init void __check_quirks_intel(void)
975 {
976 switch (boot_cpu_data.x86_vfm) {
977 case INTEL_HASWELL_X:
978 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
979 cache_alloc_hsw_probe();
980 break;
981 case INTEL_SKYLAKE_X:
982 if (boot_cpu_data.x86_stepping <= 4)
983 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
984 else
985 set_rdt_options("!l3cat");
986 fallthrough;
987 case INTEL_BROADWELL_X:
988 intel_rdt_mbm_apply_quirk();
989 break;
990 }
991 }
992
check_quirks(void)993 static __init void check_quirks(void)
994 {
995 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
996 __check_quirks_intel();
997 }
998
get_rdt_resources(void)999 static __init bool get_rdt_resources(void)
1000 {
1001 rdt_alloc_capable = get_rdt_alloc_resources();
1002 rdt_mon_capable = get_rdt_mon_resources();
1003
1004 return (rdt_mon_capable || rdt_alloc_capable);
1005 }
1006
rdt_init_res_defs_intel(void)1007 static __init void rdt_init_res_defs_intel(void)
1008 {
1009 struct rdt_hw_resource *hw_res;
1010 struct rdt_resource *r;
1011
1012 for_each_rdt_resource(r) {
1013 hw_res = resctrl_to_arch_res(r);
1014
1015 if (r->rid == RDT_RESOURCE_L3 ||
1016 r->rid == RDT_RESOURCE_L2) {
1017 r->cache.arch_has_per_cpu_cfg = false;
1018 r->cache.min_cbm_bits = 1;
1019 } else if (r->rid == RDT_RESOURCE_MBA) {
1020 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;
1021 hw_res->msr_update = mba_wrmsr_intel;
1022 }
1023 }
1024 }
1025
rdt_init_res_defs_amd(void)1026 static __init void rdt_init_res_defs_amd(void)
1027 {
1028 struct rdt_hw_resource *hw_res;
1029 struct rdt_resource *r;
1030
1031 for_each_rdt_resource(r) {
1032 hw_res = resctrl_to_arch_res(r);
1033
1034 if (r->rid == RDT_RESOURCE_L3 ||
1035 r->rid == RDT_RESOURCE_L2) {
1036 r->cache.arch_has_sparse_bitmasks = true;
1037 r->cache.arch_has_per_cpu_cfg = true;
1038 r->cache.min_cbm_bits = 0;
1039 } else if (r->rid == RDT_RESOURCE_MBA) {
1040 hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
1041 hw_res->msr_update = mba_wrmsr_amd;
1042 } else if (r->rid == RDT_RESOURCE_SMBA) {
1043 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE;
1044 hw_res->msr_update = mba_wrmsr_amd;
1045 }
1046 }
1047 }
1048
rdt_init_res_defs(void)1049 static __init void rdt_init_res_defs(void)
1050 {
1051 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1052 rdt_init_res_defs_intel();
1053 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1054 rdt_init_res_defs_amd();
1055 }
1056
1057 static enum cpuhp_state rdt_online;
1058
1059 /* Runs once on the BSP during boot. */
resctrl_cpu_detect(struct cpuinfo_x86 * c)1060 void resctrl_cpu_detect(struct cpuinfo_x86 *c)
1061 {
1062 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
1063 c->x86_cache_max_rmid = -1;
1064 c->x86_cache_occ_scale = -1;
1065 c->x86_cache_mbm_width_offset = -1;
1066 return;
1067 }
1068
1069 /* will be overridden if occupancy monitoring exists */
1070 c->x86_cache_max_rmid = cpuid_ebx(0xf);
1071
1072 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
1073 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
1074 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
1075 u32 eax, ebx, ecx, edx;
1076
1077 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
1078 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
1079
1080 c->x86_cache_max_rmid = ecx;
1081 c->x86_cache_occ_scale = ebx;
1082 c->x86_cache_mbm_width_offset = eax & 0xff;
1083
1084 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
1085 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
1086 }
1087 }
1088
resctrl_late_init(void)1089 static int __init resctrl_late_init(void)
1090 {
1091 struct rdt_resource *r;
1092 int state, ret;
1093
1094 /*
1095 * Initialize functions(or definitions) that are different
1096 * between vendors here.
1097 */
1098 rdt_init_res_defs();
1099
1100 check_quirks();
1101
1102 if (!get_rdt_resources())
1103 return -ENODEV;
1104
1105 rdt_init_padding();
1106
1107 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1108 "x86/resctrl/cat:online:",
1109 resctrl_arch_online_cpu,
1110 resctrl_arch_offline_cpu);
1111 if (state < 0)
1112 return state;
1113
1114 ret = rdtgroup_init();
1115 if (ret) {
1116 cpuhp_remove_state(state);
1117 return ret;
1118 }
1119 rdt_online = state;
1120
1121 for_each_alloc_capable_rdt_resource(r)
1122 pr_info("%s allocation detected\n", r->name);
1123
1124 for_each_mon_capable_rdt_resource(r)
1125 pr_info("%s monitoring detected\n", r->name);
1126
1127 return 0;
1128 }
1129
1130 late_initcall(resctrl_late_init);
1131
resctrl_exit(void)1132 static void __exit resctrl_exit(void)
1133 {
1134 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
1135
1136 cpuhp_remove_state(rdt_online);
1137
1138 rdtgroup_exit();
1139
1140 if (r->mon_capable)
1141 rdt_put_mon_l3_config();
1142 }
1143
1144 __exitcall(resctrl_exit);
1145