1 /*
2 * Copyright © 2020 Valve Corporation
3 *
4 * based on amdgpu winsys.
5 * Copyright © 2016 Red Hat.
6 * Copyright © 2016 Bas Nieuwenhuizen
7 *
8 * SPDX-License-Identifier: MIT
9 */
10 #include "radv_null_winsys_public.h"
11
12 #include "util/u_string.h"
13 #include "radv_null_bo.h"
14 #include "radv_null_cs.h"
15 #include "vk_sync_dummy.h"
16
17 /* Hardcode some GPU info that are needed for the driver or for some tools. */
18 static const struct {
19 uint32_t pci_id;
20 uint32_t num_render_backends;
21 bool has_dedicated_vram;
22 } pci_ids[] = {
23 /* clang-format off */
24 [CHIP_TAHITI] = {0x6780, 8, true},
25 [CHIP_PITCAIRN] = {0x6800, 8, true},
26 [CHIP_VERDE] = {0x6820, 4, true},
27 [CHIP_OLAND] = {0x6060, 2, true},
28 [CHIP_HAINAN] = {0x6660, 2, true},
29 [CHIP_BONAIRE] = {0x6640, 4, true},
30 [CHIP_KAVERI] = {0x1304, 2, false},
31 [CHIP_KABINI] = {0x9830, 2, false},
32 [CHIP_HAWAII] = {0x67A0, 16, true},
33 [CHIP_TONGA] = {0x6920, 8, true},
34 [CHIP_ICELAND] = {0x6900, 2, true},
35 [CHIP_CARRIZO] = {0x9870, 2, false},
36 [CHIP_FIJI] = {0x7300, 16, true},
37 [CHIP_STONEY] = {0x98E4, 2, false},
38 [CHIP_POLARIS10] = {0x67C0, 8, true},
39 [CHIP_POLARIS11] = {0x67E0, 4, true},
40 [CHIP_POLARIS12] = {0x6980, 4, true},
41 [CHIP_VEGAM] = {0x694C, 4, true},
42 [CHIP_VEGA10] = {0x6860, 16, true},
43 [CHIP_VEGA12] = {0x69A0, 8, true},
44 [CHIP_VEGA20] = {0x66A0, 16, true},
45 [CHIP_RAVEN] = {0x15DD, 2, false},
46 [CHIP_RENOIR] = {0x1636, 2, false},
47 [CHIP_MI100] = {0x738C, 2, true},
48 [CHIP_NAVI10] = {0x7310, 16, true},
49 [CHIP_NAVI12] = {0x7360, 8, true},
50 [CHIP_NAVI14] = {0x7340, 8, true},
51 [CHIP_NAVI21] = {0x73A0, 16, true},
52 [CHIP_VANGOGH] = {0x163F, 8, false},
53 [CHIP_NAVI22] = {0x73C0, 8, true},
54 [CHIP_NAVI23] = {0x73E0, 8, true},
55 [CHIP_NAVI31] = {0x744C, 24, true},
56 /* clang-format on */
57 };
58
59 static void
radv_null_winsys_query_info(struct radeon_winsys * rws,struct radeon_info * gpu_info)60 radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *gpu_info)
61 {
62 const char *family = getenv("RADV_FORCE_FAMILY");
63 unsigned i;
64
65 gpu_info->gfx_level = CLASS_UNKNOWN;
66 gpu_info->family = CHIP_UNKNOWN;
67
68 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
69 if (!strcasecmp(family, ac_get_family_name(i))) {
70 /* Override family and gfx_level. */
71 gpu_info->family = i;
72 gpu_info->name = ac_get_family_name(i);
73
74 if (gpu_info->family >= CHIP_NAVI31)
75 gpu_info->gfx_level = GFX11;
76 else if (i >= CHIP_NAVI21)
77 gpu_info->gfx_level = GFX10_3;
78 else if (i >= CHIP_NAVI10)
79 gpu_info->gfx_level = GFX10;
80 else if (i >= CHIP_VEGA10)
81 gpu_info->gfx_level = GFX9;
82 else if (i >= CHIP_TONGA)
83 gpu_info->gfx_level = GFX8;
84 else if (i >= CHIP_BONAIRE)
85 gpu_info->gfx_level = GFX7;
86 else
87 gpu_info->gfx_level = GFX6;
88 }
89 }
90
91 if (gpu_info->family == CHIP_UNKNOWN) {
92 fprintf(stderr, "radv: Unknown family: %s\n", family);
93 abort();
94 }
95
96 gpu_info->pci_id = pci_ids[gpu_info->family].pci_id;
97 gpu_info->max_se = 4;
98 gpu_info->num_se = 4;
99 if (gpu_info->gfx_level >= GFX10_3)
100 gpu_info->max_waves_per_simd = 16;
101 else if (gpu_info->gfx_level >= GFX10)
102 gpu_info->max_waves_per_simd = 20;
103 else if (gpu_info->family >= CHIP_POLARIS10 && gpu_info->family <= CHIP_VEGAM)
104 gpu_info->max_waves_per_simd = 8;
105 else
106 gpu_info->max_waves_per_simd = 10;
107
108 if (gpu_info->gfx_level >= GFX10)
109 gpu_info->num_physical_sgprs_per_simd = 128 * gpu_info->max_waves_per_simd;
110 else if (gpu_info->gfx_level >= GFX8)
111 gpu_info->num_physical_sgprs_per_simd = 800;
112 else
113 gpu_info->num_physical_sgprs_per_simd = 512;
114
115 gpu_info->has_3d_cube_border_color_mipmap = true;
116 gpu_info->has_image_opcodes = true;
117
118 if (gpu_info->family == CHIP_NAVI31 || gpu_info->family == CHIP_NAVI32)
119 gpu_info->num_physical_wave64_vgprs_per_simd = 768;
120 else if (gpu_info->gfx_level >= GFX10)
121 gpu_info->num_physical_wave64_vgprs_per_simd = 512;
122 else
123 gpu_info->num_physical_wave64_vgprs_per_simd = 256;
124 gpu_info->num_simd_per_compute_unit = gpu_info->gfx_level >= GFX10 ? 2 : 4;
125 gpu_info->lds_size_per_workgroup = gpu_info->gfx_level >= GFX10 ? 128 * 1024
126 : gpu_info->gfx_level >= GFX7 ? 64 * 1024
127 : 32 * 1024;
128 gpu_info->lds_encode_granularity = gpu_info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4;
129 gpu_info->lds_alloc_granularity = gpu_info->gfx_level >= GFX10_3 ? 256 * 4 : gpu_info->lds_encode_granularity;
130 gpu_info->max_render_backends = pci_ids[gpu_info->family].num_render_backends;
131
132 gpu_info->has_dedicated_vram = pci_ids[gpu_info->family].has_dedicated_vram;
133 gpu_info->has_packed_math_16bit = gpu_info->gfx_level >= GFX9;
134
135 gpu_info->has_image_load_dcc_bug = gpu_info->family == CHIP_NAVI23 || gpu_info->family == CHIP_VANGOGH;
136
137 gpu_info->has_accelerated_dot_product =
138 gpu_info->family == CHIP_VEGA20 || (gpu_info->family >= CHIP_MI100 && gpu_info->family != CHIP_NAVI10);
139
140 gpu_info->address32_hi = gpu_info->gfx_level >= GFX9 ? 0xffff8000u : 0x0;
141
142 gpu_info->has_rbplus = gpu_info->family == CHIP_STONEY || gpu_info->gfx_level >= GFX9;
143 gpu_info->rbplus_allowed =
144 gpu_info->has_rbplus &&
145 (gpu_info->family == CHIP_STONEY || gpu_info->family == CHIP_VEGA12 || gpu_info->family == CHIP_RAVEN ||
146 gpu_info->family == CHIP_RAVEN2 || gpu_info->family == CHIP_RENOIR || gpu_info->gfx_level >= GFX10_3);
147
148 gpu_info->has_scheduled_fence_dependency = true;
149 gpu_info->has_gang_submit = true;
150 }
151
152 static const char *
radv_null_winsys_get_chip_name(struct radeon_winsys * rws)153 radv_null_winsys_get_chip_name(struct radeon_winsys *rws)
154 {
155 return "Null hardware";
156 }
157
158 static void
radv_null_winsys_destroy(struct radeon_winsys * rws)159 radv_null_winsys_destroy(struct radeon_winsys *rws)
160 {
161 FREE(rws);
162 }
163
164 static int
radv_null_winsys_get_fd(struct radeon_winsys * rws)165 radv_null_winsys_get_fd(struct radeon_winsys *rws)
166 {
167 return -1;
168 }
169
170 static const struct vk_sync_type *const *
radv_null_winsys_get_sync_types(struct radeon_winsys * rws)171 radv_null_winsys_get_sync_types(struct radeon_winsys *rws)
172 {
173 return radv_null_winsys(rws)->sync_types;
174 }
175
176 struct radeon_winsys *
radv_null_winsys_create()177 radv_null_winsys_create()
178 {
179 struct radv_null_winsys *ws;
180
181 ws = calloc(1, sizeof(struct radv_null_winsys));
182 if (!ws)
183 return NULL;
184
185 ws->base.destroy = radv_null_winsys_destroy;
186 ws->base.query_info = radv_null_winsys_query_info;
187 ws->base.get_fd = radv_null_winsys_get_fd;
188 ws->base.get_sync_types = radv_null_winsys_get_sync_types;
189 ws->base.get_chip_name = radv_null_winsys_get_chip_name;
190 radv_null_bo_init_functions(ws);
191 radv_null_cs_init_functions(ws);
192
193 ws->sync_types[0] = &vk_sync_dummy_type;
194 ws->sync_types[1] = NULL;
195 return &ws->base;
196 }
197