1 /**************************************************************************
2 *
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10
11 #include "util/u_video.h"
12
13 #include "si_pipe.h"
14 #include "radeon_vcn_enc.h"
15
16 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
17 #define RENCODE_FW_INTERFACE_MINOR_VERSION 15
18
19 #define RENCODE_IB_PARAM_CDF_DEFAULT_TABLE_BUFFER 0x00000019
20 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x0000001a
21
22 #define RENCODE_AV1_IB_PARAM_SPEC_MISC 0x00300001
23 #define RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION 0x00300002
24
25 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_END RENCODE_HEADER_INSTRUCTION_END
26 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY RENCODE_HEADER_INSTRUCTION_COPY
27 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV 0x00000005
28 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS 0x00000006
29 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER 0x00000007
30 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS 0x00000008
31 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_INFO 0x00000009
32 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS 0x0000000a
33 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS 0x0000000b
34 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS 0x0000000c
35 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE 0x0000000d
36 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU 0x0000000e
37
radeon_enc_sq_begin(struct radeon_encoder * enc)38 static void radeon_enc_sq_begin(struct radeon_encoder *enc)
39 {
40 rvcn_sq_header(&enc->cs, &enc->sq, true);
41 enc->mq_begin(enc);
42 rvcn_sq_tail(&enc->cs, &enc->sq);
43 }
44
radeon_enc_sq_encode(struct radeon_encoder * enc)45 static void radeon_enc_sq_encode(struct radeon_encoder *enc)
46 {
47 rvcn_sq_header(&enc->cs, &enc->sq, true);
48 enc->mq_encode(enc);
49 rvcn_sq_tail(&enc->cs, &enc->sq);
50 }
51
radeon_enc_sq_destroy(struct radeon_encoder * enc)52 static void radeon_enc_sq_destroy(struct radeon_encoder *enc)
53 {
54 rvcn_sq_header(&enc->cs, &enc->sq, true);
55 enc->mq_destroy(enc);
56 rvcn_sq_tail(&enc->cs, &enc->sq);
57 }
58
radeon_enc_op_preset(struct radeon_encoder * enc)59 static void radeon_enc_op_preset(struct radeon_encoder *enc)
60 {
61 uint32_t preset_mode;
62
63 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_SPEED &&
64 (!enc->enc_pic.hevc_deblock.disable_sao &&
65 (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)))
66 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
67 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
68 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
69 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_HIGH_QUALITY)
70 preset_mode = RENCODE_IB_OP_SET_HIGH_QUALITY_ENCODING_MODE;
71 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
72 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
73 else
74 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
75
76 RADEON_ENC_BEGIN(preset_mode);
77 RADEON_ENC_END();
78 }
79
radeon_enc_session_init(struct radeon_encoder * enc)80 static void radeon_enc_session_init(struct radeon_encoder *enc)
81 {
82 uint32_t av1_height = enc->enc_pic.pic_height_in_luma_samples;
83
84 switch (u_reduce_video_profile(enc->base.profile)) {
85 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
86 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
87 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
88 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
89
90 enc->enc_pic.session_init.padding_width =
91 (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2;
92 enc->enc_pic.session_init.padding_height =
93 (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2;
94 break;
95 case PIPE_VIDEO_FORMAT_HEVC:
96 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
97 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
98 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
99 enc->enc_pic.session_init.padding_width =
100 (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2;
101 enc->enc_pic.session_init.padding_height =
102 (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2;
103 break;
104 case PIPE_VIDEO_FORMAT_AV1:
105 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_AV1;
106 enc->enc_pic.session_init.aligned_picture_width =
107 align(enc->enc_pic.pic_width_in_luma_samples, 64);
108 enc->enc_pic.session_init.aligned_picture_height =
109 align(enc->enc_pic.pic_height_in_luma_samples, 16);
110 if (!(av1_height % 8) && (av1_height % 16) && !(enc->enc_pic.enable_render_size))
111 enc->enc_pic.session_init.aligned_picture_height = av1_height + 2;
112
113 enc->enc_pic.session_init.padding_width =
114 enc->enc_pic.session_init.aligned_picture_width -
115 enc->enc_pic.pic_width_in_luma_samples;
116 enc->enc_pic.session_init.padding_height =
117 enc->enc_pic.session_init.aligned_picture_height - av1_height;
118
119 if (enc->enc_pic.enable_render_size)
120 enc->enc_pic.enable_render_size =
121 (enc->enc_pic.session_init.aligned_picture_width !=
122 enc->enc_pic.render_width) ||
123 (enc->enc_pic.session_init.aligned_picture_height !=
124 enc->enc_pic.render_height);
125 break;
126 default:
127 assert(0);
128 break;
129 }
130
131 enc->enc_pic.session_init.slice_output_enabled = 0;
132 enc->enc_pic.session_init.display_remote = 0;
133 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
134 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
135
136 RADEON_ENC_BEGIN(enc->cmd.session_init);
137 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
138 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
139 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
140 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
141 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
142 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
143 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
144 RADEON_ENC_CS(enc->enc_pic.session_init.slice_output_enabled);
145 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
146 RADEON_ENC_CS(0);
147 RADEON_ENC_END();
148 }
149
150 /* for new temporal_id, sequence_num has to be incremented ahead. */
radeon_enc_av1_calculate_temporal_id(uint32_t sequence_num,uint32_t max_layer)151 static uint32_t radeon_enc_av1_calculate_temporal_id(uint32_t sequence_num,
152 uint32_t max_layer)
153 {
154 for (uint32_t i = 0; i <= max_layer; i++)
155 if (!(sequence_num % (1 << (max_layer - i))))
156 return i;
157
158 /* never come here */
159 assert(0);
160 return 0;
161 }
162
radeon_enc_av1_alloc_recon_slot(struct radeon_encoder * enc)163 static uint32_t radeon_enc_av1_alloc_recon_slot(struct radeon_encoder *enc)
164 {
165 uint32_t i;
166 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.recon_slots); i++) {
167 if(!enc->enc_pic.recon_slots[i].in_use) {
168 enc->enc_pic.recon_slots[i].in_use = true;
169 break;
170 }
171 }
172 return i;
173 }
174
redeon_enc_av1_release_recon_slot(struct radeon_encoder * enc,uint32_t index,bool is_orphaned)175 static void redeon_enc_av1_release_recon_slot(struct radeon_encoder *enc,
176 uint32_t index,
177 bool is_orphaned)
178 {
179 assert(index < (ARRAY_SIZE(enc->enc_pic.recon_slots) - 1));
180 assert(enc->enc_pic.recon_slots[index].in_use);
181
182 if (is_orphaned)
183 enc->enc_pic.recon_slots[index].is_orphaned = true;
184 else
185 enc->enc_pic.recon_slots[index].in_use = false;
186 }
187
radeon_enc_av1_alloc_curr_frame(struct radeon_encoder * enc,uint32_t frame_id,uint32_t temporal_id,uint32_t mark_long_term,void * frame_signature,enum pipe_av1_enc_frame_type frame_type)188 static uint32_t radeon_enc_av1_alloc_curr_frame(struct radeon_encoder *enc,
189 uint32_t frame_id,
190 uint32_t temporal_id,
191 uint32_t mark_long_term, /* mark it as long term reference */
192 void *frame_signature,
193 enum pipe_av1_enc_frame_type frame_type)
194 {
195 uint32_t i = 0;
196
197 assert(frame_signature);
198
199 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
200 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
201 if (!frame->in_use) {
202 frame->in_use = true;
203 frame->frame_id = frame_id;
204 frame->temporal_id = temporal_id;
205 frame->slot_id = radeon_enc_av1_alloc_recon_slot(enc);
206 frame->frame_type = frame_type;
207 frame->frame_signature = frame_signature;
208 frame->is_ltr = !!(mark_long_term);
209 if (frame->is_ltr)
210 frame->ltr_seq = enc->enc_pic.av1_ltr_seq++;
211 break;
212 }
213 }
214
215 return i;
216 }
217
radeon_enc_av1_release_ref_frame(struct radeon_encoder * enc,uint32_t index,bool is_recon_orphan)218 static void radeon_enc_av1_release_ref_frame(struct radeon_encoder *enc,
219 uint32_t index,
220 bool is_recon_orphan)
221 {
222 assert(index < (ARRAY_SIZE(enc->enc_pic.frames) - 1));
223
224 redeon_enc_av1_release_recon_slot(enc,
225 enc->enc_pic.frames[index].slot_id,
226 is_recon_orphan);
227 enc->enc_pic.frames[index].in_use = false;
228 }
229
230 /* save 1 recon slot in max temporal layer = 4 case */
radeon_enc_av1_temporal_4_extra_release(struct radeon_encoder * enc,uint32_t temporal_id)231 static void radeon_enc_av1_temporal_4_extra_release(struct radeon_encoder *enc,
232 uint32_t temporal_id)
233 {
234 uint32_t i = 0;
235
236 if (temporal_id == 0)
237 enc->enc_pic.count_last_layer = 0;
238 else if (temporal_id == 3)
239 enc->enc_pic.count_last_layer++;
240
241 /* since temporal ID = 1 picture will not be used in this
242 * temporal period, that can be released */
243 if (enc->enc_pic.count_last_layer == 4) {
244 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
245 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
246 if (frame->in_use && (frame->temporal_id == 1)) {
247 radeon_enc_av1_release_ref_frame(enc, i, false);
248 break;
249 }
250 }
251 }
252 }
253
radeon_enc_av1_pre_scan_frames(struct radeon_encoder * enc,uint32_t temporal_id)254 static void radeon_enc_av1_pre_scan_frames(struct radeon_encoder *enc,
255 uint32_t temporal_id)
256 {
257 uint32_t i = 0;
258
259 /* checking long term frames if it reached the limit, it needs to
260 * release the oldest. */
261 if (enc->enc_pic.av1_mark_long_term_reference) {
262 int cnt = 0;
263 uint32_t min_seq = (uint32_t)-1;
264 uint32_t min_seq_idx = 0;
265 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
266 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
267 if (frame->in_use && frame->is_ltr) {
268 if (frame->ltr_seq < min_seq) {
269 min_seq = frame->ltr_seq;
270 min_seq_idx = i;
271 }
272 cnt++;
273
274 /* this means some LTR ref buffer has been re-used. */
275 if (enc->enc_pic.av1_recon_frame == frame->frame_signature)
276 RVID_ERR("recon duplicated! it could refer to a wrong frame!\n");
277 }
278 }
279 /* release the frame with minimum ltr seq number (oldest),
280 * this check is happening on each frame, the total number
281 * of LTR is limited by RENCODE_VCN4_AV1_MAX_NUM_LTR.*/
282 if (cnt > RENCODE_VCN4_AV1_MAX_NUM_LTR)
283 radeon_enc_av1_release_ref_frame(enc, min_seq_idx, false);
284 }
285
286 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.recon_slots); i++) {
287 rvcn_enc_av1_recon_slot_t *slot = &enc->enc_pic.recon_slots[i];
288 if (slot->in_use && slot->is_orphaned) {
289 slot->in_use = false;
290 slot->is_orphaned = false;
291 }
292 }
293
294 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
295 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
296 if (frame->in_use) {
297 if (temporal_id < frame->temporal_id)
298 radeon_enc_av1_release_ref_frame(enc, i, false);
299 else if (temporal_id == frame->temporal_id && (!frame->is_ltr))
300 radeon_enc_av1_release_ref_frame(enc, i, true);
301 }
302 }
303 }
304
radeon_enc_av1_search_requested_reference(struct radeon_encoder * enc,uint32_t * idx)305 static bool radeon_enc_av1_search_requested_reference(
306 struct radeon_encoder *enc,
307 uint32_t *idx)
308 {
309 bool find = false;
310 /* Here is the assumption, the 3rd item of ref_frame_ctrl_l0
311 indicates which slot it needs to find in ref_frame_idx[], and
312 from ref_frame_idx to find the requested reference frame
313 in ref_list[] */
314 #define RENCODE_AV1_REF_CTRL_L0_THIRD_ITEM (0x1c0) /* 111 000 000 */
315 uint32_t marked_ref_frame_idx = (RENCODE_AV1_REF_CTRL_L0_THIRD_ITEM &
316 enc->enc_pic.av1_ref_frame_ctrl_l0) >> 6;
317 /* valid marked_ref_frame_idx > 0 */
318 if (marked_ref_frame_idx) {
319 uint32_t requested_frame_idx =
320 enc->enc_pic.av1_ref_frame_idx[marked_ref_frame_idx - 1];
321 void *request_signature = NULL;
322
323 if (requested_frame_idx >= RENCDOE_AV1_NUM_REF_FRAMES)
324 goto end;
325
326 request_signature = enc->enc_pic.av1_ref_list[requested_frame_idx];
327 for (uint32_t i = 0; i < ARRAY_SIZE((enc->enc_pic.frames)); i++) {
328 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
329 if (frame->in_use &&
330 frame->is_ltr &&
331 (request_signature == frame->frame_signature)) {
332 find = true;
333 /* increase the frame seq number after found, when it
334 * reaches the maximum limit, this found one will not
335 * be released. */
336 frame->ltr_seq = enc->enc_pic.av1_ltr_seq++;
337 *idx = i;
338 break;
339 }
340 }
341 }
342 end:
343 return find;
344 }
345
radeon_enc_av1_obtain_ref0_frame(struct radeon_encoder * enc,uint32_t temporal_id)346 static uint32_t radeon_enc_av1_obtain_ref0_frame(struct radeon_encoder *enc,
347 uint32_t temporal_id)
348 {
349 /* when only ltr frames in DPB, it needs to use the biggest ltr_seq
350 * one (latest) for reference, instead of the first one met. */
351 uint32_t i = 0;
352 uint32_t ret_idx = 0;
353 uint32_t max_seq = 0;
354 uint32_t max_seq_idx = 0;
355 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
356 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
357 if (frame->in_use && frame->is_ltr && (frame->ltr_seq >= max_seq)) {
358 max_seq = frame->ltr_seq;
359 max_seq_idx = i;
360 }
361 }
362 for (i = ARRAY_SIZE(enc->enc_pic.frames); i > 0; i--) {
363 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i - 1];
364 if (frame->in_use && frame->temporal_id <= temporal_id) {
365 if (frame->is_ltr)
366 ret_idx = max_seq_idx;
367 else
368 ret_idx = i - 1;
369
370 break;
371 }
372 }
373 return ret_idx;
374 }
375
radeon_enc_reset_av1_dpb_frames(struct radeon_encoder * enc)376 static void radeon_enc_reset_av1_dpb_frames(struct radeon_encoder *enc)
377 {
378 for (int i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++)
379 enc->enc_pic.frames[i] = (rvcn_enc_av1_ref_frame_t) {
380 .in_use = false,
381 .is_ltr = false,
382 .ltr_seq = 0,
383 .frame_id = 0,
384 .temporal_id = 0,
385 .slot_id = 0,
386 .frame_type = 0,
387 .frame_signature = NULL,
388 };
389
390 for (int i = 0; i < ARRAY_SIZE(enc->enc_pic.recon_slots); i++)
391 enc->enc_pic.recon_slots[i] = (rvcn_enc_av1_recon_slot_t) {
392 .in_use = false,
393 .is_orphaned = false,
394 };
395 }
396
radeon_enc_av1_dpb_management(struct radeon_encoder * enc)397 static void radeon_enc_av1_dpb_management(struct radeon_encoder *enc)
398 {
399 struct radeon_enc_pic *pic = &enc->enc_pic;
400 uint32_t current_slot;
401 uint32_t ref_slot;
402 uint32_t request_idx;
403 bool find = false;
404
405 if (pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY) {
406 pic->frame_id = 0;
407 pic->temporal_seq_num = 0;
408 pic->temporal_id = 0;
409 pic->reference_delta_frame_id = 0;
410 pic->reference_frame_index = 0;
411 pic->last_frame_type = PIPE_AV1_ENC_FRAME_TYPE_KEY;
412 pic->av1_ltr_seq = 0;
413 current_slot = 0;
414 ref_slot = 0;
415 request_idx = 0;
416 radeon_enc_reset_av1_dpb_frames(enc);
417 } else {
418 find = radeon_enc_av1_search_requested_reference(enc, &request_idx);
419 if (pic->av1_mark_long_term_reference || find)
420 pic->temporal_seq_num = 0; /*for ltr, always temporal_id = 0 */
421 else
422 pic->temporal_seq_num++;
423
424 pic->temporal_id = radeon_enc_av1_calculate_temporal_id(pic->temporal_seq_num,
425 pic->num_temporal_layers - 1);
426 if (find)
427 pic->reference_frame_index = request_idx;
428 else
429 pic->reference_frame_index =
430 radeon_enc_av1_obtain_ref0_frame(enc, pic->temporal_id);
431 ref_slot = pic->frames[pic->reference_frame_index].slot_id;
432 pic->last_frame_type = pic->frames[pic->reference_frame_index].frame_type;
433 radeon_enc_av1_pre_scan_frames(enc, pic->temporal_id);
434 }
435
436 if (pic->num_temporal_layers == 4)
437 radeon_enc_av1_temporal_4_extra_release(enc, pic->temporal_id);
438
439 pic->frame_to_show_map_index = pic->reference_frame_index;
440
441 for (int i = 0; i < ARRAY_SIZE(pic->frames); i++)
442 pic->reference_order_hint[i] = pic->frames[i].frame_id;
443
444 pic->reference_delta_frame_id = pic->frame_id -
445 pic->frames[pic->reference_frame_index].frame_id;
446 current_slot = radeon_enc_av1_alloc_curr_frame(enc, pic->frame_id,
447 pic->temporal_id,
448 pic->av1_mark_long_term_reference,
449 pic->av1_recon_frame,
450 pic->frame_type);
451 if (pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
452 pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH ||
453 ((pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING) &&
454 pic->last_frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY))
455 pic->refresh_frame_flags = 255;
456 else
457 pic->refresh_frame_flags = 1 << current_slot;
458
459 pic->enc_params.reference_picture_index = ref_slot;
460 pic->enc_params.reconstructed_picture_index = pic->frames[current_slot].slot_id;
461 pic->display_frame_id = pic->frame_id;
462 pic->order_hint = pic->frame_id;
463 }
464
radeon_enc_spec_misc_av1(struct radeon_encoder * enc)465 static void radeon_enc_spec_misc_av1(struct radeon_encoder *enc)
466 {
467 rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
468 struct tile_1d_layout tile_layout;
469 uint32_t num_of_tiles;
470 uint32_t frame_width_in_sb;
471 uint32_t frame_height_in_sb;
472 uint32_t num_tiles_cols;
473 uint32_t num_tiles_rows;
474 uint32_t max_tile_area_sb = RENCODE_AV1_MAX_TILE_AREA >> (2 * 6);
475 uint32_t max_tile_width_in_sb = RENCODE_AV1_MAX_TILE_WIDTH >> 6;
476 uint32_t max_tile_ares_in_sb = 0;
477 uint32_t max_tile_height_in_sb = 0;
478 uint32_t min_log2_tiles_width_in_sb;
479 uint32_t min_log2_tiles;
480
481 frame_width_in_sb = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_width,
482 PIPE_AV1_ENC_SB_SIZE);
483 frame_height_in_sb = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_height,
484 PIPE_AV1_ENC_SB_SIZE);
485 num_tiles_cols = (frame_width_in_sb > max_tile_width_in_sb) ? 2 : 1;
486 num_tiles_rows = CLAMP(p_config->num_tile_rows,
487 1, RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS);
488 min_log2_tiles_width_in_sb = radeon_enc_av1_tile_log2(max_tile_width_in_sb, frame_width_in_sb);
489 min_log2_tiles = MAX2(min_log2_tiles_width_in_sb, radeon_enc_av1_tile_log2(max_tile_area_sb,
490 frame_width_in_sb * frame_height_in_sb));
491
492 max_tile_width_in_sb = (num_tiles_cols == 1) ? frame_width_in_sb : max_tile_width_in_sb;
493
494 if (min_log2_tiles)
495 max_tile_ares_in_sb = (frame_width_in_sb * frame_height_in_sb)
496 >> (min_log2_tiles + 1);
497 else
498 max_tile_ares_in_sb = frame_width_in_sb * frame_height_in_sb;
499
500 max_tile_height_in_sb = DIV_ROUND_UP(max_tile_ares_in_sb, max_tile_width_in_sb);
501 num_tiles_rows = MAX2(num_tiles_rows,
502 DIV_ROUND_UP(frame_height_in_sb, max_tile_height_in_sb));
503
504 radeon_enc_av1_tile_layout(frame_height_in_sb, num_tiles_rows, 1, &tile_layout);
505 num_tiles_rows = tile_layout.nb_main_tile + tile_layout.nb_border_tile;
506
507 num_of_tiles = num_tiles_cols * num_tiles_rows;
508 /* in case of multiple tiles, it should be an obu frame */
509 if (num_of_tiles > 1)
510 enc->enc_pic.stream_obu_frame = 1;
511 else
512 enc->enc_pic.stream_obu_frame = enc->enc_pic.is_obu_frame;
513
514 RADEON_ENC_BEGIN(enc->cmd.spec_misc_av1);
515 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.palette_mode_enable);
516 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.mv_precision);
517 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_mode);
518 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_cdf_update);
519 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf);
520 RADEON_ENC_CS(num_of_tiles);
521 RADEON_ENC_CS(0);
522 RADEON_ENC_CS(0);
523 RADEON_ENC_CS(0xFFFFFFFF);
524 RADEON_ENC_CS(0xFFFFFFFF);
525 RADEON_ENC_END();
526 }
527
radeon_enc_cdf_default_table(struct radeon_encoder * enc)528 static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
529 {
530 bool use_cdf_default = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
531 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY ||
532 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH ||
533 (enc->enc_pic.enable_error_resilient_mode);
534
535 enc->enc_pic.av1_cdf_default_table.use_cdf_default = use_cdf_default ? 1 : 0;
536
537 RADEON_ENC_BEGIN(enc->cmd.cdf_default_table_av1);
538 RADEON_ENC_CS(enc->enc_pic.av1_cdf_default_table.use_cdf_default);
539 RADEON_ENC_READWRITE(enc->cdf->res->buf, enc->cdf->res->domains, 0);
540 RADEON_ENC_ADDR_SWAP();
541 RADEON_ENC_END();
542 }
543
radeon_enc_av1_header_size_offset(struct radeon_encoder * enc)544 uint8_t *radeon_enc_av1_header_size_offset(struct radeon_encoder *enc)
545 {
546 uint32_t *bits_start = enc->enc_pic.copy_start + 3;
547 assert(enc->bits_output % 8 == 0); /* should be always byte aligned */
548 return (uint8_t *)(bits_start) + (enc->bits_output >> 3);
549 }
550
radeon_enc_av1_obu_header(struct radeon_encoder * enc,uint32_t obu_type)551 void radeon_enc_av1_obu_header(struct radeon_encoder *enc, uint32_t obu_type)
552 {
553 bool use_extension_flag = (enc->enc_pic.num_temporal_layers) > 1 &&
554 (enc->enc_pic.temporal_id) > 0 ? 1 : 0;
555 /* obu header () */
556 /* obu_forbidden_bit */
557 radeon_enc_code_fixed_bits(enc, 0, 1);
558 /* obu_type */
559 radeon_enc_code_fixed_bits(enc, obu_type, 4);
560 /* obu_extension_flag */
561 radeon_enc_code_fixed_bits(enc, use_extension_flag ? 1 : 0, 1);
562 /* obu_has_size_field */
563 radeon_enc_code_fixed_bits(enc, 1, 1);
564 /* obu_reserved_1bit */
565 radeon_enc_code_fixed_bits(enc, 0, 1);
566
567 if (use_extension_flag) {
568 radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id, 3);
569 radeon_enc_code_fixed_bits(enc, 0, 2); /* spatial_id should always be zero */
570 radeon_enc_code_fixed_bits(enc, 0, 3); /* reserved 3 bits */
571 }
572 }
573
radeon_enc_av1_temporal_delimiter(struct radeon_encoder * enc)574 void radeon_enc_av1_temporal_delimiter(struct radeon_encoder *enc)
575 {
576 radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_TEMPORAL_DELIMITER);
577 radeon_enc_code_fixed_bits(enc, 0, 8); /* obu has size */
578 }
579
radeon_enc_av1_sequence_header(struct radeon_encoder * enc,bool separate_delta_q)580 void radeon_enc_av1_sequence_header(struct radeon_encoder *enc, bool separate_delta_q)
581 {
582 uint8_t *size_offset;
583 uint8_t obu_size_bin[2];
584 uint32_t obu_size;
585 uint32_t width_bits;
586 uint32_t height_bits;
587 uint32_t max_temporal_layers = enc->enc_pic.num_temporal_layers;
588
589 radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_SEQUENCE_HEADER);
590
591 /* obu_size, use two bytes for header, the size will be written in afterwards */
592 size_offset = radeon_enc_av1_header_size_offset(enc);
593 radeon_enc_code_fixed_bits(enc, 0, 2 * 8);
594
595 /* sequence_header_obu() */
596 /* seq_profile, only seq_profile = 0 is supported */
597 radeon_enc_code_fixed_bits(enc, 0, 3);
598 /* still_picture */
599 radeon_enc_code_fixed_bits(enc, 0, 1);
600 /* reduced_still_picture_header */
601 radeon_enc_code_fixed_bits(enc, 0, 1);
602 /* timing_info_present_flag */
603 radeon_enc_code_fixed_bits(enc, enc->enc_pic.timing_info_present ? 1 : 0, 1);
604
605 if (enc->enc_pic.timing_info_present) {
606 /* num_units_in_display_tick */
607 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_timing_info.num_units_in_display_tick, 32);
608 /* time_scale */
609 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_timing_info.time_scale, 32);
610 /* equal_picture_interval */
611 radeon_enc_code_fixed_bits(enc, enc->enc_pic.timing_info_equal_picture_interval, 1);
612 /* num_ticks_per_picture_minus_1 */
613 if (enc->enc_pic.timing_info_equal_picture_interval)
614 radeon_enc_code_uvlc(enc, enc->enc_pic.av1_timing_info.num_tick_per_picture_minus1);
615 /* decoder_model_info_present_flag */
616 radeon_enc_code_fixed_bits(enc, 0, 1);
617 }
618
619 /* initial_display_delay_present_flag */
620 radeon_enc_code_fixed_bits(enc, 0, 1);
621 /* operating_points_cnt_minus_1 */
622 radeon_enc_code_fixed_bits(enc, max_temporal_layers - 1, 5);
623
624 for (uint32_t i = 0; i < max_temporal_layers; i++) {
625 uint32_t operating_point_idc = 0;
626 if (max_temporal_layers > 1) {
627 operating_point_idc = (1 << (max_temporal_layers - i)) - 1;
628 operating_point_idc |= 0x100; /* spatial layer not supported */
629 }
630 radeon_enc_code_fixed_bits(enc, operating_point_idc, 12);
631 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 5);
632 if (enc->enc_pic.general_level_idc > 7)
633 radeon_enc_code_fixed_bits(enc, 0, 1); /* tier */
634 }
635
636 /* frame_width_bits_minus_1 */
637 width_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
638 radeon_enc_code_fixed_bits(enc, width_bits - 1, 4);
639 /* frame_height_bits_minus_1 */
640 height_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
641 radeon_enc_code_fixed_bits(enc, height_bits - 1, 4);
642 /* max_frame_width_minus_1 */
643 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
644 width_bits);
645 /* max_frame_height_minus_1 */
646 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
647 height_bits);
648
649 /* frame_id_numbers_present_flag */
650 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_id_numbers_present, 1);
651 if (enc->enc_pic.frame_id_numbers_present) {
652 /* delta_frame_id_length_minus_2 */
653 radeon_enc_code_fixed_bits(enc, RENCODE_AV1_DELTA_FRAME_ID_LENGTH - 2, 4);
654 /* additional_frame_id_length_minus_1 */
655 radeon_enc_code_fixed_bits(enc, RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH - 1, 3);
656 }
657
658 /* use_128x128_superblock */
659 radeon_enc_code_fixed_bits(enc, 0, 1);
660 /* enable_filter_intra */
661 radeon_enc_code_fixed_bits(enc, 0, 1);
662 /* enable_intra_edge_filter */
663 radeon_enc_code_fixed_bits(enc, 0, 1);
664 /* enable_interintra_compound */
665 radeon_enc_code_fixed_bits(enc, 0, 1);
666 /* enable_masked_compound */
667 radeon_enc_code_fixed_bits(enc, 0, 1);
668 /* enable_warped_motion */
669 radeon_enc_code_fixed_bits(enc, 0, 1);
670 /* enable_dual_filter */
671 radeon_enc_code_fixed_bits(enc, 0, 1);
672 /* enable_order_hint */
673 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_order_hint ? 1 : 0, 1);
674
675 if (enc->enc_pic.enable_order_hint) {
676 /* enable_jnt_comp */
677 radeon_enc_code_fixed_bits(enc, 0, 1);
678 /* enable_ref_frame_mvs */
679 radeon_enc_code_fixed_bits(enc, 0, 1);
680 }
681
682 /* seq_choose_screen_content_tools */
683 radeon_enc_code_fixed_bits(enc, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
684 if (enc->enc_pic.disable_screen_content_tools)
685 /* seq_force_screen_content_tools */
686 radeon_enc_code_fixed_bits(enc, 0, 1);
687 else
688 /* seq_choose_integer_mv */
689 radeon_enc_code_fixed_bits(enc, 1, 1);
690
691 if(enc->enc_pic.enable_order_hint)
692 /* order_hint_bits_minus_1 */
693 radeon_enc_code_fixed_bits(enc, enc->enc_pic.order_hint_bits - 1, 3);
694
695 /* enable_superres */
696 radeon_enc_code_fixed_bits(enc, 0, 1);
697 /* enable_cdef */
698 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
699 /* enable_restoration */
700 radeon_enc_code_fixed_bits(enc, 0, 1);
701 /* high_bitdepth */
702 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
703 /* mono_chrome */
704 radeon_enc_code_fixed_bits(enc, 0, 1);
705 /* color_description_present_flag */
706 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_color_description ? 1 : 0, 1);
707
708 if(enc->enc_pic.enable_color_description) {
709 /* color_primaries */
710 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.color_primaries, 8);
711 /* transfer_characteristics */
712 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.transfer_characteristics, 8);
713 /* matrix_coefficients */
714 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.maxtrix_coefficients, 8);
715 }
716 /* color_range */
717 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.color_range, 1);
718 /* chroma_sample_position */
719 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.chroma_sample_position, 2);
720 /* separate_uv_delta_q */
721 radeon_enc_code_fixed_bits(enc, !!(separate_delta_q), 1);
722 /* film_grain_params_present */
723 radeon_enc_code_fixed_bits(enc, 0, 1);
724
725 /* trailing_one_bit */
726 radeon_enc_code_fixed_bits(enc, 1, 1);
727 radeon_enc_byte_align(enc);
728
729 /* obu_size doesn't include the bytes within obu_header
730 * or obu_size syntax element (6.2.1), here we use 2 bytes for obu_size syntax
731 * which needs to be removed from the size.
732 */
733 obu_size = (uint32_t)(radeon_enc_av1_header_size_offset(enc) - size_offset - 2);
734 radeon_enc_code_leb128(obu_size_bin, obu_size, 2);
735
736 /* update obu_size */
737 for (int i = 0; i < sizeof(obu_size_bin); i++) {
738 uint8_t *p = (uint8_t *)((((uintptr_t)size_offset & 3) ^ 3) | ((uintptr_t)size_offset & ~3));
739 *p = obu_size_bin[i];
740 size_offset++;
741 }
742 }
743
radeon_enc_av1_frame_header(struct radeon_encoder * enc,bool frame_header)744 static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
745 {
746 uint32_t i;
747 bool show_existing = false;
748 bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
749 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
750 uint32_t obu_type = frame_header ? RENCODE_OBU_TYPE_FRAME_HEADER
751 : RENCODE_OBU_TYPE_FRAME;
752
753 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
754
755 radeon_enc_av1_obu_header(enc, obu_type);
756
757 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
758
759 /* uncompressed_header() */
760 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
761 /* show_existing_frame */
762 show_existing = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING;
763 radeon_enc_code_fixed_bits(enc, show_existing ? 1 : 0, 1);
764 /* if (show_existing_frame == 1) */
765 if(show_existing) {
766 /* frame_to_show_map_idx */
767 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_to_show_map_index, 3);
768 /* display_frame_id */
769 if (enc->enc_pic.frame_id_numbers_present)
770 radeon_enc_code_fixed_bits(enc, enc->enc_pic.display_frame_id,
771 RENCODE_AV1_DELTA_FRAME_ID_LENGTH +
772 RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH);
773 } else {
774 /* frame_type */
775 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_type, 2);
776 /* show_frame */
777 radeon_enc_code_fixed_bits(enc, 1, 1);
778 bool error_resilient_mode = false;
779 if ((enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH) ||
780 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY))
781 error_resilient_mode = true;
782 else {
783 /* error_resilient_mode */
784 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
785 error_resilient_mode = enc->enc_pic.enable_error_resilient_mode;
786 }
787 /* disable_cdf_update */
788 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
789
790 bool allow_screen_content_tools = false;
791 if (!enc->enc_pic.disable_screen_content_tools) {
792 /* allow_screen_content_tools */
793 allow_screen_content_tools = enc->enc_pic.av1_spec_misc.palette_mode_enable ||
794 enc->enc_pic.force_integer_mv;
795 radeon_enc_code_fixed_bits(enc, allow_screen_content_tools ? 1 : 0, 1);
796 }
797
798 if (allow_screen_content_tools)
799 /* force_integer_mv */
800 radeon_enc_code_fixed_bits(enc, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
801
802 if (enc->enc_pic.frame_id_numbers_present)
803 /* current_frame_id */
804 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_id,
805 RENCODE_AV1_DELTA_FRAME_ID_LENGTH +
806 RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH);
807
808 bool frame_size_override = false;
809 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH)
810 frame_size_override = true;
811 else {
812 /* frame_size_override_flag */
813 frame_size_override = false;
814 radeon_enc_code_fixed_bits(enc, 0, 1);
815 }
816
817 if (enc->enc_pic.enable_order_hint)
818 radeon_enc_code_fixed_bits(enc, enc->enc_pic.order_hint, enc->enc_pic.order_hint_bits);
819
820 if (!frame_is_intra && !error_resilient_mode)
821 /* primary_ref_frame */
822 radeon_enc_code_fixed_bits(enc, 0, 3); /* always LAST_FRAME(1) */
823
824 if ((enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SWITCH) &&
825 (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_KEY))
826 /* refresh_frame_flags */
827 radeon_enc_code_fixed_bits(enc, enc->enc_pic.refresh_frame_flags, 8);
828
829 if ((!frame_is_intra || enc->enc_pic.refresh_frame_flags != 0xff) &&
830 error_resilient_mode && enc->enc_pic.enable_order_hint)
831 for (i = 0; i < RENCDOE_AV1_NUM_REF_FRAMES; i++)
832 /* ref_order_hint */
833 radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_order_hint[i], enc->enc_pic.order_hint_bits);
834
835 if (frame_is_intra) {
836 /* render_and_frame_size_different */
837 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_render_size ? 1 : 0, 1);
838 if (enc->enc_pic.enable_render_size) {
839 /* render_width_minus_1 */
840 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_width - 1, 16);
841 /* render_height_minus_1 */
842 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_height - 1, 16);
843 }
844 if (!enc->enc_pic.disable_screen_content_tools &&
845 (enc->enc_pic.av1_spec_misc.palette_mode_enable || enc->enc_pic.force_integer_mv))
846 /* allow_intrabc */
847 radeon_enc_code_fixed_bits(enc, 0, 1);
848 } else {
849 if (enc->enc_pic.enable_order_hint)
850 /* frame_refs_short_signaling */
851 radeon_enc_code_fixed_bits(enc, 0, 1);
852 for (i = 0; i < RENCDOE_AV1_REFS_PER_FRAME; i++) {
853 /* ref_frame_idx */
854 radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_frame_index, 3);
855 if (enc->enc_pic.frame_id_numbers_present)
856 radeon_enc_code_fixed_bits(enc,
857 enc->enc_pic.reference_delta_frame_id - 1,
858 RENCODE_AV1_DELTA_FRAME_ID_LENGTH);
859 }
860
861 if (frame_size_override && !error_resilient_mode)
862 /* found_ref */
863 radeon_enc_code_fixed_bits(enc, 1, 1);
864 else {
865 if(frame_size_override) {
866 /* frame_width_minus_1 */
867 uint32_t used_bits =
868 radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
869 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
870 used_bits);
871 /* frame_height_minus_1 */
872 used_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
873 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
874 used_bits);
875 }
876 /* render_and_frame_size_different */
877 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_render_size ? 1 : 0, 1);
878 if (enc->enc_pic.enable_render_size) {
879 /* render_width_minus_1 */
880 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_width - 1, 16);
881 /* render_height_minus_1 */
882 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_height - 1, 16);
883 }
884 }
885
886 if (enc->enc_pic.disable_screen_content_tools || !enc->enc_pic.force_integer_mv)
887 /* allow_high_precision_mv */
888 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
889
890 /* read_interpolation_filter */
891 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
892
893 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
894 /* is_motion_mode_switchable */
895 radeon_enc_code_fixed_bits(enc, 0, 1);
896 }
897
898 if (!enc->enc_pic.av1_spec_misc.disable_cdf_update)
899 /* disable_frame_end_update_cdf */
900 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
901
902 /* tile_info */
903 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
904 /* quantization_params */
905 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
906 /* segmentation_enable */
907 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
908 radeon_enc_code_fixed_bits(enc, 0, 1);
909 /* delta_q_params */
910 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
911 /* delta_lf_params */
912 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
913 /* loop_filter_params */
914 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
915 /* cdef_params */
916 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
917 /* lr_params */
918 /* read_tx_mode */
919 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
920
921 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
922 if (!frame_is_intra)
923 /* reference_select */
924 radeon_enc_code_fixed_bits(enc, 0, 1);
925
926 radeon_enc_code_fixed_bits(enc, 0, 1);
927 if (!frame_is_intra)
928 for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
929 /* is_global */
930 radeon_enc_code_fixed_bits(enc, 0, 1);
931 /* film_grain_params() */
932 }
933 }
934
radeon_enc_av1_tile_group(struct radeon_encoder * enc)935 void radeon_enc_av1_tile_group(struct radeon_encoder *enc)
936 {
937 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
938 RENCODE_OBU_START_TYPE_TILE_GROUP);
939 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
940
941 radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_TILE_GROUP);
942
943 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
944 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
945 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
946 }
947
radeon_enc_av1_metadata_obu_hdr_cll(struct radeon_encoder * enc)948 static void radeon_enc_av1_metadata_obu_hdr_cll(struct radeon_encoder *enc)
949 {
950 uint8_t *size_offset;
951 uint8_t obu_size_bin;
952 uint8_t metadata_type;
953 uint8_t *p;
954 uint32_t obu_size;
955 uint32_t nb_obu_size_byte = sizeof(obu_size_bin);
956 rvcn_enc_sei_hdr_cll_t *p_cll = &enc->enc_pic.enc_sei.hdr_cll;
957
958 radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_METADATA);
959 /* obu_size, use nb_obu_size_byte bytes for header,
960 * the size will be written in afterwards */
961 size_offset = radeon_enc_av1_header_size_offset(enc);
962 radeon_enc_code_fixed_bits(enc, 0, nb_obu_size_byte * 8);
963 radeon_enc_code_leb128(&metadata_type, RENCODE_METADATA_TYPE_HDR_CLL, 1);
964 radeon_enc_code_fixed_bits(enc, metadata_type, 8);
965
966 radeon_enc_code_fixed_bits(enc, p_cll->max_cll, 16);
967 radeon_enc_code_fixed_bits(enc, p_cll->max_fall, 16);
968
969 /* trailing_one_bit */
970 radeon_enc_code_fixed_bits(enc, 1, 1);
971 radeon_enc_byte_align(enc);
972
973 /* obu_size doesn't include the bytes within obu_header
974 * or obu_size syntax element (6.2.1), here we use
975 * nb_obu_size_byte bytes for obu_size syntax
976 * which needs to be removed from the size.
977 */
978 obu_size = (uint32_t)(radeon_enc_av1_header_size_offset(enc)
979 - size_offset - nb_obu_size_byte);
980
981 radeon_enc_code_leb128(&obu_size_bin, obu_size, nb_obu_size_byte);
982
983 p = (uint8_t *)((((uintptr_t)size_offset & 3) ^ 3) | ((uintptr_t)size_offset & ~3));
984 *p = obu_size_bin;
985 }
986
radeon_enc_av1_metadata_obu_hdr_mdcv(struct radeon_encoder * enc)987 static void radeon_enc_av1_metadata_obu_hdr_mdcv(struct radeon_encoder *enc)
988 {
989 uint8_t *size_offset;
990 uint8_t obu_size_bin;
991 uint8_t metadata_type;
992 uint8_t *p;
993 uint32_t obu_size;
994 uint32_t nb_obu_size_byte = sizeof(obu_size_bin);
995 rvcn_enc_sei_hdr_mdcv_t *p_mdcv = &enc->enc_pic.enc_sei.hdr_mdcv;
996
997 radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_METADATA);
998 /* obu_size, use nb_obu_size_byte bytes for header,
999 * the size will be written in afterwards */
1000 size_offset = radeon_enc_av1_header_size_offset(enc);
1001 radeon_enc_code_fixed_bits(enc, 0, nb_obu_size_byte * 8);
1002 radeon_enc_code_leb128(&metadata_type, RENCODE_METADATA_TYPE_HDR_MDCV, 1);
1003 radeon_enc_code_fixed_bits(enc, metadata_type, 8);
1004
1005 for (int32_t i = 0; i < 3; i++) {
1006 radeon_enc_code_fixed_bits(enc, p_mdcv->primary_chromaticity_x[i], 16);
1007 radeon_enc_code_fixed_bits(enc, p_mdcv->primary_chromaticity_y[i], 16);
1008 }
1009
1010 radeon_enc_code_fixed_bits(enc, p_mdcv->white_point_chromaticity_x, 16);
1011 radeon_enc_code_fixed_bits(enc, p_mdcv->white_point_chromaticity_y, 16);
1012
1013 radeon_enc_code_fixed_bits(enc, p_mdcv->luminance_max, 32);
1014 radeon_enc_code_fixed_bits(enc, p_mdcv->luminance_min, 32);
1015
1016 /* trailing_one_bit */
1017 radeon_enc_code_fixed_bits(enc, 1, 1);
1018 radeon_enc_byte_align(enc);
1019
1020 /* obu_size doesn't include the bytes within obu_header
1021 * or obu_size syntax element (6.2.1), here we use
1022 * nb_obu_size_byte bytes for obu_size syntax
1023 * which needs to be removed from the size.
1024 */
1025 obu_size = (uint32_t)(radeon_enc_av1_header_size_offset(enc)
1026 - size_offset - nb_obu_size_byte);
1027
1028 radeon_enc_code_leb128(&obu_size_bin, obu_size, nb_obu_size_byte);
1029
1030 p = (uint8_t *)((((uintptr_t)size_offset & 3) ^ 3) | ((uintptr_t)size_offset & ~3));
1031 *p = obu_size_bin;
1032 }
1033
radeon_enc_av1_metadata_obu(struct radeon_encoder * enc)1034 void radeon_enc_av1_metadata_obu(struct radeon_encoder *enc)
1035 {
1036 if (!enc->enc_pic.enc_sei.flags.value)
1037 return;
1038
1039 if (enc->enc_pic.enc_sei.flags.hdr_mdcv)
1040 radeon_enc_av1_metadata_obu_hdr_mdcv(enc);
1041
1042 if (enc->enc_pic.enc_sei.flags.hdr_cll)
1043 radeon_enc_av1_metadata_obu_hdr_cll(enc);
1044
1045 }
1046
radeon_enc_obu_instruction(struct radeon_encoder * enc)1047 static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
1048 {
1049 bool frame_header = !enc->enc_pic.stream_obu_frame ||
1050 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING);
1051 radeon_enc_reset(enc);
1052 RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
1053 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
1054
1055 radeon_enc_av1_temporal_delimiter(enc);
1056 if (enc->enc_pic.need_av1_seq || enc->enc_pic.need_sequence_header)
1057 radeon_enc_av1_sequence_header(enc, false);
1058
1059 /* if others OBU types are needed such as meta data, then they need to be byte aligned and added here
1060 *
1061 * if (others)
1062 * radeon_enc_av1_others(enc); */
1063 radeon_enc_av1_metadata_obu(enc);
1064
1065 radeon_enc_av1_bs_instruction_type(enc,
1066 RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
1067 frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
1068 : RENCODE_OBU_START_TYPE_FRAME);
1069
1070 radeon_enc_av1_frame_header(enc, frame_header);
1071
1072 if (!frame_header && (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING))
1073 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
1074
1075 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
1076
1077 if (frame_header && (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING))
1078 radeon_enc_av1_tile_group(enc);
1079
1080 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
1081 RADEON_ENC_END();
1082 }
1083
1084 /* av1 encode params */
radeon_enc_av1_encode_params(struct radeon_encoder * enc)1085 static void radeon_enc_av1_encode_params(struct radeon_encoder *enc)
1086 {
1087 switch (enc->enc_pic.frame_type) {
1088 case PIPE_AV1_ENC_FRAME_TYPE_KEY:
1089 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1090 break;
1091 case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
1092 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1093 break;
1094 case PIPE_AV1_ENC_FRAME_TYPE_INTER:
1095 case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
1096 case PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING:
1097 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1098 break;
1099 default:
1100 assert(0); /* never come to this condition */
1101 }
1102
1103 if (enc->luma->meta_offset) {
1104 RVID_ERR("DCC surfaces not supported.\n");
1105 assert(false);
1106 }
1107
1108 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1109 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
1110 enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;
1111 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1112
1113 RADEON_ENC_BEGIN(enc->cmd.enc_params);
1114 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1115 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1116
1117 /* show existing type doesn't need input picture */
1118 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING) {
1119 RADEON_ENC_CS(0);
1120 RADEON_ENC_CS(0);
1121 RADEON_ENC_CS(0);
1122 RADEON_ENC_CS(0);
1123 } else {
1124 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1125 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma ?
1126 enc->chroma->u.gfx9.surf_offset : enc->luma->u.gfx9.surf_pitch);
1127 }
1128
1129 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1130 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1131 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1132 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1133 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1134 RADEON_ENC_END();
1135 }
1136
radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)1137 static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
1138 {
1139 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
1140 if (enc->enc_pic.bit_depth_luma_minus8 != 0)
1141 return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP;
1142 else
1143 return RENCODE_REC_SWIZZLE_MODE_256B_D;
1144 }
1145
radeon_enc_ctx(struct radeon_encoder * enc)1146 static void radeon_enc_ctx(struct radeon_encoder *enc)
1147 {
1148
1149 bool is_av1 = u_reduce_video_profile(enc->base.profile)
1150 == PIPE_VIDEO_FORMAT_AV1;
1151 enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc);
1152 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
1153
1154 RADEON_ENC_BEGIN(enc->cmd.ctx);
1155 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
1156 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1157 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1158 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1159 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1160
1161 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1162 rvcn_enc_reconstructed_picture_t *pic =
1163 &enc->enc_pic.ctx_buf.reconstructed_pictures[i];
1164 RADEON_ENC_CS(pic->luma_offset);
1165 RADEON_ENC_CS(pic->chroma_offset);
1166 if (is_av1) {
1167 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
1168 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
1169 } else {
1170 RADEON_ENC_CS(0x00000000); /* unused offset 1 */
1171 RADEON_ENC_CS(0x00000000); /* unused offset 2 */
1172 }
1173 }
1174
1175 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
1176 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
1177
1178 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1179 rvcn_enc_reconstructed_picture_t *pic =
1180 &enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i];
1181 RADEON_ENC_CS(pic->luma_offset);
1182 RADEON_ENC_CS(pic->chroma_offset);
1183 if (is_av1) {
1184 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
1185 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
1186 } else {
1187 RADEON_ENC_CS(0x00000000); /* unused offset 1 */
1188 RADEON_ENC_CS(0x00000000); /* unused offset 2 */
1189 }
1190 }
1191
1192 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset);
1193 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset);
1194 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset);
1195
1196 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
1197 if (is_av1)
1198 RADEON_ENC_CS(enc->enc_pic.ctx_buf.av1.av1_sdb_intermediate_context_offset);
1199 else
1200 RADEON_ENC_CS(enc->enc_pic.ctx_buf.colloc_buffer_offset);
1201 RADEON_ENC_END();
1202 }
1203
radeon_enc_header_av1(struct radeon_encoder * enc)1204 static void radeon_enc_header_av1(struct radeon_encoder *enc)
1205 {
1206 enc->tile_config(enc);
1207 enc->obu_instructions(enc);
1208 enc->encode_params(enc);
1209 enc->encode_params_codec_spec(enc);
1210 enc->cdf_default_table(enc);
1211
1212 enc->enc_pic.frame_id++;
1213 if (enc->enc_pic.frame_id > (1 << (RENCODE_AV1_DELTA_FRAME_ID_LENGTH - 2)))
1214 enc->enc_pic.frame_id = 0;
1215 }
1216
radeon_enc_4_0_init(struct radeon_encoder * enc)1217 void radeon_enc_4_0_init(struct radeon_encoder *enc)
1218 {
1219 radeon_enc_3_0_init(enc);
1220
1221 enc->session_init = radeon_enc_session_init;
1222 enc->ctx = radeon_enc_ctx;
1223 enc->mq_begin = enc->begin;
1224 enc->mq_encode = enc->encode;
1225 enc->mq_destroy = enc->destroy;
1226 enc->begin = radeon_enc_sq_begin;
1227 enc->encode = radeon_enc_sq_encode;
1228 enc->destroy = radeon_enc_sq_destroy;
1229 enc->op_preset = radeon_enc_op_preset;
1230
1231 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1) {
1232 enc->before_encode = radeon_enc_av1_dpb_management;
1233 /* begin function need to set these functions to dummy */
1234 enc->slice_control = radeon_enc_dummy;
1235 enc->deblocking_filter = radeon_enc_dummy;
1236 enc->tile_config = radeon_enc_dummy;
1237 enc->encode_params_codec_spec = radeon_enc_dummy;
1238 enc->cmd.cdf_default_table_av1 = RENCODE_IB_PARAM_CDF_DEFAULT_TABLE_BUFFER;
1239 enc->cmd.bitstream_instruction_av1 = RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
1240 enc->cmd.spec_misc_av1 = RENCODE_AV1_IB_PARAM_SPEC_MISC;
1241 enc->spec_misc = radeon_enc_spec_misc_av1;
1242 enc->encode_headers = radeon_enc_header_av1;
1243 enc->obu_instructions = radeon_enc_obu_instruction;
1244 enc->cdf_default_table = radeon_enc_cdf_default_table;
1245 enc->encode_params = radeon_enc_av1_encode_params;
1246 }
1247
1248 enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
1249
1250 enc->enc_pic.session_info.interface_version =
1251 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1252 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1253 }
1254