1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <libfdt.h>
11
12 #include <platform_def.h>
13
14 #include <arch_features.h>
15 #include <arch_helpers.h>
16 #include <common/bl_common.h>
17 #include <common/debug.h>
18 #include <common/desc_image_load.h>
19 #include <common/fdt_fixup.h>
20 #include <common/fdt_wrappers.h>
21 #include <lib/optee_utils.h>
22 #include <lib/transfer_list.h>
23 #include <lib/utils.h>
24 #include <plat/common/platform.h>
25 #if ENABLE_RME
26 #include <qemu_pas_def.h>
27 #endif
28
29 #include "qemu_private.h"
30
31 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \
32 bl2_tzram_layout.total_base, \
33 bl2_tzram_layout.total_size, \
34 MT_MEMORY | MT_RW | EL3_PAS)
35
36 #define MAP_BL2_RO MAP_REGION_FLAT( \
37 BL_CODE_BASE, \
38 BL_CODE_END - BL_CODE_BASE, \
39 MT_CODE | EL3_PAS), \
40 MAP_REGION_FLAT( \
41 BL_RO_DATA_BASE, \
42 BL_RO_DATA_END \
43 - BL_RO_DATA_BASE, \
44 MT_RO_DATA | EL3_PAS)
45
46 #if USE_COHERENT_MEM
47 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
48 BL_COHERENT_RAM_BASE, \
49 BL_COHERENT_RAM_END \
50 - BL_COHERENT_RAM_BASE, \
51 MT_DEVICE | MT_RW | EL3_PAS)
52 #endif
53
54 /* Data structure which holds the extents of the trusted SRAM for BL2 */
55 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
56 static struct transfer_list_header *bl2_tl;
57
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)58 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
59 u_register_t arg2, u_register_t arg3)
60 {
61 meminfo_t *mem_layout = (void *)arg1;
62
63 /* Initialize the console to provide early debug support */
64 qemu_console_init();
65
66 /* Setup the BL2 memory layout */
67 bl2_tzram_layout = *mem_layout;
68
69 plat_qemu_io_setup();
70 }
71
security_setup(void)72 static void security_setup(void)
73 {
74 /*
75 * This is where a TrustZone address space controller and other
76 * security related peripherals, would be configured.
77 */
78 }
79
80 #if defined (SPD_trusty) || defined(SPD_spmd)
81
82 #define GIC_SPI 0
83 #define GIC_PPI 1
84
spd_add_dt_node(void * fdt)85 static int spd_add_dt_node(void *fdt)
86 {
87 int offs, trusty_offs, root_offs;
88 int gic, ipi;
89 int len;
90 const uint32_t *prop;
91
92 if (fdt_path_offset(fdt, "/trusty") >= 0) {
93 WARN("Trusty Device Tree node already exists!\n");
94 return 0;
95 }
96
97 offs = fdt_node_offset_by_compatible(fdt, -1, "arm,cortex-a15-gic");
98 if (offs < 0)
99 offs = fdt_node_offset_by_compatible(fdt, -1, "arm,gic-v3");
100
101 if (offs < 0)
102 return -1;
103 gic = fdt_get_phandle(fdt, offs);
104 if (!gic) {
105 WARN("Failed to get gic phandle\n");
106 return -1;
107 }
108 INFO("Found gic phandle 0x%x\n", gic);
109
110 offs = fdt_path_offset(fdt, "/");
111 if (offs < 0)
112 return -1;
113 root_offs = offs;
114
115 /* CustomIPI node for pre 5.10 linux driver */
116 offs = fdt_add_subnode(fdt, offs, "interrupt-controller");
117 if (offs < 0)
118 return -1;
119 ipi = fdt_get_max_phandle(fdt) + 1;
120 if (fdt_setprop_u32(fdt, offs, "phandle", 1))
121 return -1;
122 INFO("Found ipi phandle 0x%x\n", ipi);
123
124 ipi = fdt_get_phandle(fdt, offs);
125 if (!ipi) {
126 WARN("Failed to get ipi phandle\n");
127 return -1;
128 }
129
130 if (fdt_appendprop_string(fdt, offs, "compatible", "android,CustomIPI"))
131 return -1;
132 if (fdt_setprop_u32(fdt, offs, "#interrupt-cells", 1))
133 return -1;
134 if (fdt_setprop_u32(fdt, offs, "interrupt-controller", 0))
135 return -1;
136
137 offs = fdt_add_subnode(fdt, root_offs, "trusty");
138 if (offs < 0)
139 return -1;
140 trusty_offs = offs;
141
142 if (fdt_appendprop_string(fdt, offs, "compatible", "android,trusty-smc-v1"))
143 return -1;
144 if (fdt_setprop_u32(fdt, offs, "ranges", 0))
145 return -1;
146 if (fdt_setprop_u32(fdt, offs, "#address-cells", 2))
147 return -1;
148 if (fdt_setprop_u32(fdt, offs, "#size-cells", 2))
149 return -1;
150
151 offs = fdt_add_subnode(fdt, trusty_offs, "irq");
152 if (offs < 0)
153 return -1;
154 if (fdt_appendprop_string(fdt, offs, "compatible", "android,trusty-irq-v1"))
155 return -1;
156 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", ipi))
157 return -1;
158 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", 0))
159 return -1;
160 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", gic))
161 return -1;
162 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", 1))
163 return -1;
164 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", GIC_PPI))
165 return -1;
166 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", 4))
167 return -1;
168 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", gic))
169 return -1;
170 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", 1))
171 return -1;
172 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", GIC_SPI))
173 return -1;
174 if (fdt_appendprop_u32(fdt, offs, "interrupt-templates", 4))
175 return -1;
176
177 /* CustomIPI range for pre 5.10 linux driver */
178 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 0))
179 return -1;
180 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 15))
181 return -1;
182 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 0))
183 return -1;
184
185 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 16))
186 return -1;
187 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 31))
188 return -1;
189 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 1))
190 return -1;
191 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 32))
192 return -1;
193 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 63))
194 return -1;
195 if (fdt_appendprop_u32(fdt, offs, "interrupt-ranges", 2))
196 return -1;
197
198 if (fdt_appendprop_u32(fdt, offs, "ipi-range", 8)) /* beg */
199 return -1;
200 if (fdt_appendprop_u32(fdt, offs, "ipi-range", 15)) /* end */
201 return -1;
202 if (fdt_appendprop_u32(fdt, offs, "ipi-range", 8)) /* ipi_base */
203 return -1;
204
205 offs = fdt_add_subnode(fdt, trusty_offs, "log");
206 if (offs < 0)
207 return -1;
208 if (fdt_appendprop_string(fdt, offs, "compatible", "android,trusty-log-v1"))
209 return -1;
210
211 offs = fdt_add_subnode(fdt, trusty_offs, "test");
212 if (offs < 0)
213 return -1;
214 if (fdt_appendprop_string(fdt, offs, "compatible", "android,trusty-test-v1"))
215 return -1;
216
217 offs = fdt_add_subnode(fdt, trusty_offs, "virtio");
218 if (offs < 0)
219 return -1;
220 if (fdt_appendprop_string(fdt, offs, "compatible", "android,trusty-virtio-v1"))
221 return -1;
222
223 offs = fdt_node_offset_by_compatible(fdt, -1, "arm,armv8-timer");
224 if (offs < 0)
225 offs = fdt_node_offset_by_compatible(fdt, -1, "arm,armv7-timer");
226 if (offs < 0)
227 return -1;
228
229 prop = fdt_getprop(fdt, offs, "interrupts", &len);
230 if (fdt_setprop_inplace_namelen_partial(fdt, offs, "interrupts",
231 strlen("interrupts"), 0,
232 prop + len / 4 / 2, len / 4))
233 return -1;
234
235 return 0;
236 }
237
238 #else
239
spd_add_dt_node(void * fdt)240 static int spd_add_dt_node(void *fdt)
241 {
242 return 0;
243 }
244
245 #endif
246
qemu_dt_fixup_securemem(void * fdt)247 static int qemu_dt_fixup_securemem(void *fdt)
248 {
249 /*
250 * QEMU adds a device tree node for secure memory. Linux fails to ignore
251 * it and will crash when it allocates memory out of this secure memory
252 * region. We currently don't use this node for anything, remove it.
253 */
254
255 int offs;
256 const char *prop;
257 const char memory_device_type[] = "memory";
258
259 offs = -1;
260 while (true) {
261 offs = fdt_node_offset_by_prop_value(fdt, offs, "device_type",
262 memory_device_type,
263 sizeof(memory_device_type)
264 );
265 if (offs < 0)
266 break;
267
268 prop = fdt_getprop(fdt, offs, "status", NULL);
269 if (prop == NULL)
270 continue;
271 if ((strcmp(prop, "disabled") != 0))
272 continue;
273 prop = fdt_getprop(fdt, offs, "secure-status", NULL);
274 if (prop == NULL)
275 continue;
276 if ((strcmp(prop, "okay") != 0))
277 continue;
278
279 if (fdt_del_node(fdt, offs)) {
280 return -1;
281 }
282 INFO("Removed secure memory node\n");
283 }
284
285 return 0;
286 }
287
update_dt(void)288 static void update_dt(void)
289 {
290 #if TRANSFER_LIST
291 struct transfer_list_entry *te;
292 #endif
293 int ret;
294 void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
295
296 ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
297 if (ret < 0) {
298 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
299 return;
300 }
301
302 if (qemu_dt_fixup_securemem(fdt)) {
303 ERROR("Failed to fixup secure-mem Device Tree node\n");
304 return;
305 }
306
307 if (dt_add_psci_node(fdt)) {
308 ERROR("Failed to add PSCI Device Tree node\n");
309 return;
310 }
311
312 if (dt_add_psci_cpu_enable_methods(fdt)) {
313 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
314 return;
315 }
316
317 if (spd_add_dt_node(fdt)) {
318 ERROR("Failed to add SPD Device Tree node\n");
319 return;
320 }
321
322 #if ENABLE_RME
323 if (fdt_add_reserved_memory(fdt, "rmm", REALM_DRAM_BASE,
324 REALM_DRAM_SIZE)) {
325 ERROR("Failed to reserve RMM memory in Device Tree\n");
326 return;
327 }
328
329 INFO("Reserved RMM memory [0x%lx, 0x%lx] in Device tree\n",
330 (uintptr_t)REALM_DRAM_BASE,
331 (uintptr_t)REALM_DRAM_BASE + REALM_DRAM_SIZE - 1);
332 #endif
333
334 ret = fdt_pack(fdt);
335 if (ret < 0)
336 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
337
338 #if TRANSFER_LIST
339 /* create a TE */
340 te = transfer_list_add(bl2_tl, TL_TAG_FDT, fdt_totalsize(fdt), fdt);
341 if (!te) {
342 ERROR("Failed to add FDT entry to Transfer List\n");
343 return;
344 }
345 #endif
346 }
347
bl2_platform_setup(void)348 void bl2_platform_setup(void)
349 {
350 #if TRANSFER_LIST
351 bl2_tl = transfer_list_init((void *)(uintptr_t)FW_HANDOFF_BASE,
352 FW_HANDOFF_SIZE);
353 if (!bl2_tl) {
354 ERROR("Failed to initialize Transfer List at 0x%lx\n",
355 (unsigned long)FW_HANDOFF_BASE);
356 }
357 #endif
358 security_setup();
359 update_dt();
360
361 /* TODO Initialize timer */
362 }
363
qemu_bl2_sync_transfer_list(void)364 void qemu_bl2_sync_transfer_list(void)
365 {
366 #if TRANSFER_LIST
367 transfer_list_update_checksum(bl2_tl);
368 #endif
369 }
370
371 #if ENABLE_RME
bl2_plat_gpt_setup(void)372 static void bl2_plat_gpt_setup(void)
373 {
374 /*
375 * The GPT library might modify the gpt regions structure to optimize
376 * the layout, so the array cannot be constant.
377 */
378 pas_region_t pas_regions[] = {
379 QEMU_PAS_ROOT,
380 QEMU_PAS_SECURE,
381 QEMU_PAS_GPTS,
382 QEMU_PAS_NS0,
383 QEMU_PAS_REALM,
384 QEMU_PAS_NS1,
385 };
386
387 /*
388 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry
389 * covering 1GB (currently the only supported option), then covering
390 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the
391 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA).
392 */
393 if (gpt_init_l0_tables(GPCCR_PPS_1TB, PLAT_QEMU_L0_GPT_BASE,
394 PLAT_QEMU_L0_GPT_SIZE) < 0) {
395 ERROR("gpt_init_l0_tables() failed!\n");
396 panic();
397 }
398
399 /* Carve out defined PAS ranges. */
400 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
401 PLAT_QEMU_L1_GPT_BASE,
402 PLAT_QEMU_L1_GPT_SIZE,
403 pas_regions,
404 (unsigned int)(sizeof(pas_regions) /
405 sizeof(pas_region_t))) < 0) {
406 ERROR("gpt_init_pas_l1_tables() failed!\n");
407 panic();
408 }
409
410 INFO("Enabling Granule Protection Checks\n");
411 if (gpt_enable() < 0) {
412 ERROR("gpt_enable() failed!\n");
413 panic();
414 }
415 }
416 #endif
417
bl2_plat_arch_setup(void)418 void bl2_plat_arch_setup(void)
419 {
420 const mmap_region_t bl_regions[] = {
421 MAP_BL2_TOTAL,
422 MAP_BL2_RO,
423 #if USE_COHERENT_MEM
424 MAP_BL_COHERENT_RAM,
425 #endif
426 #if ENABLE_RME
427 MAP_RMM_DRAM,
428 MAP_GPT_L0_REGION,
429 MAP_GPT_L1_REGION,
430 #endif
431 {0}
432 };
433
434 setup_page_tables(bl_regions, plat_qemu_get_mmap());
435
436 #if ENABLE_RME
437 /* BL2 runs in EL3 when RME enabled. */
438 assert(is_feat_rme_present());
439 enable_mmu_el3(0);
440
441 /* Initialise and enable granule protection after MMU. */
442 bl2_plat_gpt_setup();
443 #else /* ENABLE_RME */
444
445 #ifdef __aarch64__
446 enable_mmu_el1(0);
447 #else
448 enable_mmu_svc_mon(0);
449 #endif
450 #endif /* ENABLE_RME */
451 }
452
453 /*******************************************************************************
454 * Gets SPSR for BL32 entry
455 ******************************************************************************/
qemu_get_spsr_for_bl32_entry(void)456 static uint32_t qemu_get_spsr_for_bl32_entry(void)
457 {
458 #ifdef __aarch64__
459 /*
460 * The Secure Payload Dispatcher service is responsible for
461 * setting the SPSR prior to entry into the BL3-2 image.
462 */
463 return 0;
464 #else
465 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
466 DISABLE_ALL_EXCEPTIONS);
467 #endif
468 }
469
470 /*******************************************************************************
471 * Gets SPSR for BL33 entry
472 ******************************************************************************/
qemu_get_spsr_for_bl33_entry(void)473 static uint32_t qemu_get_spsr_for_bl33_entry(void)
474 {
475 uint32_t spsr;
476 #ifdef __aarch64__
477 unsigned int mode;
478
479 /* Figure out what mode we enter the non-secure world in */
480 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
481
482 /*
483 * TODO: Consider the possibility of specifying the SPSR in
484 * the FIP ToC and allowing the platform to have a say as
485 * well.
486 */
487 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
488 #else
489 spsr = SPSR_MODE32(MODE32_svc,
490 plat_get_ns_image_entrypoint() & 0x1,
491 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
492 #endif
493 return spsr;
494 }
495
496 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
load_sps_from_tb_fw_config(struct image_info * image_info)497 static int load_sps_from_tb_fw_config(struct image_info *image_info)
498 {
499 void *dtb = (void *)image_info->image_base;
500 const char *compat_str = "arm,sp";
501 const struct fdt_property *uuid;
502 uint32_t load_addr;
503 const char *name;
504 int sp_node;
505 int node;
506
507 node = fdt_node_offset_by_compatible(dtb, -1, compat_str);
508 if (node < 0) {
509 ERROR("Can't find %s in TB_FW_CONFIG", compat_str);
510 return -1;
511 }
512
513 fdt_for_each_subnode(sp_node, dtb, node) {
514 name = fdt_get_name(dtb, sp_node, NULL);
515 if (name == NULL) {
516 ERROR("Can't get name of node in dtb\n");
517 return -1;
518 }
519 uuid = fdt_get_property(dtb, sp_node, "uuid", NULL);
520 if (uuid == NULL) {
521 ERROR("Can't find property uuid in node %s", name);
522 return -1;
523 }
524 if (fdt_read_uint32(dtb, sp_node, "load-address",
525 &load_addr) < 0) {
526 ERROR("Can't read load-address in node %s", name);
527 return -1;
528 }
529 if (qemu_io_register_sp_pkg(name, uuid->data, load_addr) < 0) {
530 return -1;
531 }
532 }
533
534 return 0;
535 }
536 #endif /*defined(SPD_spmd) && SPMD_SPM_AT_SEL2*/
537
538 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) || defined(SPMC_OPTEE)
handoff_pageable_part(uint64_t pagable_part)539 static int handoff_pageable_part(uint64_t pagable_part)
540 {
541 #if TRANSFER_LIST
542 struct transfer_list_entry *te;
543
544 te = transfer_list_add(bl2_tl, TL_TAG_OPTEE_PAGABLE_PART,
545 sizeof(pagable_part), &pagable_part);
546 if (!te) {
547 INFO("Cannot add TE for pageable part\n");
548 return -1;
549 }
550 #endif
551 return 0;
552 }
553 #endif
554
qemu_bl2_handle_post_image_load(unsigned int image_id)555 static int qemu_bl2_handle_post_image_load(unsigned int image_id)
556 {
557 int err = 0;
558 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
559 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) || defined(SPMC_OPTEE)
560 bl_mem_params_node_t *pager_mem_params = NULL;
561 bl_mem_params_node_t *paged_mem_params = NULL;
562 #endif
563 #if defined(SPD_spmd)
564 bl_mem_params_node_t *bl32_mem_params = NULL;
565 #endif
566 #if TRANSFER_LIST
567 struct transfer_list_header *ns_tl = NULL;
568 #endif
569
570 assert(bl_mem_params);
571
572 switch (image_id) {
573 #if TRANSFER_LIST
574 case BL31_IMAGE_ID:
575 /*
576 * arg0 is a bl_params_t reserved for bl31_early_platform_setup2
577 * we just need arg1 and arg3 for BL31 to update th TL from S
578 * to NS memory before it exits
579 */
580 bl_mem_params->ep_info.args.arg1 =
581 TRANSFER_LIST_SIGNATURE |
582 REGISTER_CONVENTION_VERSION_MASK;
583 bl_mem_params->ep_info.args.arg3 = (uintptr_t)bl2_tl;
584 break;
585 #endif
586 case BL32_IMAGE_ID:
587 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) || defined(SPMC_OPTEE)
588 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
589 assert(pager_mem_params);
590
591 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
592 assert(paged_mem_params);
593
594 err = parse_optee_header(&bl_mem_params->ep_info,
595 &pager_mem_params->image_info,
596 &paged_mem_params->image_info);
597 if (err != 0) {
598 WARN("OPTEE header parse error.\n");
599 }
600
601 /* add TL_TAG_OPTEE_PAGABLE_PART entry to the TL */
602 if (handoff_pageable_part(bl_mem_params->ep_info.args.arg1)) {
603 return -1;
604 }
605 #endif
606
607 INFO("Handoff to BL32\n");
608 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
609 if (TRANSFER_LIST &&
610 transfer_list_set_handoff_args(bl2_tl,
611 &bl_mem_params->ep_info))
612 break;
613
614 INFO("Using default arguments\n");
615 #if defined(SPMC_OPTEE)
616 /*
617 * Explicit zeroes to unused registers since they may have
618 * been populated by parse_optee_header() above.
619 *
620 * OP-TEE expects system DTB in x2 and TOS_FW_CONFIG in x0,
621 * the latter is filled in below for TOS_FW_CONFIG_ID and
622 * applies to any other SPMC too.
623 */
624 bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
625 #elif defined(SPD_opteed)
626 /*
627 * OP-TEE expect to receive DTB address in x2.
628 * This will be copied into x2 by dispatcher.
629 */
630 bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
631 #elif defined(AARCH32_SP_OPTEE)
632 bl_mem_params->ep_info.args.arg0 =
633 bl_mem_params->ep_info.args.arg1;
634 bl_mem_params->ep_info.args.arg1 = 0;
635 bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
636 bl_mem_params->ep_info.args.arg3 = 0;
637 #endif
638 break;
639
640 case BL33_IMAGE_ID:
641 #ifdef AARCH32_SP_OPTEE
642 /* AArch32 only core: OP-TEE expects NSec EP in register LR */
643 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
644 assert(pager_mem_params);
645 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
646 #endif
647
648 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
649
650 #if ARM_LINUX_KERNEL_AS_BL33
651 /*
652 * According to the file ``Documentation/arm64/booting.txt`` of
653 * the Linux kernel tree, Linux expects the physical address of
654 * the device tree blob (DTB) in x0, while x1-x3 are reserved
655 * for future use and must be 0.
656 */
657 bl_mem_params->ep_info.args.arg0 =
658 (u_register_t)ARM_PRELOADED_DTB_BASE;
659 bl_mem_params->ep_info.args.arg1 = 0U;
660 bl_mem_params->ep_info.args.arg2 = 0U;
661 bl_mem_params->ep_info.args.arg3 = 0U;
662 #elif TRANSFER_LIST
663 if (bl2_tl) {
664 /* relocate the tl to pre-allocate NS memory */
665 ns_tl = transfer_list_relocate(bl2_tl,
666 (void *)(uintptr_t)FW_NS_HANDOFF_BASE,
667 bl2_tl->max_size);
668 if (!ns_tl) {
669 ERROR("Relocate TL to 0x%lx failed\n",
670 (unsigned long)FW_NS_HANDOFF_BASE);
671 return -1;
672 }
673 }
674
675 INFO("Handoff to BL33\n");
676 if (!transfer_list_set_handoff_args(ns_tl,
677 &bl_mem_params->ep_info)) {
678 INFO("Invalid TL, fallback to default arguments\n");
679 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
680 }
681 #else
682 /* BL33 expects to receive the primary CPU MPID (through r0) */
683 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
684 #endif /* ARM_LINUX_KERNEL_AS_BL33 */
685
686 break;
687 #ifdef SPD_spmd
688 #if SPMD_SPM_AT_SEL2
689 case TB_FW_CONFIG_ID:
690 err = load_sps_from_tb_fw_config(&bl_mem_params->image_info);
691 break;
692 #endif
693 case TOS_FW_CONFIG_ID:
694 /* An SPMC expects TOS_FW_CONFIG in x0/r0 */
695 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
696 bl32_mem_params->ep_info.args.arg0 =
697 bl_mem_params->image_info.image_base;
698 break;
699 #endif
700 default:
701 /* Do nothing in default case */
702 break;
703 }
704
705 return err;
706 }
707
708 /*******************************************************************************
709 * This function can be used by the platforms to update/use image
710 * information for given `image_id`.
711 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)712 int bl2_plat_handle_post_image_load(unsigned int image_id)
713 {
714 return qemu_bl2_handle_post_image_load(image_id);
715 }
716
plat_get_ns_image_entrypoint(void)717 uintptr_t plat_get_ns_image_entrypoint(void)
718 {
719 return NS_IMAGE_OFFSET;
720 }
721