1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Rudolf Marek <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 /* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
18
19 #include <stdlib.h>
20 #include "programmer.h"
21 #include "hwaccess_physmap.h"
22 #include "platform/pci.h"
23
24 #define PCI_VENDOR_ID_SII 0x1095
25
26 #define SATASII_MEMMAP_SIZE 0x100
27
28 struct satasii_data {
29 uint8_t *bar;
30 };
31
32 static const struct dev_entry satas_sii[] = {
33 {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},
34 {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},
35 {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},
36 {0x1095, 0x3124, OK, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},
37 {0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},
38 {0x1095, 0x3512, OK, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"},
39
40 {0},
41 };
42
satasii_wait_done(const uint8_t * bar)43 static uint32_t satasii_wait_done(const uint8_t *bar)
44 {
45 uint32_t ctrl_reg;
46 int i = 0;
47 while ((ctrl_reg = pci_mmio_readl(bar)) & (1 << 25)) {
48 if (++i > 10000) {
49 msg_perr("%s: control register stuck at %08"PRIx32", ignoring.\n",
50 __func__, pci_mmio_readl(bar));
51 break;
52 }
53 }
54 return ctrl_reg;
55 }
56
satasii_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)57 static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
58 {
59 const struct satasii_data *data = flash->mst->par.data;
60 uint32_t data_reg;
61 uint32_t ctrl_reg = satasii_wait_done(data->bar);
62
63 /* Mask out unused/reserved bits, set writes and start transaction. */
64 ctrl_reg &= 0xfcf80000;
65 ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
66
67 data_reg = (pci_mmio_readl((data->bar + 4)) & ~0xff) | val;
68 pci_mmio_writel(data_reg, (data->bar + 4));
69 pci_mmio_writel(ctrl_reg, data->bar);
70
71 satasii_wait_done(data->bar);
72 }
73
satasii_chip_readb(const struct flashctx * flash,const chipaddr addr)74 static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr)
75 {
76 const struct satasii_data *data = flash->mst->par.data;
77 uint32_t ctrl_reg = satasii_wait_done(data->bar);
78
79 /* Mask out unused/reserved bits, set reads and start transaction. */
80 ctrl_reg &= 0xfcf80000;
81 ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
82
83 pci_mmio_writel(ctrl_reg, data->bar);
84
85 satasii_wait_done(data->bar);
86
87 return (pci_mmio_readl(data->bar + 4)) & 0xff;
88 }
89
satasii_shutdown(void * par_data)90 static int satasii_shutdown(void *par_data)
91 {
92 free(par_data);
93 return 0;
94 }
95
96 static const struct par_master par_master_satasii = {
97 .chip_readb = satasii_chip_readb,
98 .chip_writeb = satasii_chip_writeb,
99 .shutdown = satasii_shutdown,
100 };
101
satasii_init(const struct programmer_cfg * cfg)102 static int satasii_init(const struct programmer_cfg *cfg)
103 {
104 struct pci_dev *dev = NULL;
105 uint32_t addr;
106 uint16_t reg_offset, id;
107 uint8_t *bar;
108
109 dev = pcidev_init(cfg, satas_sii, PCI_BASE_ADDRESS_0);
110 if (!dev)
111 return 1;
112
113 id = dev->device_id;
114
115 if ((id == 0x3132) || (id == 0x3124)) {
116 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
117 if (!addr)
118 return 1;
119 reg_offset = 0x70;
120 } else {
121 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
122 if (!addr)
123 return 1;
124 reg_offset = 0x50;
125 }
126
127 bar = rphysmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE);
128 if (bar == ERROR_PTR)
129 return 1;
130 bar += reg_offset;
131
132 /* Check if ROM cycle are OK. */
133 if ((id != 0x0680) && (!(pci_mmio_readl(bar) & (1 << 26))))
134 msg_pwarn("Warning: Flash seems unconnected.\n");
135
136 struct satasii_data *data = calloc(1, sizeof(*data));
137 if (!data) {
138 msg_perr("Unable to allocate space for PAR master data\n");
139 return 1;
140 }
141 data->bar = bar;
142
143 return register_par_master(&par_master_satasii, BUS_PARALLEL, data);
144 }
145 const struct programmer_entry programmer_satasii = {
146 .name = "satasii",
147 .type = PCI,
148 .devs.dev = satas_sii,
149 .init = satasii_init,
150 };
151