1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2011 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 /* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
17
18 #include <stdlib.h>
19 #include "flash.h"
20 #include "programmer.h"
21 #include "hwaccess_physmap.h"
22 #include "platform/pci.h"
23
24 struct nicintel_data {
25 uint8_t *nicintel_bar;
26 uint8_t *nicintel_control_bar;
27 };
28
29 static const struct dev_entry nics_intel[] = {
30 {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
31 {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
32
33 {0},
34 };
35
36 /* Arbitrary limit, taken from the datasheet I just had lying around.
37 * 128 kByte on the 82559 device. Or not. Depends on whom you ask.
38 */
39 #define NICINTEL_MEMMAP_SIZE (128 * 1024)
40 #define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
41
42 #define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
43
44 #define CSR_FCR 0x0c
45
nicintel_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)46 static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
47 chipaddr addr)
48 {
49 const struct nicintel_data *data = flash->mst->par.data;
50
51 pci_mmio_writeb(val, data->nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
52 }
53
nicintel_chip_readb(const struct flashctx * flash,const chipaddr addr)54 static uint8_t nicintel_chip_readb(const struct flashctx *flash,
55 const chipaddr addr)
56 {
57 const struct nicintel_data *data = flash->mst->par.data;
58
59 return pci_mmio_readb(data->nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
60 }
61
nicintel_shutdown(void * par_data)62 static int nicintel_shutdown(void *par_data)
63 {
64 free(par_data);
65 return 0;
66 }
67
68 static const struct par_master par_master_nicintel = {
69 .chip_readb = nicintel_chip_readb,
70 .chip_writeb = nicintel_chip_writeb,
71 .shutdown = nicintel_shutdown,
72 };
73
nicintel_init(const struct programmer_cfg * cfg)74 static int nicintel_init(const struct programmer_cfg *cfg)
75 {
76 struct pci_dev *dev = NULL;
77 uintptr_t addr;
78 uint8_t *bar;
79 uint8_t *control_bar;
80
81 /* FIXME: BAR2 is not available if the device uses the CardBus function. */
82 dev = pcidev_init(cfg, nics_intel, PCI_BASE_ADDRESS_2);
83 if (!dev)
84 return 1;
85
86 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
87 if (!addr)
88 return 1;
89
90 bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
91 if (bar == ERROR_PTR)
92 return 1;
93
94 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
95 if (!addr)
96 return 1;
97
98 control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE);
99 if (control_bar == ERROR_PTR)
100 return 1;
101
102 /* FIXME: This register is pretty undocumented in all publicly available
103 * documentation from Intel. Let me quote the complete info we have:
104 * "Flash Control Register: The Flash Control register allows the CPU to
105 * enable writes to an external Flash. The Flash Control Register is a
106 * 32-bit field that allows access to an external Flash device."
107 * Ah yes, we also know where it is, but we have absolutely _no_ idea
108 * what we should do with it. Write 0x0001 because we have nothing
109 * better to do with our time.
110 */
111 pci_rmmio_writew(0x0001, control_bar + CSR_FCR);
112
113 struct nicintel_data *data = calloc(1, sizeof(*data));
114 if (!data) {
115 msg_perr("Unable to allocate space for PAR master data\n");
116 return 1;
117 }
118 data->nicintel_bar = bar;
119 data->nicintel_control_bar = control_bar;
120
121 max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
122 return register_par_master(&par_master_nicintel, BUS_PARALLEL, data);
123 }
124
125 const struct programmer_entry programmer_nicintel = {
126 .name = "nicintel",
127 .type = PCI,
128 .devs.dev = nics_intel,
129 .init = nicintel_init,
130 };
131