1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <stdbool.h>
18 #include <stdlib.h>
19 #include <string.h>
20 #include "flash.h"
21 #include "programmer.h"
22 #include "hwaccess_physmap.h"
23 #include "platform/pci.h"
24
25 #define PCI_VENDOR_ID_NVIDIA 0x10de
26
27 /* Mask to restrict flash accesses to a 128kB memory window.
28 * FIXME: Is this size a one-fits-all or card dependent?
29 */
30 #define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
31 #define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
32
33 #define REG_FLASH_ACCESS 0x50
34 #define BIT_FLASH_ACCESS BIT(0)
35
36 struct gfxnvidia_data {
37 struct pci_dev *dev;
38 uint8_t *bar;
39 uint32_t flash_access;
40 };
41
42 static const struct dev_entry gfx_nvidia[] = {
43 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
44 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
45 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
46 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
47 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
48 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
49 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
50 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
51 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
52 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
53 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
54 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
55 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
56 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
57 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
58 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
59 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
60 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
61 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
62 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
63 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
64 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
65 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
66
67 {0},
68 };
69
gfxnvidia_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)70 static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
71 chipaddr addr)
72 {
73 const struct gfxnvidia_data *data = flash->mst->par.data;
74
75 pci_mmio_writeb(val, data->bar + (addr & GFXNVIDIA_MEMMAP_MASK));
76 }
77
gfxnvidia_chip_readb(const struct flashctx * flash,const chipaddr addr)78 static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
79 const chipaddr addr)
80 {
81 const struct gfxnvidia_data *data = flash->mst->par.data;
82
83 return pci_mmio_readb(data->bar + (addr & GFXNVIDIA_MEMMAP_MASK));
84 }
85
gfxnvidia_shutdown(void * par_data)86 static int gfxnvidia_shutdown(void *par_data)
87 {
88 struct gfxnvidia_data *data = par_data;
89
90 /* Restore original flash interface access state. */
91 pci_write_long(data->dev, REG_FLASH_ACCESS, data->flash_access);
92
93 free(par_data);
94 return 0;
95 }
96
97 static const struct par_master par_master_gfxnvidia = {
98 .chip_readb = gfxnvidia_chip_readb,
99 .chip_writeb = gfxnvidia_chip_writeb,
100 .shutdown = gfxnvidia_shutdown,
101 };
102
gfxnvidia_init(const struct programmer_cfg * cfg)103 static int gfxnvidia_init(const struct programmer_cfg *cfg)
104 {
105 struct pci_dev *dev = NULL;
106 uint32_t reg32;
107 uint8_t *bar;
108
109 dev = pcidev_init(cfg, gfx_nvidia, PCI_BASE_ADDRESS_0);
110 if (!dev)
111 return 1;
112
113 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
114 if (!io_base_addr)
115 return 1;
116
117 io_base_addr += 0x300000;
118 msg_pinfo("Detected NVIDIA I/O base address: 0x%"PRIx32".\n", io_base_addr);
119
120 bar = rphysmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
121 if (bar == ERROR_PTR)
122 return 1;
123
124 struct gfxnvidia_data *data = calloc(1, sizeof(*data));
125 if (!data) {
126 msg_perr("Unable to allocate space for PAR master data\n");
127 return 1;
128 }
129 data->dev = dev;
130 data->bar = bar;
131
132 /* Allow access to flash interface (will disable screen). */
133 data->flash_access = pci_read_long(dev, REG_FLASH_ACCESS);
134 reg32 = data->flash_access & ~BIT_FLASH_ACCESS;
135 pci_write_long(dev, REG_FLASH_ACCESS, reg32);
136
137 /* Write/erase doesn't work. */
138 programmer_may_write = false;
139 return register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, data);
140 }
141
142 const struct programmer_entry programmer_gfxnvidia = {
143 .name = "gfxnvidia",
144 .type = PCI,
145 .devs.dev = gfx_nvidia,
146 .init = gfxnvidia_init,
147 };
148