1 /*
2 * Copyright 2003 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * \file intel_debug.c
27 *
28 * Support for the INTEL_DEBUG environment variable, along with other
29 * miscellaneous debugging code.
30 */
31
32 #include <stdio.h>
33 #include <stdlib.h>
34 #include <string.h>
35
36 #include "dev/intel_debug.h"
37 #include "util/macros.h"
38 #include "util/u_debug.h"
39 #include "util/u_math.h"
40 #include "c11/threads.h"
41
42 uint64_t intel_debug = 0;
43
44 #define DEBUG_NO16 (1ull << 16)
45 #define DEBUG_NO8 (1ull << 20)
46 #define DEBUG_NO32 (1ull << 39)
47
48 static const struct debug_control debug_control[] = {
49 { "tex", DEBUG_TEXTURE},
50 { "blit", DEBUG_BLIT},
51 { "fall", DEBUG_PERF},
52 { "perf", DEBUG_PERF},
53 { "perfmon", DEBUG_PERFMON},
54 { "bat", DEBUG_BATCH},
55 { "buf", DEBUG_BUFMGR},
56 { "fs", DEBUG_WM },
57 { "gs", DEBUG_GS},
58 { "sync", DEBUG_SYNC},
59 { "sf", DEBUG_SF },
60 { "submit", DEBUG_SUBMIT },
61 { "wm", DEBUG_WM },
62 { "urb", DEBUG_URB },
63 { "vs", DEBUG_VS },
64 { "clip", DEBUG_CLIP },
65 { "no16", DEBUG_NO16 },
66 { "blorp", DEBUG_BLORP },
67 { "nodualobj", DEBUG_NO_DUAL_OBJECT_GS },
68 { "optimizer", DEBUG_OPTIMIZER },
69 { "ann", DEBUG_ANNOTATION },
70 { "no8", DEBUG_NO8 },
71 { "no-oaconfig", DEBUG_NO_OACONFIG },
72 { "spill_fs", DEBUG_SPILL_FS },
73 { "spill_vec4", DEBUG_SPILL_VEC4 },
74 { "cs", DEBUG_CS },
75 { "hex", DEBUG_HEX },
76 { "nocompact", DEBUG_NO_COMPACTION },
77 { "hs", DEBUG_TCS },
78 { "tcs", DEBUG_TCS },
79 { "ds", DEBUG_TES },
80 { "tes", DEBUG_TES },
81 { "l3", DEBUG_L3 },
82 { "do32", DEBUG_DO32 },
83 { "norbc", DEBUG_NO_CCS },
84 { "noccs", DEBUG_NO_CCS },
85 { "nohiz", DEBUG_NO_HIZ },
86 { "color", DEBUG_COLOR },
87 { "reemit", DEBUG_REEMIT },
88 { "soft64", DEBUG_SOFT64 },
89 { "bt", DEBUG_BT },
90 { "pc", DEBUG_PIPE_CONTROL },
91 { "nofc", DEBUG_NO_FAST_CLEAR },
92 { "no32", DEBUG_NO32 },
93 { "shaders", DEBUG_WM | DEBUG_VS | DEBUG_TCS |
94 DEBUG_TES | DEBUG_GS | DEBUG_CS |
95 DEBUG_RT | DEBUG_TASK | DEBUG_MESH },
96 { "rt", DEBUG_RT },
97 { "task", DEBUG_TASK },
98 { "mesh", DEBUG_MESH },
99 { "stall", DEBUG_STALL },
100 { "capture-all", DEBUG_CAPTURE_ALL },
101 { "perf-symbol-names", DEBUG_PERF_SYMBOL_NAMES },
102 { "swsb-stall", DEBUG_SWSB_STALL },
103 { "heaps", DEBUG_HEAPS },
104 { "isl", DEBUG_ISL },
105 { "sparse", DEBUG_SPARSE },
106 { "draw_bkp", DEBUG_DRAW_BKP },
107 { "bat-stats", DEBUG_BATCH_STATS },
108 { "reg-pressure", DEBUG_REG_PRESSURE },
109 { "shader-print", DEBUG_SHADER_PRINT },
110 { "cl-quiet", DEBUG_CL_QUIET },
111 { NULL, 0 }
112 };
113
114 uint64_t intel_simd = 0;
115
116 static const struct debug_control simd_control[] = {
117 { "fs8", DEBUG_FS_SIMD8 },
118 { "fs16", DEBUG_FS_SIMD16 },
119 { "fs32", DEBUG_FS_SIMD32 },
120 { "fs2x8", DEBUG_FS_SIMD2X8 },
121 { "fs4x8", DEBUG_FS_SIMD4X8 },
122 { "fs2x16", DEBUG_FS_SIMD2X16 },
123 { "cs8", DEBUG_CS_SIMD8 },
124 { "cs16", DEBUG_CS_SIMD16 },
125 { "cs32", DEBUG_CS_SIMD32 },
126 { "ts8", DEBUG_TS_SIMD8 },
127 { "ts16", DEBUG_TS_SIMD16 },
128 { "ts32", DEBUG_TS_SIMD32 },
129 { "ms8", DEBUG_MS_SIMD8 },
130 { "ms16", DEBUG_MS_SIMD16 },
131 { "ms32", DEBUG_MS_SIMD32 },
132 { "rt8", DEBUG_RT_SIMD8 },
133 { "rt16", DEBUG_RT_SIMD16 },
134 { "rt32", DEBUG_RT_SIMD32 },
135 { NULL, 0 }
136 };
137
138 uint64_t
intel_debug_flag_for_shader_stage(gl_shader_stage stage)139 intel_debug_flag_for_shader_stage(gl_shader_stage stage)
140 {
141 uint64_t flags[] = {
142 [MESA_SHADER_VERTEX] = DEBUG_VS,
143 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
144 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
145 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
146 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
147 [MESA_SHADER_COMPUTE] = DEBUG_CS,
148 [MESA_SHADER_KERNEL] = DEBUG_CS,
149
150 [MESA_SHADER_TASK] = DEBUG_TASK,
151 [MESA_SHADER_MESH] = DEBUG_MESH,
152
153 [MESA_SHADER_RAYGEN] = DEBUG_RT,
154 [MESA_SHADER_ANY_HIT] = DEBUG_RT,
155 [MESA_SHADER_CLOSEST_HIT] = DEBUG_RT,
156 [MESA_SHADER_MISS] = DEBUG_RT,
157 [MESA_SHADER_INTERSECTION] = DEBUG_RT,
158 [MESA_SHADER_CALLABLE] = DEBUG_RT,
159 };
160 return flags[stage];
161 }
162
163 #define DEBUG_FS_SIMD (DEBUG_FS_SIMD8 | DEBUG_FS_SIMD16 | \
164 DEBUG_FS_SIMD32)
165 #define DEBUG_CS_SIMD (DEBUG_CS_SIMD8 | DEBUG_CS_SIMD16 | DEBUG_CS_SIMD32)
166 #define DEBUG_TS_SIMD (DEBUG_TS_SIMD8 | DEBUG_TS_SIMD16 | DEBUG_TS_SIMD32)
167 #define DEBUG_MS_SIMD (DEBUG_MS_SIMD8 | DEBUG_MS_SIMD16 | DEBUG_MS_SIMD32)
168 #define DEBUG_RT_SIMD (DEBUG_RT_SIMD8 | DEBUG_RT_SIMD16 | DEBUG_RT_SIMD32)
169
170 #define DEBUG_SIMD8_ALL \
171 (DEBUG_FS_SIMD8 | \
172 DEBUG_CS_SIMD8 | \
173 DEBUG_TS_SIMD8 | \
174 DEBUG_MS_SIMD8 | \
175 DEBUG_RT_SIMD8)
176
177 #define DEBUG_SIMD16_ALL \
178 (DEBUG_FS_SIMD16 | \
179 DEBUG_CS_SIMD16 | \
180 DEBUG_TS_SIMD16 | \
181 DEBUG_MS_SIMD16 | \
182 DEBUG_RT_SIMD16)
183
184 #define DEBUG_SIMD32_ALL \
185 (DEBUG_FS_SIMD32 | \
186 DEBUG_CS_SIMD32 | \
187 DEBUG_TS_SIMD32 | \
188 DEBUG_MS_SIMD32 | \
189 DEBUG_RT_SIMD32)
190
191 uint64_t intel_debug_batch_frame_start = 0;
192 uint64_t intel_debug_batch_frame_stop = -1;
193
194 uint32_t intel_debug_bkp_before_draw_count = 0;
195 uint32_t intel_debug_bkp_after_draw_count = 0;
196
197 static void
process_intel_debug_variable_once(void)198 process_intel_debug_variable_once(void)
199 {
200 intel_debug = parse_debug_string(getenv("INTEL_DEBUG"), debug_control);
201 intel_simd = parse_debug_string(getenv("INTEL_SIMD_DEBUG"), simd_control);
202 intel_debug_batch_frame_start =
203 debug_get_num_option("INTEL_DEBUG_BATCH_FRAME_START", 0);
204 intel_debug_batch_frame_stop =
205 debug_get_num_option("INTEL_DEBUG_BATCH_FRAME_STOP", -1);
206
207 intel_debug_bkp_before_draw_count =
208 debug_get_num_option("INTEL_DEBUG_BKP_BEFORE_DRAW_COUNT", 0);
209 intel_debug_bkp_after_draw_count =
210 debug_get_num_option("INTEL_DEBUG_BKP_AFTER_DRAW_COUNT", 0);
211
212 if (!(intel_simd & DEBUG_FS_SIMD))
213 intel_simd |= DEBUG_FS_SIMD;
214 if (!(intel_simd & DEBUG_CS_SIMD))
215 intel_simd |= DEBUG_CS_SIMD;
216 if (!(intel_simd & DEBUG_TS_SIMD))
217 intel_simd |= DEBUG_TS_SIMD;
218 if (!(intel_simd & DEBUG_MS_SIMD))
219 intel_simd |= DEBUG_MS_SIMD;
220 if (!(intel_simd & DEBUG_RT_SIMD))
221 intel_simd |= DEBUG_RT_SIMD;
222
223 if (intel_debug & DEBUG_NO8)
224 intel_simd &= ~DEBUG_SIMD8_ALL;
225 if (intel_debug & DEBUG_NO16)
226 intel_simd &= ~DEBUG_SIMD16_ALL;
227 if (intel_debug & DEBUG_NO32)
228 intel_simd &= ~DEBUG_SIMD32_ALL;
229 intel_debug &= ~(DEBUG_NO8 | DEBUG_NO16 | DEBUG_NO32);
230 }
231
232 void
process_intel_debug_variable(void)233 process_intel_debug_variable(void)
234 {
235 static once_flag process_intel_debug_variable_flag = ONCE_FLAG_INIT;
236
237 call_once(&process_intel_debug_variable_flag,
238 process_intel_debug_variable_once);
239 }
240