1 // Copyright 2016 The SwiftShader Authors. All Rights Reserved.
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "CPUID.hpp"
16
17 #if defined(_WIN32)
18 # ifndef WIN32_LEAN_AND_MEAN
19 # define WIN32_LEAN_AND_MEAN
20 # endif
21 # include <windows.h>
22 # include <intrin.h>
23 # include <float.h>
24 #else
25 # include <unistd.h>
26 # include <sched.h>
27 # include <sys/types.h>
28 #endif
29
30 #if defined(__i386__) || defined(__x86_64__)
31 # include <xmmintrin.h>
32 # include <pmmintrin.h>
33 #endif
34
35 namespace sw {
36
cpuid(int registers[4],int info)37 static void cpuid(int registers[4], int info)
38 {
39 #if defined(__i386__) || defined(__x86_64__)
40 # if defined(_WIN32)
41 __cpuid(registers, info);
42 # else
43 __asm volatile("cpuid"
44 : "=a"(registers[0]), "=b"(registers[1]), "=c"(registers[2]), "=d"(registers[3])
45 : "a"(info));
46 # endif
47 #else
48 registers[0] = 0;
49 registers[1] = 0;
50 registers[2] = 0;
51 registers[3] = 0;
52 #endif
53 }
54
supportsMMX()55 bool CPUID::supportsMMX()
56 {
57 int registers[4];
58 cpuid(registers, 1);
59 return (registers[3] & 0x00800000) != 0;
60 }
61
supportsCMOV()62 bool CPUID::supportsCMOV()
63 {
64 int registers[4];
65 cpuid(registers, 1);
66 return (registers[3] & 0x00008000) != 0;
67 }
68
supportsSSE()69 bool CPUID::supportsSSE()
70 {
71 int registers[4];
72 cpuid(registers, 1);
73 return (registers[3] & 0x02000000) != 0;
74 }
75
supportsSSE2()76 bool CPUID::supportsSSE2()
77 {
78 int registers[4];
79 cpuid(registers, 1);
80 return (registers[3] & 0x04000000) != 0;
81 }
82
supportsSSE3()83 bool CPUID::supportsSSE3()
84 {
85 int registers[4];
86 cpuid(registers, 1);
87 return (registers[2] & 0x00000001) != 0;
88 }
89
supportsSSSE3()90 bool CPUID::supportsSSSE3()
91 {
92 int registers[4];
93 cpuid(registers, 1);
94 return (registers[2] & 0x00000200) != 0;
95 }
96
supportsSSE4_1()97 bool CPUID::supportsSSE4_1()
98 {
99 int registers[4];
100 cpuid(registers, 1);
101 return (registers[2] & 0x00080000) != 0;
102 }
103
coreCount()104 int CPUID::coreCount()
105 {
106 int cores = 0;
107
108 #if defined(_WIN32)
109 DWORD_PTR processAffinityMask = 1;
110 DWORD_PTR systemAffinityMask = 1;
111
112 GetProcessAffinityMask(GetCurrentProcess(), &processAffinityMask, &systemAffinityMask);
113
114 while(systemAffinityMask)
115 {
116 if(systemAffinityMask & 1)
117 {
118 cores++;
119 }
120
121 systemAffinityMask >>= 1;
122 }
123 #else
124 cores = sysconf(_SC_NPROCESSORS_ONLN);
125 #endif
126
127 if(cores < 1) cores = 1;
128 if(cores > 16) cores = 16;
129
130 return cores; // FIXME: Number of physical cores
131 }
132
processAffinity()133 int CPUID::processAffinity()
134 {
135 int cores = 0;
136
137 #if defined(_WIN32)
138 DWORD_PTR processAffinityMask = 1;
139 DWORD_PTR systemAffinityMask = 1;
140
141 GetProcessAffinityMask(GetCurrentProcess(), &processAffinityMask, &systemAffinityMask);
142
143 while(processAffinityMask)
144 {
145 if(processAffinityMask & 1)
146 {
147 cores++;
148 }
149
150 processAffinityMask >>= 1;
151 }
152 #else
153 return coreCount(); // FIXME: Assumes no affinity limitation
154 #endif
155
156 if(cores < 1) cores = 1;
157 if(cores > 16) cores = 16;
158
159 return cores;
160 }
161
setFlushToZero(bool enableFTZ)162 void CPUID::setFlushToZero(bool enableFTZ)
163 {
164 #if defined(_MSC_VER)
165 unsigned int current = _controlfp(0, 0) & _MCW_DN;
166 if(current == _DN_SAVE || current == _DN_SAVE_OPERANDS_FLUSH_RESULTS) // DAZ off
167 {
168 _controlfp(enableFTZ ? _DN_SAVE_OPERANDS_FLUSH_RESULTS : _DN_SAVE, _MCW_DN);
169 }
170 else // DAZ on
171 {
172 _controlfp(enableFTZ ? _DN_FLUSH : _DN_FLUSH_OPERANDS_SAVE_RESULTS, _MCW_DN);
173 }
174 #elif defined(__i386__) || defined(__x86_64__)
175 _MM_SET_FLUSH_ZERO_MODE(enableFTZ ? _MM_FLUSH_ZERO_ON : _MM_FLUSH_ZERO_OFF);
176 #else
177 // Unimplemented
178 #endif
179 }
180
setDenormalsAreZero(bool enableDAZ)181 void CPUID::setDenormalsAreZero(bool enableDAZ)
182 {
183 #if defined(_MSC_VER)
184 unsigned int current = _controlfp(0, 0) & _MCW_DN;
185 if(current == _DN_SAVE || current == _DN_FLUSH_OPERANDS_SAVE_RESULTS) // FTZ off
186 {
187 _controlfp(enableDAZ ? _DN_FLUSH_OPERANDS_SAVE_RESULTS : _DN_SAVE, _MCW_DN);
188 }
189 else // FTZ on
190 {
191 _controlfp(enableDAZ ? _DN_FLUSH : _DN_SAVE_OPERANDS_FLUSH_RESULTS, _MCW_DN);
192 }
193 #elif defined(__i386__) || defined(__x86_64__)
194 _MM_SET_DENORMALS_ZERO_MODE(enableDAZ ? _MM_DENORMALS_ZERO_ON : _MM_DENORMALS_ZERO_OFF);
195 #else
196 // Unimplemented
197 #endif
198 }
199
200 } // namespace sw
201