1 /* inteltool - dump all registers on an Intel CPU + chipset based system. */
2 /* SPDX-License-Identifier: GPL-2.0-only */
3
4
5 #include <stdio.h>
6 #include <stdlib.h>
7 #include <inttypes.h>
8 #include "inteltool.h"
9
10 volatile uint8_t *mchbar;
11
write_mchbar32(uint32_t addr,uint32_t val)12 static void write_mchbar32 (uint32_t addr, uint32_t val)
13 {
14 * (volatile uint32_t *) (mchbar + addr) = val;
15 }
16
read_mchbar32(uint32_t addr)17 static uint32_t read_mchbar32 (uint32_t addr)
18 {
19 return * (volatile uint32_t *) (mchbar + addr);
20 }
21
read_mchbar8(uint32_t addr)22 static uint8_t read_mchbar8 (uint32_t addr)
23 {
24 return * (volatile uint8_t *) (mchbar + addr);
25 }
26
read_500(int channel,u16 addr,int split)27 static u16 read_500 (int channel, u16 addr, int split)
28 {
29 uint32_t val;
30 write_mchbar32 (0x500 + (channel << 10), 0);
31 while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
32 write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
33 while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
34 val = read_mchbar32 (0x508 + (channel << 10));
35
36 return val & ((1 << split) - 1);
37 }
38
get_lane_offset(int slot,int rank,int lane)39 static inline u16 get_lane_offset (int slot, int rank, int lane)
40 {
41 return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8);
42 }
43
get_timing_register_addr(int lane,int tm,int slot,int rank)44 static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank)
45 {
46 const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
47 return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4];
48 }
49
write_1d0(u32 val,u16 addr,int bits,int flag)50 static void write_1d0 (u32 val, u16 addr, int bits, int flag)
51 {
52 write_mchbar32 (0x1d0, 0);
53 while (read_mchbar32 (0x1d0) & 0x800000);
54 write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
55 write_mchbar32 (0x1d0, 0x40000000 | addr);
56 while (read_mchbar32 (0x1d0) & 0x800000);
57 }
58
read_1d0(u16 addr,int split)59 static u16 read_1d0 (u16 addr, int split)
60 {
61 u32 val;
62 write_mchbar32 (0x1d0, 0);
63 while (read_mchbar32 (0x1d0) & 0x800000);
64 write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr));
65 while (read_mchbar32 (0x1d0) & 0x800000);
66 val = read_mchbar32 (0x1d8);
67 write_1d0 (0, 0x33d, 0, 0);
68 write_1d0 (0, 0x33d, 0, 0);
69 return val & ((1 << split) - 1);
70 }
71
dump_timings(void)72 static void dump_timings (void)
73 {
74 int channel, slot, rank, lane, i;
75 printf ("Timings:\n");
76 for (channel = 0; channel < 2; channel++)
77 for (slot = 0; slot < 2; slot++)
78 for (rank = 0; rank < 2; rank++) {
79 printf ("channel %d, slot %d, rank %d\n", channel, slot, rank);
80 for (lane = 0; lane < 9; lane++) {
81 printf ("lane %d: ", lane);
82 for (i = 0; i < 4; i++) {
83 printf ("%x ", read_500 (channel,
84 get_timing_register_addr (lane, i, slot, rank), 9));
85 }
86 printf ("\n");
87 }
88 }
89
90 printf ("[178] = %x\n", read_1d0 (0x178, 7));
91 printf ("[10b] = %x\n", read_1d0 (0x10b, 6));
92 }
93
94
95 /*
96 * (G)MCH MMIO Config Space
97 */
print_mchbar(struct pci_dev * nb,struct pci_access * pacc,const char * dump_spd_file)98 int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file)
99 {
100 int i, size = (16 * 1024);
101 uint64_t mchbar_phys;
102 struct pci_dev *nb_device6; /* "overflow device" on i865 */
103 uint16_t pcicmd6;
104
105 printf("\n============= MCHBAR ============\n\n");
106
107 switch (nb->device_id) {
108 case PCI_DEVICE_ID_INTEL_82865:
109 /*
110 * On i865, the memory access enable/disable bit (MCHBAREN on
111 * i945/i965) is not in the MCHBAR (i945/i965) register but in
112 * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6.
113 *
114 * The actual base address is in BAR6 on i865 where on
115 * i945/i965 the base address is in MCHBAR.
116 */
117 nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */
118 mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */
119 pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */
120
121 /* Try to enable Memory Access Enable (MAE). */
122 if (!(pcicmd6 & (1 << 1))) {
123 printf("Access to BAR6 is currently disabled, "
124 "attempting to enable.\n");
125 pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1));
126 if (pci_read_long(nb_device6, 0x04) & (1 << 1))
127 printf("Enabled successfully.\n");
128 else
129 printf("Enable FAILED!\n");
130 }
131 mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */
132 break;
133 case PCI_DEVICE_ID_INTEL_82915:
134 case PCI_DEVICE_ID_INTEL_82945GM:
135 case PCI_DEVICE_ID_INTEL_82945GSE:
136 case PCI_DEVICE_ID_INTEL_82945P:
137 case PCI_DEVICE_ID_INTEL_82975X:
138 mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
139 break;
140 case PCI_DEVICE_ID_INTEL_82965PM:
141 case PCI_DEVICE_ID_INTEL_82Q35:
142 case PCI_DEVICE_ID_INTEL_82G33:
143 case PCI_DEVICE_ID_INTEL_82Q33:
144 mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
145 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
146 break;
147 case PCI_DEVICE_ID_INTEL_82946:
148 case PCI_DEVICE_ID_INTEL_82Q965:
149 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
150 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
151 case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
152 case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
153 case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
154 mchbar_phys = pci_read_long(nb, 0x48);
155
156 /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
157 * If it isn't, try to set it. This may fail, because there is
158 * some bit that locks that bit, and isn't in the public
159 * datasheets.
160 */
161
162 if(!(mchbar_phys & 1))
163 {
164 printf("Access to the MCHBAR is currently disabled, "
165 "attempting to enable.\n");
166 mchbar_phys |= 0x1;
167 pci_write_long(nb, 0x48, mchbar_phys);
168 if(pci_read_long(nb, 0x48) & 1)
169 printf("Enabled successfully.\n");
170 else
171 printf("Enable FAILED!\n");
172 }
173 mchbar_phys &= 0xfffffffe;
174 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
175 break;
176 case PCI_DEVICE_ID_INTEL_82443LX:
177 case PCI_DEVICE_ID_INTEL_82443BX:
178 case PCI_DEVICE_ID_INTEL_82810:
179 case PCI_DEVICE_ID_INTEL_82810E_DC:
180 case PCI_DEVICE_ID_INTEL_82810_DC:
181 case PCI_DEVICE_ID_INTEL_82830M:
182 printf("This northbridge does not have MCHBAR.\n");
183 return 1;
184 case PCI_DEVICE_ID_INTEL_82XX4X:
185 case PCI_DEVICE_ID_INTEL_82Q45:
186 case PCI_DEVICE_ID_INTEL_82G45:
187 case PCI_DEVICE_ID_INTEL_82G41:
188 case PCI_DEVICE_ID_INTEL_82B43:
189 case PCI_DEVICE_ID_INTEL_82B43_2:
190 case PCI_DEVICE_ID_INTEL_82X38:
191 case PCI_DEVICE_ID_INTEL_32X0:
192 mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
193 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
194 break;
195 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
196 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
197 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
198 mchbar_phys = pci_read_long(nb, 0x48);
199 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
200 mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
201 break;
202 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
203 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
204 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
205 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
206 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
207 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
208 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
209 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
210 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
211 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
212 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
213 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
214 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D:
215 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M:
216 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
217 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
218 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
219 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
220 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
221 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
222 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
223 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
224 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
225 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
226 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
227 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
228 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
229 case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
230 case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
231 case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
232 mchbar_phys = pci_read_long(nb, 0x48);
233 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
234 mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
235 size = 32768;
236 break;
237 case PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U:
238 mchbar_phys = pci_read_long(nb, 0x48);
239 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
240 mchbar_phys &= 0x0000007fffff0000UL; /* 38:16 */
241 size = 32768;
242 break;
243 default:
244 printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
245 printf("Error: Unknown PCI id: %08x/%08x\n", nb->vendor_id, nb->device_id);
246 return 1;
247 }
248
249 mchbar = map_physical(mchbar_phys, size);
250
251 if (mchbar == NULL) {
252 if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
253 perror("Error mapping BAR6");
254 else
255 perror("Error mapping MCHBAR");
256 exit(1);
257 }
258
259 if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
260 printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
261 else
262 printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
263
264 for (i = 0; i < size; i += 4) {
265 if (read32(mchbar + i))
266 printf("0x%04x: 0x%08"PRIx32"\n", i, read32(mchbar+i));
267 }
268
269 switch (nb->device_id)
270 {
271 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
272 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
273 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
274 printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
275 dump_timings ();
276 if (dump_spd_file != NULL)
277 printf("\nCreating a memory timings file is not supported on this chipset.\n");
278 break;
279 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
280 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
281 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
282 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
283 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
284 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
285 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
286 ivybridge_dump_timings(dump_spd_file);
287 break;
288 default:
289 if (dump_spd_file != NULL)
290 printf("\nCreating a memory timings file is not supported on this chipset.\n");
291 }
292 unmap_physical((void *)mchbar, size);
293 return 0;
294 }
295