1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #define __SIMPLE_DEVICE__
4
5 #include <arch/ioapic.h>
6 #include <assert.h>
7 #include <console/console.h>
8 #include <device/pci.h>
9 #include <device/pci_ops.h>
10 #include <intelblocks/gpmr.h>
11 #include <intelblocks/itss.h>
12 #include <intelblocks/lpc_lib.h>
13 #include <intelblocks/pcr.h>
14 #include <lib.h>
15 #include "lpc_def.h"
16 #include <soc/irq.h>
17 #include <soc/pci_devs.h>
18 #include <soc/pcr_ids.h>
19 #include <southbridge/intel/common/acpi_pirq_gen.h>
20
lpc_enable_fixed_io_ranges(uint16_t io_enables)21 uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
22 {
23 uint16_t reg_io_enables;
24
25 reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
26 io_enables |= reg_io_enables;
27 pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
28 if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
29 gpmr_write32(GPMR_LPCIOE, io_enables);
30
31 return io_enables;
32 }
33
lpc_get_fixed_io_decode(void)34 uint16_t lpc_get_fixed_io_decode(void)
35 {
36 return pci_read_config16(PCH_DEV_LPC, LPC_IO_DECODE);
37 }
38
lpc_set_fixed_io_ranges(uint16_t io_ranges,uint16_t mask)39 uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask)
40 {
41 uint16_t reg_io_ranges;
42
43 reg_io_ranges = lpc_get_fixed_io_decode() & ~mask;
44 io_ranges |= reg_io_ranges & mask;
45 pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges);
46 if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
47 gpmr_write32(GPMR_LPCIOD, io_ranges);
48
49 return io_ranges;
50 }
51
52 /*
53 * Find the first unused IO window.
54 * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
55 */
find_unused_pmio_window(void)56 static int find_unused_pmio_window(void)
57 {
58 int i;
59 uint32_t lgir;
60
61 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
62 lgir = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i));
63
64 if (!(lgir & LPC_LGIR_EN))
65 return i;
66 }
67
68 return -1;
69 }
70
lpc_open_pmio_window(uint16_t base,uint16_t size)71 void lpc_open_pmio_window(uint16_t base, uint16_t size)
72 {
73 int i, lgir_reg_num;
74 uint32_t lgir_reg_offset, lgir, window_size, alignment;
75 resource_t bridged_size, bridge_base;
76
77 switch (base) {
78 case 0:
79 printk(BIOS_ERR, "LPC IO decode base 0!\n");
80 return;
81 case 0x2e:
82 case 0x2f:
83 if (size > 2)
84 break;
85 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_SUPERIO_2E_2F\n");
86 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_SUPERIO_2E_2F);
87 return;
88 case 0x4e:
89 case 0x4f:
90 if (size > 2)
91 break;
92 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_EC_4E_4F\n");
93 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_EC_4E_4F);
94 return;
95 case 0x60:
96 case 0x64:
97 if (size > 1)
98 break;
99 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_KBC_60_64\n");
100 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_KBC_60_64);
101 return;
102 case 0x62:
103 case 0x66:
104 if (size > 1)
105 break;
106 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_EC_62_66\n");
107 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_EC_62_66);
108 return;
109 case 0x200:
110 if (size > 8)
111 break;
112 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_LGE_200\n");
113 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_LGE_200);
114 return;
115 case 0x208:
116 if (size > 8)
117 break;
118 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_HGE_208\n");
119 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_HGE_208);
120 return;
121 case 0x2f8: /* Don't support secondary ranges */
122 if (size > 8)
123 break;
124 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_COMB_EN\n");
125 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_COMB_EN);
126 pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_COMB_RANGE_MASK,
127 LPC_IOD_COMB_RANGE);
128 return;
129 case 0x378: /* Don't support secondary ranges */
130 if (size > 8)
131 break;
132 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_LPT_EN\n");
133 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_HGE_208);
134 pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_LPT_RANGE_MASK,
135 LPC_IOD_LPT_RANGE);
136 return;
137 case 0x3f0: /* Don't support secondary ranges */
138 if (size > 8)
139 break;
140 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_FDD_EN\n");
141 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_FDD_EN);
142 pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_FDD_RANGE_MASK,
143 LPC_IOD_FDD_RANGE);
144 return;
145 case 0x3f8: /* Don't support secondary ranges */
146 if (size > 8)
147 break;
148 printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_COMA_EN\n");
149 pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_COMA_EN);
150 pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_COMA_RANGE_MASK,
151 LPC_IOD_COMA_RANGE);
152 return;
153 }
154
155 printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n",
156 base, size);
157
158 bridged_size = 0;
159 bridge_base = base;
160
161 while (bridged_size < size) {
162 /* Each IO range register can only open a 256-byte window. */
163 window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE);
164
165 if (window_size <= 0)
166 return;
167
168 /* Window size must be a power of two for the AMASK to work. */
169 alignment = 1UL << (log2_ceil(window_size));
170 window_size = ALIGN_UP(window_size, alignment);
171
172 /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18]. */
173 lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
174 lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
175
176 /* Skip programming if same range already programmed. */
177 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
178 if (lgir == pci_read_config32(PCH_DEV_LPC,
179 LPC_GENERIC_IO_RANGE(i)))
180 return;
181 }
182
183 lgir_reg_num = find_unused_pmio_window();
184 if (lgir_reg_num < 0) {
185 printk(BIOS_ERR,
186 "LPC: Cannot open IO window: %llx size %llx\n",
187 bridge_base, size - bridged_size);
188 printk(BIOS_ERR, "No more IO windows\n");
189 return;
190 }
191 lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
192
193 pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
194 if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
195 gpmr_write32(GPMR_LPCLGIR1 + lgir_reg_num * 4, lgir);
196
197 printk(BIOS_DEBUG,
198 "LPC: Opened IO window LGIR%d: base %llx size %x\n",
199 lgir_reg_num, bridge_base, window_size);
200
201 bridged_size += window_size;
202 bridge_base += window_size;
203 }
204 }
205
lpc_open_mmio_window(uintptr_t base,size_t size)206 void lpc_open_mmio_window(uintptr_t base, size_t size)
207 {
208 uint32_t lgmr;
209
210 lgmr = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE);
211
212 if (lgmr & LPC_LGMR_EN) {
213 printk(BIOS_ERR,
214 "LPC: Cannot open window to resource %lx size %zx\n",
215 base, size);
216 printk(BIOS_ERR, "LPC: MMIO window already in use\n");
217 return;
218 }
219
220 if (size > LPC_LGMR_WINDOW_SIZE) {
221 printk(BIOS_WARNING,
222 "LPC: Resource %lx size %zx larger than window(%x)\n",
223 base, size, LPC_LGMR_WINDOW_SIZE);
224 }
225
226 lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN;
227
228 pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
229 if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
230 gpmr_write32(GPMR_LPCGMR, lgmr);
231 }
232
233 /*
234 * Set LPC BIOS Control register based on input bit field.
235 */
lpc_set_bios_control_reg(uint8_t bios_cntl_bit)236 static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)
237 {
238 pci_devfn_t dev = PCH_DEV_LPC;
239 uint8_t bc_cntl;
240
241 assert(IS_POWER_OF_2(bios_cntl_bit));
242 bc_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
243 bc_cntl |= bios_cntl_bit;
244 pci_write_config8(dev, LPC_BIOS_CNTL, bc_cntl);
245
246 /*
247 * Ensure an additional read back after performing lock down
248 */
249 pci_read_config8(PCH_DEV_LPC, LPC_BIOS_CNTL);
250 }
251
252 /*
253 * Set LPC BIOS Control BILD bit.
254 */
lpc_set_bios_interface_lock_down(void)255 void lpc_set_bios_interface_lock_down(void)
256 {
257 lpc_set_bios_control_reg(LPC_BC_BILD);
258 }
259
260 /*
261 * Set LPC BIOS Control LE bit.
262 */
lpc_set_lock_enable(void)263 void lpc_set_lock_enable(void)
264 {
265 lpc_set_bios_control_reg(LPC_BC_LE);
266 }
267
268 /*
269 * Set LPC BIOS Control EISS bit.
270 */
lpc_set_eiss(void)271 void lpc_set_eiss(void)
272 {
273 lpc_set_bios_control_reg(LPC_BC_EISS);
274 }
275
lpc_configure_write_protect(bool status)276 static void lpc_configure_write_protect(bool status)
277 {
278 const pci_devfn_t dev = PCH_DEV_LPC;
279 uint8_t bios_cntl;
280
281 bios_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
282 if (status)
283 bios_cntl &= ~LPC_BC_WPD;
284 else
285 bios_cntl |= LPC_BC_WPD;
286 pci_write_config8(dev, LPC_BIOS_CNTL, bios_cntl);
287 }
288
289 /* Enable LPC Write Protect. */
lpc_enable_wp(void)290 void lpc_enable_wp(void)
291 {
292 lpc_configure_write_protect(true);
293 }
294
295 /* Disable LPC Write Protect. */
lpc_disable_wp(void)296 void lpc_disable_wp(void)
297 {
298 lpc_configure_write_protect(false);
299 }
300
lpc_set_bde(void)301 void lpc_set_bde(void)
302 {
303 const pci_devfn_t dev = PCH_DEV_LPC;
304 uint32_t bde;
305
306 bde = pci_read_config32(dev, LPC_BIOS_DECODE_EN);
307 bde |= LPC_BIOS_DECODE_LOCK;
308 pci_write_config32(dev, LPC_BIOS_DECODE_EN, bde);
309 }
310
311 /*
312 * Set LPC Serial IRQ mode.
313 */
lpc_set_serirq_mode(enum serirq_mode mode)314 void lpc_set_serirq_mode(enum serirq_mode mode)
315 {
316 pci_devfn_t dev = PCH_DEV_LPC;
317 uint8_t scnt;
318
319 scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);
320 scnt &= ~(LPC_SCNT_EN | LPC_SCNT_MODE);
321
322 switch (mode) {
323 case SERIRQ_QUIET:
324 scnt |= LPC_SCNT_EN;
325 break;
326 case SERIRQ_CONTINUOUS:
327 scnt |= LPC_SCNT_EN | LPC_SCNT_MODE;
328 break;
329 case SERIRQ_OFF:
330 default:
331 break;
332 }
333
334 pci_write_config8(dev, LPC_SERIRQ_CTL, scnt);
335 }
336
lpc_io_setup_comm_a_b(void)337 void lpc_io_setup_comm_a_b(void)
338 {
339 /* ComA Range 3F8h-3FFh [2:0] */
340 uint16_t com_ranges = LPC_IOD_COMA_RANGE;
341 uint16_t com_enable = LPC_IOE_COMA_EN;
342 uint16_t com_mask = LPC_IOD_COMA_RANGE_MASK;
343
344 /* ComB Range 2F8h-2FFh [6:4] */
345 if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
346 com_ranges |= LPC_IOD_COMB_RANGE;
347 com_enable |= LPC_IOE_COMB_EN;
348 com_mask |= LPC_IOD_COMB_RANGE_MASK;
349 }
350
351 /* Setup I/O Decode Range Register for LPC */
352 lpc_set_fixed_io_ranges(com_ranges, com_mask);
353 /* Enable ComA and ComB Port */
354 lpc_enable_fixed_io_ranges(com_enable);
355 }
356
lpc_set_gen_decode_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])357 static void lpc_set_gen_decode_range(
358 uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
359 {
360 size_t i;
361
362 /* Set in PCI generic decode range registers */
363 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
364 pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]);
365 if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
366 gpmr_write32(GPMR_LPCLGIR1 + i * 4, gen_io_dec[i]);
367 }
368 }
369
pch_enable_lpc(void)370 void pch_enable_lpc(void)
371 {
372 uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES];
373
374 soc_get_gen_io_dec_range(gen_io_dec);
375 lpc_set_gen_decode_range(gen_io_dec);
376 if (ENV_PAYLOAD_LOADER)
377 pch_pirq_init();
378 }
379
lpc_enable_pci_clk_cntl(void)380 void lpc_enable_pci_clk_cntl(void)
381 {
382 pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);
383 }
384
lpc_disable_clkrun(void)385 void lpc_disable_clkrun(void)
386 {
387 const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL);
388 pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);
389 }
390
391 /* PCH I/O APIC redirection entries */
392 #define PCH_REDIR_ETR 120
393
394 /* Enable PCH IOAPIC */
pch_enable_ioapic(void)395 void pch_enable_ioapic(void)
396 {
397 /* affirm full set of redirection table entries ("write once") */
398 ioapic_set_max_vectors(IO_APIC_ADDR, PCH_REDIR_ETR);
399
400 register_new_ioapic_gsi0(IO_APIC_ADDR);
401 }
402
403 static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
404 [0] = PCH_IRQ11, /* PIRQ_A */
405 [1] = PCH_IRQ10, /* PIRQ_B */
406 [2] = PCH_IRQ11, /* PIRQ_C */
407 [3] = PCH_IRQ11, /* PIRQ_D */
408 [4] = PCH_IRQ11, /* PIRQ_E */
409 [5] = PCH_IRQ11, /* PIRQ_F */
410 [6] = PCH_IRQ11, /* PIRQ_G */
411 [7] = PCH_IRQ11, /* PIRQ_H */
412 };
413
lpc_get_pic_pirq_routing(size_t * num)414 const uint8_t *lpc_get_pic_pirq_routing(size_t *num)
415 {
416 *num = ARRAY_SIZE(pch_interrupt_routing);
417 return pch_interrupt_routing;
418 }
419
420 /*
421 * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
422 * 0x00 - 0000 = Reserved
423 * 0x01 - 0001 = Reserved
424 * 0x02 - 0010 = Reserved
425 * 0x03 - 0011 = IRQ3
426 * 0x04 - 0100 = IRQ4
427 * 0x05 - 0101 = IRQ5
428 * 0x06 - 0110 = IRQ6
429 * 0x07 - 0111 = IRQ7
430 * 0x08 - 1000 = Reserved
431 * 0x09 - 1001 = IRQ9
432 * 0x0A - 1010 = IRQ10
433 * 0x0B - 1011 = IRQ11
434 * 0x0C - 1100 = IRQ12
435 * 0x0D - 1101 = Reserved
436 * 0x0E - 1110 = IRQ14
437 * 0x0F - 1111 = IRQ15
438 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
439 * 0x80 - The PIRQ is not routed.
440 */
pch_pirq_init(void)441 void pch_pirq_init(void)
442 {
443 const struct device *irq_dev;
444 itss_irq_init(pch_interrupt_routing);
445
446 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
447 uint8_t int_pin = 0, int_line = 0;
448
449 if (!is_enabled_pci(irq_dev))
450 continue;
451
452 int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN);
453
454 switch (int_pin) {
455 case 1: /* INTA# */
456 int_line = PCH_IRQ11;
457 break;
458 case 2: /* INTB# */
459 int_line = PCH_IRQ10;
460 break;
461 case 3: /* INTC# */
462 int_line = PCH_IRQ11;
463 break;
464 case 4: /* INTD# */
465 int_line = PCH_IRQ11;
466 break;
467 }
468
469 if (!int_line)
470 continue;
471
472 pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line);
473 }
474 }
475
476 #define PPI_PORT_B 0x61
477 #define SERR_DIS (1 << 2)
478 #define CMOS_NMI 0x70
479 #define NMI_DIS (1 << 7)
480
481 /* LPC MISC programming */
pch_misc_init(void)482 void pch_misc_init(void)
483 {
484 uint8_t reg8;
485
486 /* Setup NMI on errors, disable SERR */
487 reg8 = (inb(PPI_PORT_B)) & 0xf0;
488 outb((reg8 | SERR_DIS), PPI_PORT_B);
489
490 /* Disable NMI sources */
491 outb(NMI_DIS, CMOS_NMI);
492 }
493