1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
24
25 #include "pipe/p_context.h"
26 #include "pipe/p_state.h"
27 #include "util/u_draw.h"
28 #include "util/u_inlines.h"
29 #include "util/format/u_format.h"
30 #include "translate/translate.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34 #include "nvc0/nvc0_resource.h"
35
36 #include "nvc0/nvc0_3d.xml.h"
37
38 void
nvc0_vertex_state_delete(struct pipe_context * pipe,void * hwcso)39 nvc0_vertex_state_delete(struct pipe_context *pipe,
40 void *hwcso)
41 {
42 struct nvc0_vertex_stateobj *so = hwcso;
43
44 if (so->translate)
45 so->translate->release(so->translate);
46 FREE(hwcso);
47 }
48
49 void *
nvc0_vertex_state_create(struct pipe_context * pipe,unsigned num_elements,const struct pipe_vertex_element * elements)50 nvc0_vertex_state_create(struct pipe_context *pipe,
51 unsigned num_elements,
52 const struct pipe_vertex_element *elements)
53 {
54 struct nvc0_context *nvc0 = nvc0_context(pipe);
55 struct nvc0_vertex_stateobj *so;
56 struct translate_key transkey;
57 unsigned i;
58 unsigned src_offset_max = 0;
59
60 so = CALLOC(1, sizeof(*so) +
61 num_elements * sizeof(struct nvc0_vertex_element));
62 if (!so)
63 return NULL;
64 so->num_elements = num_elements;
65 so->instance_elts = 0;
66 so->instance_bufs = 0;
67 so->shared_slots = false;
68 so->need_conversion = false;
69
70 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
71
72 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
73 so->min_instance_div[i] = 0xffffffff;
74
75 transkey.nr_elements = 0;
76 transkey.output_stride = 0;
77
78 for (i = 0; i < num_elements; ++i) {
79 const struct pipe_vertex_element *ve = &elements[i];
80 const unsigned vbi = ve->vertex_buffer_index;
81 unsigned size;
82 enum pipe_format fmt = ve->src_format;
83
84 so->element[i].pipe = elements[i];
85 so->element[i].state = nvc0_vertex_format[fmt].vtx;
86
87 if (!so->element[i].state) {
88 switch (util_format_get_nr_components(fmt)) {
89 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
90 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
91 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
92 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
93 default:
94 assert(0);
95 FREE(so);
96 return NULL;
97 }
98 so->element[i].state = nvc0_vertex_format[fmt].vtx;
99 so->need_conversion = true;
100 util_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
101 "Converting vertex element %d, no hw format %s",
102 i, util_format_name(ve->src_format));
103 }
104 size = util_format_get_blocksize(fmt);
105
106 src_offset_max = MAX2(src_offset_max, ve->src_offset);
107
108 if (so->vb_access_size[vbi] < (ve->src_offset + size))
109 so->vb_access_size[vbi] = ve->src_offset + size;
110
111 if (unlikely(ve->instance_divisor)) {
112 so->instance_elts |= 1 << i;
113 so->instance_bufs |= 1 << vbi;
114 if (ve->instance_divisor < so->min_instance_div[vbi])
115 so->min_instance_div[vbi] = ve->instance_divisor;
116 }
117
118 so->strides[vbi] = ve->src_stride;
119 if (!ve->src_stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
120 so->constant_vbos |= 1 << vbi;
121
122 if (1) {
123 unsigned ca;
124 unsigned j = transkey.nr_elements++;
125
126 ca = util_format_description(fmt)->channel[0].size / 8;
127 if (ca != 1 && ca != 2)
128 ca = 4;
129
130 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
131 transkey.element[j].input_format = ve->src_format;
132 transkey.element[j].input_buffer = vbi;
133 transkey.element[j].input_offset = ve->src_offset;
134 transkey.element[j].instance_divisor = ve->instance_divisor;
135
136 transkey.output_stride = align(transkey.output_stride, ca);
137 transkey.element[j].output_format = fmt;
138 transkey.element[j].output_offset = transkey.output_stride;
139 transkey.output_stride += size;
140
141 so->element[i].state_alt = so->element[i].state;
142 so->element[i].state_alt |= transkey.element[j].output_offset << 7;
143 }
144
145 so->element[i].state |= i << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
146 }
147 transkey.output_stride = align(transkey.output_stride, 4);
148
149 so->size = transkey.output_stride;
150 so->translate = translate_create(&transkey);
151
152 if (so->instance_elts || src_offset_max >= (1 << 14))
153 return so;
154 so->shared_slots = true;
155
156 for (i = 0; i < num_elements; ++i) {
157 const unsigned b = elements[i].vertex_buffer_index;
158 const unsigned s = elements[i].src_offset;
159 so->element[i].state &= ~NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__MASK;
160 so->element[i].state |= b << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
161 so->element[i].state |= s << NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT;
162 }
163 return so;
164 }
165
166 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
167 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
168 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
169
170 #define VTX_ATTR(a, c, t, s) \
171 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
172 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
173 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
174 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
175
176 static void
nvc0_set_constant_vertex_attrib(struct nvc0_context * nvc0,const unsigned a)177 nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a)
178 {
179 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
180 struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe;
181 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index];
182 uint32_t mode;
183 const struct util_format_description *desc;
184 void *dst;
185 const void *src = (const uint8_t *)vb->buffer.user + ve->src_offset;
186 assert(vb->is_user_buffer);
187
188 desc = util_format_description(ve->src_format);
189
190 PUSH_SPACE(push, 6);
191 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 5);
192 dst = &push->cur[1];
193 util_format_unpack_rgba(ve->src_format, dst, src, 1);
194 if (desc->channel[0].pure_integer) {
195 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
196 mode = VTX_ATTR(a, 4, SINT, 32);
197 } else {
198 mode = VTX_ATTR(a, 4, UINT, 32);
199 }
200 } else {
201 mode = VTX_ATTR(a, 4, FLOAT, 32);
202 }
203 push->cur[0] = mode;
204 push->cur += 5;
205 }
206
207 static inline void
nvc0_user_vbuf_range(struct nvc0_context * nvc0,int vbi,uint32_t * base,uint32_t * size)208 nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi,
209 uint32_t *base, uint32_t *size)
210 {
211 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
212 const uint32_t div = nvc0->vertex->min_instance_div[vbi];
213 *base = nvc0->instance_off * nvc0->vertex->strides[vbi];
214 *size = (nvc0->instance_max / div) * nvc0->vertex->strides[vbi] +
215 nvc0->vertex->vb_access_size[vbi];
216 } else {
217 /* NOTE: if there are user buffers, we *must* have index bounds */
218 assert(nvc0->vb_elt_limit != ~0);
219 *base = nvc0->vb_elt_first * nvc0->vertex->strides[vbi];
220 *size = nvc0->vb_elt_limit * nvc0->vertex->strides[vbi] +
221 nvc0->vertex->vb_access_size[vbi];
222 }
223 }
224
225 static inline void
nvc0_release_user_vbufs(struct nvc0_context * nvc0)226 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
227 {
228 if (nvc0->vbo_user) {
229 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP);
230 nouveau_scratch_done(&nvc0->base);
231 }
232 }
233
234 static void
nvc0_update_user_vbufs(struct nvc0_context * nvc0)235 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
236 {
237 uint64_t address[PIPE_MAX_ATTRIBS];
238 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
239 int i;
240 uint32_t written = 0;
241
242 PUSH_SPACE(push, nvc0->vertex->num_elements * 8);
243 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
244 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
245 const unsigned b = ve->vertex_buffer_index;
246 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
247 uint32_t base, size;
248
249 if (!(nvc0->vbo_user & (1 << b)))
250 continue;
251 if (nvc0->constant_vbos & (1 << b)) {
252 nvc0_set_constant_vertex_attrib(nvc0, i);
253 continue;
254 }
255 nvc0_user_vbuf_range(nvc0, b, &base, &size);
256
257 if (!(written & (1 << b))) {
258 struct nouveau_bo *bo;
259 const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
260 written |= 1 << b;
261 address[b] = nouveau_scratch_data(&nvc0->base, vb->buffer.user,
262 base, size, &bo);
263 if (bo)
264 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP, bo_flags, bo);
265
266 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
267 }
268
269 BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
270 PUSH_DATA (push, i);
271 PUSH_DATAh(push, address[b] + base + size - 1);
272 PUSH_DATA (push, address[b] + base + size - 1);
273 PUSH_DATAh(push, address[b] + ve->src_offset);
274 PUSH_DATA (push, address[b] + ve->src_offset);
275 }
276 nvc0->base.vbo_dirty = true;
277 }
278
279 static void
nvc0_update_user_vbufs_shared(struct nvc0_context * nvc0)280 nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0)
281 {
282 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
283 uint32_t mask = nvc0->vbo_user & ~nvc0->constant_vbos;
284
285 PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
286 while (mask) {
287 struct nouveau_bo *bo;
288 const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
289 uint64_t address;
290 uint32_t base, size;
291 const int b = ffs(mask) - 1;
292 mask &= ~(1 << b);
293
294 nvc0_user_vbuf_range(nvc0, b, &base, &size);
295
296 address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].buffer.user,
297 base, size, &bo);
298 if (bo)
299 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP, bo_flags, bo);
300
301 BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
302 PUSH_DATA (push, b);
303 PUSH_DATAh(push, address + base + size - 1);
304 PUSH_DATA (push, address + base + size - 1);
305 PUSH_DATAh(push, address);
306 PUSH_DATA (push, address);
307
308 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
309 }
310
311 mask = nvc0->state.constant_elts;
312 while (mask) {
313 int i = ffs(mask) - 1;
314 mask &= ~(1 << i);
315 nvc0_set_constant_vertex_attrib(nvc0, i);
316 }
317 }
318
319 static void
nvc0_validate_vertex_buffers(struct nvc0_context * nvc0)320 nvc0_validate_vertex_buffers(struct nvc0_context *nvc0)
321 {
322 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
323 const struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
324 uint32_t refd = 0;
325 unsigned i;
326
327 PUSH_SPACE(push, vertex->num_elements * 8);
328 for (i = 0; i < vertex->num_elements; ++i) {
329 const struct nvc0_vertex_element *ve;
330 const struct pipe_vertex_buffer *vb;
331 struct nv04_resource *res;
332 unsigned b;
333 unsigned limit, offset;
334
335 if (nvc0->state.constant_elts & (1 << i))
336 continue;
337 ve = &vertex->element[i];
338 b = ve->pipe.vertex_buffer_index;
339 vb = &nvc0->vtxbuf[b];
340
341 if (nvc0->vbo_user & (1 << b)) {
342 if (!(nvc0->constant_vbos & (1 << b))) {
343 if (ve->pipe.instance_divisor) {
344 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
345 PUSH_DATA (push, ve->pipe.instance_divisor);
346 }
347 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 1);
348 PUSH_DATA (push, (1 << 12) | vertex->strides[b]);
349 }
350 /* address/value set in nvc0_update_user_vbufs */
351 continue;
352 }
353 res = nv04_resource(vb->buffer.resource);
354 offset = ve->pipe.src_offset + vb->buffer_offset;
355 limit = vb->buffer.resource->width0 - 1;
356
357 if (unlikely(ve->pipe.instance_divisor)) {
358 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4);
359 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vertex->strides[b]);
360 PUSH_DATAh(push, res->address + offset);
361 PUSH_DATA (push, res->address + offset);
362 PUSH_DATA (push, ve->pipe.instance_divisor);
363 } else {
364 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 3);
365 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vertex->strides[b]);
366 PUSH_DATAh(push, res->address + offset);
367 PUSH_DATA (push, res->address + offset);
368 }
369
370 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS)
371 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
372 else
373 BEGIN_NVC0(push, SUBC_3D(TU102_3D_VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
374 PUSH_DATAh(push, res->address + limit);
375 PUSH_DATA (push, res->address + limit);
376
377 if (!(refd & (1 << b))) {
378 refd |= 1 << b;
379 BCTX_REFN(nvc0->bufctx_3d, 3D_VTX, res, RD);
380 }
381 }
382 if (nvc0->vbo_user)
383 nvc0_update_user_vbufs(nvc0);
384 }
385
386 static void
nvc0_validate_vertex_buffers_shared(struct nvc0_context * nvc0)387 nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0)
388 {
389 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
390 unsigned b;
391 const uint32_t mask = nvc0->vbo_user;
392
393 PUSH_SPACE(push, nvc0->num_vtxbufs * 8 + nvc0->vertex->num_elements);
394 for (b = 0; b < nvc0->num_vtxbufs; ++b) {
395 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
396 struct nv04_resource *buf;
397 uint32_t offset, limit;
398
399 if (mask & (1 << b)) {
400 if (!(nvc0->constant_vbos & (1 << b))) {
401 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 1);
402 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | nvc0->vertex->strides[b]);
403 }
404 /* address/value set in nvc0_update_user_vbufs_shared */
405 continue;
406 } else if (!vb->buffer.resource) {
407 /* there can be holes in the vertex buffer lists */
408 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0);
409 continue;
410 }
411 buf = nv04_resource(vb->buffer.resource);
412 offset = vb->buffer_offset;
413 limit = buf->base.width0 - 1;
414
415 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 3);
416 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | nvc0->vertex->strides[b]);
417 PUSH_DATAh(push, buf->address + offset);
418 PUSH_DATA (push, buf->address + offset);
419
420 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS)
421 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
422 else
423 BEGIN_NVC0(push, SUBC_3D(TU102_3D_VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
424 PUSH_DATAh(push, buf->address + limit);
425 PUSH_DATA (push, buf->address + limit);
426
427 BCTX_REFN(nvc0->bufctx_3d, 3D_VTX, buf, RD);
428 }
429 /* If there are more elements than buffers, we might not have unset
430 * fetching on the later elements.
431 */
432 for (; b < nvc0->vertex->num_elements; ++b)
433 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0);
434
435 if (nvc0->vbo_user)
436 nvc0_update_user_vbufs_shared(nvc0);
437 }
438
439 void
nvc0_vertex_arrays_validate(struct nvc0_context * nvc0)440 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
441 {
442 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
443 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
444 struct nvc0_vertex_element *ve;
445 uint32_t const_vbos;
446 unsigned i;
447 uint8_t vbo_mode;
448 bool update_vertex;
449
450 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
451
452 assert(vertex);
453 if (unlikely(vertex->need_conversion) ||
454 unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
455 vbo_mode = 3;
456 } else if (nvc0->vbo_user & ~nvc0->constant_vbos) {
457 vbo_mode = nvc0->vbo_push_hint ? 1 : 0;
458 } else {
459 vbo_mode = 0;
460 }
461 const_vbos = vbo_mode ? 0 : nvc0->constant_vbos;
462
463 update_vertex = (nvc0->dirty_3d & NVC0_NEW_3D_VERTEX) ||
464 (const_vbos != nvc0->state.constant_vbos) ||
465 (vbo_mode != nvc0->state.vbo_mode);
466
467 if (update_vertex) {
468 const unsigned n = MAX2(vertex->num_elements, nvc0->state.num_vtxelts);
469
470 simple_mtx_assert_locked(&nvc0->screen->state_lock);
471 nvc0->state.constant_vbos = const_vbos;
472 nvc0->state.constant_elts = 0;
473 nvc0->state.num_vtxelts = vertex->num_elements;
474 nvc0->state.vbo_mode = vbo_mode;
475
476 if (unlikely(vbo_mode)) {
477 if (unlikely(nvc0->state.instance_elts & 3)) {
478 /* translate mode uses only 2 vertex buffers */
479 nvc0->state.instance_elts &= ~3;
480 PUSH_SPACE(push, 3);
481 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_PER_INSTANCE(0)), 2);
482 PUSH_DATA (push, 0);
483 PUSH_DATA (push, 0);
484 }
485
486 PUSH_SPACE(push, n * 2 + 4);
487
488 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
489 for (i = 0; i < vertex->num_elements; ++i)
490 PUSH_DATA(push, vertex->element[i].state_alt);
491 for (; i < n; ++i)
492 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
493
494 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 1);
495 PUSH_DATA (push, (1 << 12) | vertex->size);
496 for (i = 1; i < n; ++i)
497 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
498 } else {
499 uint32_t *restrict data;
500
501 if (unlikely(vertex->instance_elts != nvc0->state.instance_elts)) {
502 nvc0->state.instance_elts = vertex->instance_elts;
503 assert(n); /* if (n == 0), both masks should be 0 */
504 PUSH_SPACE(push, 3);
505 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
506 PUSH_DATA (push, n);
507 PUSH_DATA (push, vertex->instance_elts);
508 }
509
510 PUSH_SPACE(push, n * 2 + 1);
511 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
512 data = push->cur;
513 push->cur += n;
514 for (i = 0; i < vertex->num_elements; ++i) {
515 ve = &vertex->element[i];
516 data[i] = ve->state;
517 if (unlikely(const_vbos & (1 << ve->pipe.vertex_buffer_index))) {
518 nvc0->state.constant_elts |= 1 << i;
519 data[i] |= NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST;
520 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
521 }
522 }
523 for (; i < n; ++i) {
524 data[i] = NVC0_3D_VERTEX_ATTRIB_INACTIVE;
525 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
526 }
527 }
528 }
529 if (nvc0->state.vbo_mode) /* using translate, don't set up arrays here */
530 return;
531
532 if (vertex->shared_slots)
533 nvc0_validate_vertex_buffers_shared(nvc0);
534 else
535 nvc0_validate_vertex_buffers(nvc0);
536 }
537
538 #define NVC0_PRIM_GL_CASE(n) \
539 case MESA_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
540
541 static inline unsigned
nvc0_prim_gl(unsigned prim)542 nvc0_prim_gl(unsigned prim)
543 {
544 switch (prim) {
545 NVC0_PRIM_GL_CASE(POINTS);
546 NVC0_PRIM_GL_CASE(LINES);
547 NVC0_PRIM_GL_CASE(LINE_LOOP);
548 NVC0_PRIM_GL_CASE(LINE_STRIP);
549 NVC0_PRIM_GL_CASE(TRIANGLES);
550 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
551 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
552 NVC0_PRIM_GL_CASE(QUADS);
553 NVC0_PRIM_GL_CASE(QUAD_STRIP);
554 NVC0_PRIM_GL_CASE(POLYGON);
555 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
556 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
557 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
558 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
559 NVC0_PRIM_GL_CASE(PATCHES);
560 default:
561 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
562 }
563 }
564
565 static void
nvc0_draw_vbo_kick_notify(struct nouveau_context * context)566 nvc0_draw_vbo_kick_notify(struct nouveau_context *context)
567 {
568 _nouveau_fence_update(context->screen, true);
569 }
570
571 static void
nvc0_draw_arrays(struct nvc0_context * nvc0,unsigned mode,unsigned start,unsigned count,unsigned instance_count)572 nvc0_draw_arrays(struct nvc0_context *nvc0,
573 unsigned mode, unsigned start, unsigned count,
574 unsigned instance_count)
575 {
576 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
577 unsigned prim;
578
579 if (nvc0->state.index_bias) {
580 /* index_bias is implied 0 if !info->index_size (really ?) */
581 /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
582 PUSH_SPACE(push, 2);
583 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
584 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
585 nvc0->state.index_bias = 0;
586 }
587
588 prim = nvc0_prim_gl(mode);
589
590 while (instance_count--) {
591 PUSH_SPACE(push, 6);
592 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
593 PUSH_DATA (push, prim);
594 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
595 PUSH_DATA (push, start);
596 PUSH_DATA (push, count);
597 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
598
599 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
600 }
601 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1);
602 }
603
604 static void
nvc0_draw_elements_inline_u08(struct nouveau_pushbuf * push,const uint8_t * map,unsigned start,unsigned count)605 nvc0_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
606 unsigned start, unsigned count)
607 {
608 map += start;
609
610 if (count & 3) {
611 unsigned i;
612 PUSH_SPACE(push, 4);
613 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), count & 3);
614 for (i = 0; i < (count & 3); ++i)
615 PUSH_DATA(push, *map++);
616 count &= ~3;
617 }
618 while (count) {
619 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
620
621 PUSH_SPACE(push, nr + 1);
622 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U8), nr);
623 for (i = 0; i < nr; ++i) {
624 PUSH_DATA(push,
625 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
626 map += 4;
627 }
628 count -= nr * 4;
629 }
630 }
631
632 static void
nvc0_draw_elements_inline_u16(struct nouveau_pushbuf * push,const uint16_t * map,unsigned start,unsigned count)633 nvc0_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
634 unsigned start, unsigned count)
635 {
636 map += start;
637
638 if (count & 1) {
639 count &= ~1;
640 PUSH_SPACE(push, 2);
641 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
642 PUSH_DATA (push, *map++);
643 }
644 while (count) {
645 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
646
647 PUSH_SPACE(push, nr + 1);
648 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
649 for (i = 0; i < nr; ++i) {
650 PUSH_DATA(push, (map[1] << 16) | map[0]);
651 map += 2;
652 }
653 count -= nr * 2;
654 }
655 }
656
657 static void
nvc0_draw_elements_inline_u32(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)658 nvc0_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
659 unsigned start, unsigned count)
660 {
661 map += start;
662
663 while (count) {
664 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
665
666 PUSH_SPACE(push, nr + 1);
667 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), nr);
668 PUSH_DATAp(push, map, nr);
669
670 map += nr;
671 count -= nr;
672 }
673 }
674
675 static void
nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)676 nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
677 const uint32_t *map,
678 unsigned start, unsigned count)
679 {
680 map += start;
681
682 if (count & 1) {
683 count--;
684 PUSH_SPACE(push, 2);
685 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
686 PUSH_DATA (push, *map++);
687 }
688 while (count) {
689 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
690
691 PUSH_SPACE(push, nr + 1);
692 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
693 for (i = 0; i < nr; ++i) {
694 PUSH_DATA(push, (map[1] << 16) | map[0]);
695 map += 2;
696 }
697 count -= nr * 2;
698 }
699 }
700
701 static void
nvc0_draw_elements(struct nvc0_context * nvc0,bool shorten,const struct pipe_draw_info * info,unsigned mode,unsigned start,unsigned count,unsigned instance_count,int32_t index_bias,unsigned index_size)702 nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
703 const struct pipe_draw_info *info,
704 unsigned mode, unsigned start, unsigned count,
705 unsigned instance_count, int32_t index_bias,
706 unsigned index_size)
707 {
708 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
709 unsigned prim;
710
711 prim = nvc0_prim_gl(mode);
712
713 if (index_bias != nvc0->state.index_bias) {
714 PUSH_SPACE(push, 4);
715 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
716 PUSH_DATA (push, index_bias);
717 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 1);
718 PUSH_DATA (push, index_bias);
719 nvc0->state.index_bias = index_bias;
720 }
721
722 if (!info->has_user_indices) {
723 PUSH_SPACE(push, 1);
724 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
725 do {
726 PUSH_SPACE(push, 7);
727 BEGIN_NVC0(push, NVC0_3D(INDEX_BATCH_FIRST), 2);
728 PUSH_DATA (push, start);
729 PUSH_DATA (push, count);
730 if (--instance_count) {
731 BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 2);
732 PUSH_DATA (push, 0);
733 PUSH_DATA (push, prim | NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT);
734 }
735 } while (instance_count);
736 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
737 } else {
738 const void *data = info->index.user;
739
740 while (instance_count--) {
741 PUSH_SPACE(push, 2);
742 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
743 PUSH_DATA (push, prim);
744 switch (index_size) {
745 case 1:
746 nvc0_draw_elements_inline_u08(push, data, start, count);
747 break;
748 case 2:
749 nvc0_draw_elements_inline_u16(push, data, start, count);
750 break;
751 case 4:
752 if (shorten)
753 nvc0_draw_elements_inline_u32_short(push, data, start, count);
754 else
755 nvc0_draw_elements_inline_u32(push, data, start, count);
756 break;
757 default:
758 assert(0);
759 return;
760 }
761 PUSH_SPACE(push, 1);
762 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
763
764 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
765 }
766 }
767 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1);
768 }
769
770 static void
nvc0_draw_stream_output(struct nvc0_context * nvc0,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect)771 nvc0_draw_stream_output(struct nvc0_context *nvc0,
772 const struct pipe_draw_info *info,
773 const struct pipe_draw_indirect_info *indirect)
774 {
775 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
776 struct nvc0_so_target *so = nvc0_so_target(indirect->count_from_stream_output);
777 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
778 unsigned mode = nvc0_prim_gl(info->mode);
779 unsigned num_instances = info->instance_count;
780
781 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
782 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
783 PUSH_SPACE(push, 2);
784 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
785 nvc0_hw_query_fifo_wait(nvc0, nvc0_query(so->pq));
786 if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
787 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
788
789 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
790 }
791
792 while (num_instances--) {
793 PUSH_SPACE_EX(push, 16, 0, 1);
794 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
795 PUSH_DATA (push, mode);
796 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
797 PUSH_DATA (push, 0);
798 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_STRIDE), 1);
799 PUSH_DATA (push, so->stride);
800 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BYTES), 1);
801 nvc0_hw_query_pushbuf_submit(push, nvc0_query(so->pq), 0x4);
802 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
803
804 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
805 }
806 }
807
808 static void
nvc0_draw_indirect(struct nvc0_context * nvc0,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect)809 nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info,
810 unsigned drawid_offset,
811 const struct pipe_draw_indirect_info *indirect)
812 {
813 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
814 struct nv04_resource *buf = nv04_resource(indirect->buffer);
815 struct nv04_resource *buf_count = nv04_resource(indirect->indirect_draw_count);
816 unsigned size, macro, count = indirect->draw_count, drawid = drawid_offset;
817 uint32_t offset = buf->offset + indirect->offset;
818 struct nvc0_screen *screen = nvc0->screen;
819
820 PUSH_SPACE(push, 7);
821
822 /* must make FIFO wait for engines idle before continuing to process */
823 if ((buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr)) ||
824 (buf_count && buf_count->fence_wr &&
825 !nouveau_fence_signalled(buf_count->fence_wr))) {
826 IMMED_NVC0(push, SUBC_3D(NV10_SUBCHAN_REF_CNT), 0);
827 }
828
829 /* Queue things up to let the macros write params to the driver constbuf */
830 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
831 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
832 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
833 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
834 BEGIN_NVC0(push, NVC0_3D(CB_POS), 1);
835 PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO);
836
837 if (info->index_size) {
838 assert(!info->has_user_indices);
839 assert(nouveau_resource_mapped_by_gpu(info->index.resource));
840 size = 5;
841 if (buf_count)
842 macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT;
843 else
844 macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT;
845 } else {
846 if (nvc0->state.index_bias) {
847 /* index_bias is implied 0 if !info->index_size (really ?) */
848 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
849 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
850 nvc0->state.index_bias = 0;
851 }
852 size = 4;
853 if (buf_count)
854 macro = NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT;
855 else
856 macro = NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT;
857 }
858
859 /* If the stride is not the natural stride, we have to stick a separate
860 * push data reference for each draw. Otherwise it can all go in as one.
861 * Of course there is a maximum packet size, so we have to break things up
862 * along those borders as well.
863 */
864 while (count) {
865 unsigned draws = count, pushes, i;
866 if (indirect->stride == size * 4) {
867 draws = MIN2(draws, (NV04_PFIFO_MAX_PACKET_LEN - 4) / size);
868 pushes = 1;
869 } else {
870 draws = MIN2(draws, 32);
871 pushes = draws;
872 }
873
874 PUSH_SPACE_EX(push, 16, 0, pushes + !!buf_count);
875 PUSH_REF1(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
876 if (buf_count)
877 PUSH_REF1(push, buf_count->bo, NOUVEAU_BO_RD | buf_count->domain);
878 PUSH_DATA(push,
879 NVC0_FIFO_PKHDR_1I(0, macro, 3 + !!buf_count + draws * size));
880 PUSH_DATA(push, nvc0_prim_gl(info->mode));
881 PUSH_DATA(push, drawid);
882 PUSH_DATA(push, draws);
883 if (buf_count) {
884 nouveau_pushbuf_data(push,
885 buf_count->bo,
886 buf_count->offset + indirect->indirect_draw_count_offset,
887 NVC0_IB_ENTRY_1_NO_PREFETCH | 4);
888 }
889 if (pushes == 1) {
890 nouveau_pushbuf_data(push,
891 buf->bo, offset,
892 NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4 * draws));
893 offset += draws * indirect->stride;
894 } else {
895 for (i = 0; i < pushes; i++) {
896 nouveau_pushbuf_data(push,
897 buf->bo, offset,
898 NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4));
899 offset += indirect->stride;
900 }
901 }
902 count -= draws;
903 drawid += draws;
904 }
905 }
906
907 static inline void
nvc0_update_prim_restart(struct nvc0_context * nvc0,bool en,uint32_t index)908 nvc0_update_prim_restart(struct nvc0_context *nvc0, bool en, uint32_t index)
909 {
910 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
911
912 if (en != nvc0->state.prim_restart) {
913 if (en) {
914 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 2);
915 PUSH_DATA (push, 1);
916 PUSH_DATA (push, index);
917 } else {
918 IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
919 }
920 nvc0->state.prim_restart = en;
921 } else
922 if (en) {
923 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_INDEX), 1);
924 PUSH_DATA (push, index);
925 }
926 }
927
928 static void
nvc0_draw_single_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws)929 nvc0_draw_single_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
930 unsigned drawid_offset,
931 const struct pipe_draw_indirect_info *indirect,
932 const struct pipe_draw_start_count_bias *draws)
933 {
934 struct nvc0_context *nvc0 = nvc0_context(pipe);
935 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
936 struct nvc0_screen *screen = nvc0->screen;
937 int s;
938
939 simple_mtx_assert_locked(&nvc0->screen->state_lock);
940
941 if (nvc0->vertprog->vp.need_draw_parameters && (!indirect || indirect->count_from_stream_output)) {
942 PUSH_SPACE(push, 9);
943 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
944 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
945 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
946 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
947 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 3);
948 PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO);
949 PUSH_DATA (push, info->index_size ? draws->index_bias : 0);
950 PUSH_DATA (push, info->start_instance);
951 PUSH_DATA (push, drawid_offset);
952 }
953
954 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS &&
955 nvc0->seamless_cube_map != nvc0->state.seamless_cube_map) {
956 nvc0->state.seamless_cube_map = nvc0->seamless_cube_map;
957 PUSH_SPACE(push, 1);
958 IMMED_NVC0(push, NVC0_3D(TEX_MISC),
959 nvc0->seamless_cube_map ? NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
960 }
961
962 nvc0->base.kick_notify = nvc0_draw_vbo_kick_notify;
963
964 for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
965 if (nvc0->constbuf_coherent[s])
966 nvc0->cb_dirty = true;
967 }
968
969 if (nvc0->cb_dirty) {
970 PUSH_SPACE(push, 1);
971 IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
972 nvc0->cb_dirty = false;
973 }
974
975 for (s = 0; s < 5; ++s) {
976 if (!nvc0->textures_coherent[s])
977 continue;
978
979 PUSH_SPACE(push, nvc0->num_textures[s] * 2);
980
981 for (int i = 0; i < nvc0->num_textures[s]; ++i) {
982 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
983 if (!(nvc0->textures_coherent[s] & (1 << i)))
984 continue;
985
986 BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
987 PUSH_DATA (push, (tic->id << 4) | 1);
988 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
989 }
990 }
991
992 if (nvc0->state.vbo_mode) {
993 if (indirect && indirect->buffer)
994 nvc0_push_vbo_indirect(nvc0, info, drawid_offset, indirect, &draws[0]);
995 else
996 nvc0_push_vbo(nvc0, info, indirect, &draws[0]);
997 return;
998 }
999
1000 /* space for base instance, flush, and prim restart */
1001 PUSH_SPACE(push, 8);
1002
1003 if (nvc0->state.instance_base != info->start_instance) {
1004 nvc0->state.instance_base = info->start_instance;
1005 /* NOTE: this does not affect the shader input, should it ? */
1006 BEGIN_NVC0(push, NVC0_3D(VB_INSTANCE_BASE), 1);
1007 PUSH_DATA (push, info->start_instance);
1008 }
1009
1010 nvc0->base.vbo_dirty |= !!nvc0->vtxbufs_coherent;
1011
1012 if (!nvc0->base.vbo_dirty && info->index_size && !info->has_user_indices &&
1013 info->index.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1014 nvc0->base.vbo_dirty = true;
1015
1016 nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index);
1017
1018 if (nvc0->base.vbo_dirty) {
1019 if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1020 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
1021 nvc0->base.vbo_dirty = false;
1022 }
1023
1024 if (unlikely(indirect && indirect->buffer)) {
1025 nvc0_draw_indirect(nvc0, info, drawid_offset, indirect);
1026 } else
1027 if (unlikely(indirect && indirect->count_from_stream_output)) {
1028 nvc0_draw_stream_output(nvc0, info, indirect);
1029 } else
1030 if (info->index_size) {
1031 bool shorten = info->index_bounds_valid && info->max_index <= 65535;
1032
1033 if (info->primitive_restart && info->restart_index > 65535)
1034 shorten = false;
1035
1036 nvc0_draw_elements(nvc0, shorten, info,
1037 info->mode, draws[0].start, draws[0].count,
1038 info->instance_count, draws->index_bias, info->index_size);
1039 } else {
1040 nvc0_draw_arrays(nvc0,
1041 info->mode, draws[0].start, draws[0].count,
1042 info->instance_count);
1043 }
1044 }
1045
1046 /* Thin wrapper to avoid kicking every 3 ns during multidraw */
1047
1048 void
nvc0_draw_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)1049 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
1050 unsigned drawid_offset,
1051 const struct pipe_draw_indirect_info *indirect,
1052 const struct pipe_draw_start_count_bias *draws,
1053 unsigned num_draws)
1054 {
1055 struct nvc0_context *nvc0 = nvc0_context(pipe);
1056 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1057
1058 struct nvc0_screen *screen = nvc0->screen;
1059 unsigned vram_domain = NV_VRAM_DOMAIN(&screen->base);
1060 unsigned count_total = 0;
1061
1062 /* The rest is copied straight from util_multi_draw
1063 *
1064 * XXX: Properly rewrite vbo handling in nvc0/nv50
1065 *
1066 */
1067
1068 unsigned drawid = drawid_offset;
1069
1070 /* dont wanna start trippin */
1071 simple_mtx_lock(&nvc0->screen->state_lock);
1072
1073 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
1074 if (info->index_bounds_valid) {
1075 nvc0->vb_elt_first = info->min_index + (info->index_size ? draws->index_bias : 0);
1076 nvc0->vb_elt_limit = info->max_index - info->min_index;
1077 } else {
1078 nvc0->vb_elt_first = 0;
1079 nvc0->vb_elt_limit = ~0;
1080 }
1081 nvc0->instance_off = info->start_instance;
1082 nvc0->instance_max = info->instance_count - 1;
1083
1084 /* Get total amount of draw counts to determine whether to push or upload vertices */
1085 for (unsigned i = 0; i < num_draws; i++) {
1086 count_total += draws[i].count;
1087 }
1088
1089 /* For picking only a few vertices from a large user buffer, push is better,
1090 * if index count is larger and we expect repeated vertices, suggest upload.
1091 */
1092 nvc0->vbo_push_hint =
1093 (!indirect || indirect->count_from_stream_output) && info->index_size &&
1094 (nvc0->vb_elt_limit >= (count_total * 2));
1095
1096 if (nvc0->dirty_3d & (NVC0_NEW_3D_ARRAYS | NVC0_NEW_3D_VERTEX))
1097 nvc0->constant_vbos = nvc0->vertex->constant_vbos & nvc0->vbo_user;
1098 /* Check whether we want to switch vertex-submission mode. */
1099 if (nvc0->vbo_user && !(nvc0->dirty_3d & (NVC0_NEW_3D_ARRAYS | NVC0_NEW_3D_VERTEX))) {
1100 if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode)
1101 if (nvc0->state.vbo_mode != 3)
1102 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1103
1104 if (!(nvc0->dirty_3d & NVC0_NEW_3D_ARRAYS) && nvc0->state.vbo_mode == 0) {
1105 if (nvc0->vertex->shared_slots)
1106 nvc0_update_user_vbufs_shared(nvc0);
1107 else
1108 nvc0_update_user_vbufs(nvc0);
1109 }
1110 }
1111
1112 if (info->mode == MESA_PRIM_PATCHES &&
1113 nvc0->state.patch_vertices != nvc0->patch_vertices) {
1114 nvc0->state.patch_vertices = nvc0->patch_vertices;
1115 PUSH_SPACE(push, 1);
1116 IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
1117 }
1118
1119 if (info->index_size && !info->has_user_indices) {
1120 struct nv04_resource *buf = nv04_resource(info->index.resource);
1121
1122 assert(buf);
1123 assert(nouveau_resource_mapped_by_gpu(&buf->base));
1124
1125 PUSH_SPACE(push, 6);
1126 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS) {
1127 BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
1128 PUSH_DATAh(push, buf->address);
1129 PUSH_DATA (push, buf->address);
1130 PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
1131 PUSH_DATA (push, buf->address + buf->base.width0 - 1);
1132 PUSH_DATA (push, info->index_size >> 1);
1133 } else {
1134 BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 2);
1135 PUSH_DATAh(push, buf->address);
1136 PUSH_DATA (push, buf->address);
1137 BEGIN_NVC0(push, SUBC_3D(TU102_3D_INDEX_ARRAY_LIMIT_HIGH), 2);
1138 PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
1139 PUSH_DATA (push, buf->address + buf->base.width0 - 1);
1140 BEGIN_NVC0(push, NVC0_3D(INDEX_FORMAT), 1);
1141 PUSH_DATA (push, info->index_size >> 1);
1142 }
1143
1144 BCTX_REFN(nvc0->bufctx_3d, 3D_IDX, buf, RD);
1145 }
1146
1147 list_for_each_entry(struct nvc0_resident, resident, &nvc0->tex_head, list) {
1148 nvc0_add_resident(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS, resident->buf,
1149 resident->flags);
1150 }
1151
1152 list_for_each_entry(struct nvc0_resident, resident, &nvc0->img_head, list) {
1153 nvc0_add_resident(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS, resident->buf,
1154 resident->flags);
1155 }
1156
1157 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT, vram_domain | NOUVEAU_BO_RD,
1158 screen->text);
1159
1160 nvc0_state_validate_3d(nvc0, ~0);
1161
1162 for (unsigned i = 0; i < num_draws; i++) {
1163 if (indirect || (draws[i].count && info->instance_count))
1164 nvc0_draw_single_vbo(pipe, info, drawid, indirect, &draws[i]);
1165 if (info->increment_draw_id)
1166 drawid++;
1167 }
1168
1169 PUSH_KICK(push);
1170 simple_mtx_unlock(&nvc0->screen->state_lock);
1171
1172 nvc0->base.kick_notify = nvc0_default_kick_notify;
1173
1174 nvc0_release_user_vbufs(nvc0);
1175
1176 nouveau_pushbuf_bufctx(push, NULL);
1177
1178 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
1179 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
1180 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS);
1181 }
1182