1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_draw.h"
26 #include "util/u_inlines.h"
27 #include "util/u_prim.h"
28 #include "util/format/u_format.h"
29 #include "translate/translate.h"
30
31 #include "nv50/nv50_context.h"
32 #include "nv50/nv50_query_hw.h"
33 #include "nv50/nv50_resource.h"
34
35 #include "nv50/nv50_3d.xml.h"
36
37 void
nv50_vertex_state_delete(struct pipe_context * pipe,void * hwcso)38 nv50_vertex_state_delete(struct pipe_context *pipe,
39 void *hwcso)
40 {
41 struct nv50_vertex_stateobj *so = hwcso;
42
43 if (so->translate)
44 so->translate->release(so->translate);
45 FREE(hwcso);
46 }
47
48 void *
nv50_vertex_state_create(struct pipe_context * pipe,unsigned num_elements,const struct pipe_vertex_element * elements)49 nv50_vertex_state_create(struct pipe_context *pipe,
50 unsigned num_elements,
51 const struct pipe_vertex_element *elements)
52 {
53 struct nv50_vertex_stateobj *so;
54 struct translate_key transkey;
55 unsigned i;
56
57 so = CALLOC(1, sizeof(*so) +
58 num_elements * sizeof(struct nv50_vertex_element));
59 if (!so)
60 return NULL;
61 so->num_elements = num_elements;
62 so->instance_elts = 0;
63 so->instance_bufs = 0;
64 so->need_conversion = false;
65
66 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
67
68 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
69 so->min_instance_div[i] = 0xffffffff;
70
71 transkey.nr_elements = 0;
72 transkey.output_stride = 0;
73
74 for (i = 0; i < num_elements; ++i) {
75 const struct pipe_vertex_element *ve = &elements[i];
76 const unsigned vbi = ve->vertex_buffer_index;
77 unsigned size;
78 enum pipe_format fmt = ve->src_format;
79
80 so->element[i].pipe = elements[i];
81 so->element[i].state = nv50_vertex_format[fmt].vtx;
82
83 if (!so->element[i].state) {
84 switch (util_format_get_nr_components(fmt)) {
85 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
86 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
87 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
88 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
89 default:
90 assert(0);
91 FREE(so);
92 return NULL;
93 }
94 so->element[i].state = nv50_vertex_format[fmt].vtx;
95 so->need_conversion = true;
96 util_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
97 "Converting vertex element %d, no hw format %s",
98 i, util_format_name(ve->src_format));
99 }
100 so->element[i].state |= i;
101 so->strides[vbi] = ve->src_stride;
102 if (!ve->src_stride)
103 so->vbo_constant |= 1 << vbi;
104
105 size = util_format_get_blocksize(fmt);
106 if (so->vb_access_size[vbi] < (ve->src_offset + size))
107 so->vb_access_size[vbi] = ve->src_offset + size;
108
109 if (1) {
110 unsigned j = transkey.nr_elements++;
111
112 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
113 transkey.element[j].input_format = ve->src_format;
114 transkey.element[j].input_buffer = vbi;
115 transkey.element[j].input_offset = ve->src_offset;
116 transkey.element[j].instance_divisor = ve->instance_divisor;
117
118 transkey.element[j].output_format = fmt;
119 transkey.element[j].output_offset = transkey.output_stride;
120 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
121
122 if (unlikely(ve->instance_divisor)) {
123 so->instance_elts |= 1 << i;
124 so->instance_bufs |= 1 << vbi;
125 if (ve->instance_divisor < so->min_instance_div[vbi])
126 so->min_instance_div[vbi] = ve->instance_divisor;
127 }
128 }
129 }
130
131 so->translate = translate_create(&transkey);
132 so->vertex_size = transkey.output_stride / 4;
133 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
134 MAX2(so->vertex_size, 1);
135
136 return so;
137 }
138
139 #define NV50_3D_VERTEX_ATTRIB_INACTIVE \
140 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \
141 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
142 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
143
144 static void
nv50_emit_vtxattr(struct nv50_context * nv50,struct pipe_vertex_buffer * vb,struct pipe_vertex_element * ve,unsigned attr)145 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
146 struct pipe_vertex_element *ve, unsigned attr)
147 {
148 struct nouveau_pushbuf *push = nv50->base.pushbuf;
149 const void *data = (const uint8_t *)vb->buffer.user + ve->src_offset;
150 float v[4];
151 const unsigned nc = util_format_get_nr_components(ve->src_format);
152
153 assert(vb->is_user_buffer);
154
155 util_format_unpack_rgba(ve->src_format, v, data, 1);
156
157 switch (nc) {
158 case 4:
159 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
160 PUSH_DATAf(push, v[0]);
161 PUSH_DATAf(push, v[1]);
162 PUSH_DATAf(push, v[2]);
163 PUSH_DATAf(push, v[3]);
164 break;
165 case 3:
166 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
167 PUSH_DATAf(push, v[0]);
168 PUSH_DATAf(push, v[1]);
169 PUSH_DATAf(push, v[2]);
170 break;
171 case 2:
172 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
173 PUSH_DATAf(push, v[0]);
174 PUSH_DATAf(push, v[1]);
175 break;
176 case 1:
177 if (attr == nv50->vertprog->vp.edgeflag) {
178 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
179 PUSH_DATA (push, v[0] ? 1 : 0);
180 }
181 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
182 PUSH_DATAf(push, v[0]);
183 break;
184 default:
185 assert(0);
186 break;
187 }
188 }
189
190 static inline void
nv50_user_vbuf_range(struct nv50_context * nv50,unsigned vbi,uint32_t * base,uint32_t * size)191 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
192 uint32_t *base, uint32_t *size)
193 {
194 assert(vbi < PIPE_MAX_ATTRIBS);
195 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
196 const uint32_t div = nv50->vertex->min_instance_div[vbi];
197 *base = nv50->instance_off * nv50->vertex->strides[vbi];
198 *size = (nv50->instance_max / div) * nv50->vertex->strides[vbi] +
199 nv50->vertex->vb_access_size[vbi];
200 } else {
201 /* NOTE: if there are user buffers, we *must* have index bounds */
202 assert(nv50->vb_elt_limit != ~0);
203 *base = nv50->vb_elt_first * nv50->vertex->strides[vbi];
204 *size = nv50->vb_elt_limit * nv50->vertex->strides[vbi] +
205 nv50->vertex->vb_access_size[vbi];
206 }
207 }
208
209 static void
nv50_upload_user_buffers(struct nv50_context * nv50,uint64_t addrs[],uint32_t limits[])210 nv50_upload_user_buffers(struct nv50_context *nv50,
211 uint64_t addrs[], uint32_t limits[])
212 {
213 unsigned b;
214
215 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
216 for (b = 0; b < nv50->num_vtxbufs; ++b) {
217 struct nouveau_bo *bo;
218 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
219 uint32_t base, size;
220
221 if (!(nv50->vbo_user & (1 << b)) || !nv50->vertex->strides[b])
222 continue;
223 nv50_user_vbuf_range(nv50, b, &base, &size);
224
225 limits[b] = base + size - 1;
226 addrs[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, base, size,
227 &bo);
228 if (addrs[b])
229 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, NOUVEAU_BO_GART |
230 NOUVEAU_BO_RD, bo);
231 }
232 nv50->base.vbo_dirty = true;
233 }
234
235 static void
nv50_update_user_vbufs(struct nv50_context * nv50)236 nv50_update_user_vbufs(struct nv50_context *nv50)
237 {
238 uint64_t address[PIPE_MAX_ATTRIBS];
239 struct nouveau_pushbuf *push = nv50->base.pushbuf;
240 unsigned i;
241 uint32_t written = 0;
242
243 for (i = 0; i < nv50->vertex->num_elements; ++i) {
244 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
245 const unsigned b = ve->vertex_buffer_index;
246 struct pipe_vertex_buffer *vb;
247 uint32_t base, size;
248
249 assert(b < PIPE_MAX_ATTRIBS);
250 vb = &nv50->vtxbuf[b];
251
252 if (!(nv50->vbo_user & (1 << b)))
253 continue;
254
255 if (!ve->src_stride) {
256 nv50_emit_vtxattr(nv50, vb, ve, i);
257 continue;
258 }
259 nv50_user_vbuf_range(nv50, b, &base, &size);
260
261 if (!(written & (1 << b))) {
262 struct nouveau_bo *bo;
263 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
264 written |= 1 << b;
265 address[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user,
266 base, size, &bo);
267 if (address[b])
268 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo);
269 }
270
271 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
272 PUSH_DATAh(push, address[b] + base + size - 1);
273 PUSH_DATA (push, address[b] + base + size - 1);
274 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
275 PUSH_DATAh(push, address[b] + ve->src_offset);
276 PUSH_DATA (push, address[b] + ve->src_offset);
277 }
278 nv50->base.vbo_dirty = true;
279 }
280
281 static inline void
nv50_release_user_vbufs(struct nv50_context * nv50)282 nv50_release_user_vbufs(struct nv50_context *nv50)
283 {
284 if (nv50->vbo_user) {
285 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX_TMP);
286 nouveau_scratch_done(&nv50->base);
287 }
288 }
289
290 void
nv50_vertex_arrays_validate(struct nv50_context * nv50)291 nv50_vertex_arrays_validate(struct nv50_context *nv50)
292 {
293 uint64_t addrs[PIPE_MAX_ATTRIBS];
294 uint32_t limits[PIPE_MAX_ATTRIBS];
295 struct nouveau_pushbuf *push = nv50->base.pushbuf;
296 struct nv50_vertex_stateobj *vertex = nv50->vertex;
297 struct nv50_vertex_element *ve;
298 uint32_t mask;
299 uint32_t refd = 0;
300 unsigned i;
301 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
302
303 if (unlikely(vertex->need_conversion))
304 nv50->vbo_fifo = ~0;
305 else
306 if (nv50->vbo_user & ~nv50->vbo_constant)
307 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
308 else
309 nv50->vbo_fifo = 0;
310
311 if (!nv50->vbo_fifo) {
312 /* if vertex buffer was written by GPU - flush VBO cache */
313 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
314 for (i = 0; i < nv50->num_vtxbufs; ++i) {
315 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer.resource);
316 if (!nv50->vtxbuf[i].is_user_buffer &&
317 buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
318 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
319 nv50->base.vbo_dirty = true;
320 }
321 }
322 }
323
324 /* update vertex format state */
325 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
326 if (nv50->vbo_fifo) {
327 nv50->state.num_vtxelts = vertex->num_elements;
328 for (i = 0; i < vertex->num_elements; ++i)
329 PUSH_DATA (push, vertex->element[i].state);
330 for (; i < n; ++i)
331 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
332 for (i = 0; i < n; ++i) {
333 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
334 PUSH_DATA (push, 0);
335 }
336 return;
337 }
338 for (i = 0; i < vertex->num_elements; ++i) {
339 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
340
341 assert(b < PIPE_MAX_ATTRIBS);
342 ve = &vertex->element[i];
343
344 if (likely(vertex->strides[b]) || !(nv50->vbo_user & (1 << b)))
345 PUSH_DATA(push, ve->state);
346 else
347 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
348 }
349 for (; i < n; ++i)
350 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
351
352 /* update per-instance enables */
353 mask = vertex->instance_elts ^ nv50->state.instance_elts;
354 while (mask) {
355 const int i = ffs(mask) - 1;
356 mask &= ~(1 << i);
357 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
358 PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
359 }
360 nv50->state.instance_elts = vertex->instance_elts;
361
362 if (nv50->vbo_user & ~nv50->vbo_constant)
363 nv50_upload_user_buffers(nv50, addrs, limits);
364
365 /* update buffers and set constant attributes */
366 for (i = 0; i < vertex->num_elements; ++i) {
367 uint64_t address, limit;
368 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
369 struct pipe_vertex_buffer *vb;
370
371 assert(b < PIPE_MAX_ATTRIBS);
372 ve = &vertex->element[i];
373 vb = &nv50->vtxbuf[b];
374
375 if (unlikely(nv50->vbo_constant & (1 << b))) {
376 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
377 PUSH_DATA (push, 0);
378 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
379 continue;
380 } else
381 if (nv50->vbo_user & (1 << b)) {
382 address = addrs[b] + ve->pipe.src_offset;
383 limit = addrs[b] + limits[b];
384 } else
385 if (!vb->buffer.resource) {
386 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
387 PUSH_DATA (push, 0);
388 continue;
389 } else {
390 struct nv04_resource *buf = nv04_resource(vb->buffer.resource);
391 if (!(refd & (1 << b))) {
392 refd |= 1 << b;
393 BCTX_REFN(nv50->bufctx_3d, 3D_VERTEX, buf, RD);
394 }
395 address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
396 limit = buf->address + buf->base.width0 - 1;
397 }
398
399 if (unlikely(ve->pipe.instance_divisor)) {
400 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
401 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vertex->strides[b]);
402 PUSH_DATAh(push, address);
403 PUSH_DATA (push, address);
404 PUSH_DATA (push, ve->pipe.instance_divisor);
405 } else {
406 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
407 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vertex->strides[b]);
408 PUSH_DATAh(push, address);
409 PUSH_DATA (push, address);
410 }
411 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
412 PUSH_DATAh(push, limit);
413 PUSH_DATA (push, limit);
414 }
415 for (; i < nv50->state.num_vtxelts; ++i) {
416 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
417 PUSH_DATA (push, 0);
418 }
419 nv50->state.num_vtxelts = vertex->num_elements;
420 }
421
422 #define NV50_PRIM_GL_CASE(n) \
423 case MESA_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
424
425 static inline unsigned
nv50_prim_gl(unsigned prim)426 nv50_prim_gl(unsigned prim)
427 {
428 switch (prim) {
429 NV50_PRIM_GL_CASE(POINTS);
430 NV50_PRIM_GL_CASE(LINES);
431 NV50_PRIM_GL_CASE(LINE_LOOP);
432 NV50_PRIM_GL_CASE(LINE_STRIP);
433 NV50_PRIM_GL_CASE(TRIANGLES);
434 NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
435 NV50_PRIM_GL_CASE(TRIANGLE_FAN);
436 NV50_PRIM_GL_CASE(QUADS);
437 NV50_PRIM_GL_CASE(QUAD_STRIP);
438 NV50_PRIM_GL_CASE(POLYGON);
439 NV50_PRIM_GL_CASE(LINES_ADJACENCY);
440 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
441 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
442 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
443 default:
444 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
445 break;
446 }
447 }
448
449 /* For pre-nva0 transform feedback. */
450 static const uint8_t nv50_pipe_prim_to_prim_size[MESA_PRIM_COUNT + 1] =
451 {
452 [MESA_PRIM_POINTS] = 1,
453 [MESA_PRIM_LINES] = 2,
454 [MESA_PRIM_LINE_LOOP] = 2,
455 [MESA_PRIM_LINE_STRIP] = 2,
456 [MESA_PRIM_TRIANGLES] = 3,
457 [MESA_PRIM_TRIANGLE_STRIP] = 3,
458 [MESA_PRIM_TRIANGLE_FAN] = 3,
459 [MESA_PRIM_QUADS] = 3,
460 [MESA_PRIM_QUAD_STRIP] = 3,
461 [MESA_PRIM_POLYGON] = 3,
462 [MESA_PRIM_LINES_ADJACENCY] = 2,
463 [MESA_PRIM_LINE_STRIP_ADJACENCY] = 2,
464 [MESA_PRIM_TRIANGLES_ADJACENCY] = 3,
465 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
466 };
467
468 static void
nv50_draw_arrays(struct nv50_context * nv50,unsigned mode,unsigned start,unsigned count,unsigned instance_count)469 nv50_draw_arrays(struct nv50_context *nv50,
470 unsigned mode, unsigned start, unsigned count,
471 unsigned instance_count)
472 {
473 struct nouveau_pushbuf *push = nv50->base.pushbuf;
474 unsigned prim;
475
476 if (nv50->state.index_bias) {
477 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
478 PUSH_DATA (push, 0);
479 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
480 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
481 PUSH_DATA (push, 0);
482 }
483 nv50->state.index_bias = 0;
484 }
485
486 prim = nv50_prim_gl(mode);
487
488 while (instance_count--) {
489 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
490 PUSH_DATA (push, prim);
491 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
492 PUSH_DATA (push, start);
493 PUSH_DATA (push, count);
494 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
495 PUSH_DATA (push, 0);
496
497 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
498 }
499 }
500
501 static void
nv50_draw_elements_inline_u08(struct nouveau_pushbuf * push,const uint8_t * map,unsigned start,unsigned count)502 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
503 unsigned start, unsigned count)
504 {
505 map += start;
506
507 if (count & 3) {
508 unsigned i;
509 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
510 for (i = 0; i < (count & 3); ++i)
511 PUSH_DATA(push, *map++);
512 count &= ~3;
513 }
514 while (count) {
515 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
516
517 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
518 for (i = 0; i < nr; ++i) {
519 PUSH_DATA(push,
520 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
521 map += 4;
522 }
523 count -= nr * 4;
524 }
525 }
526
527 static void
nv50_draw_elements_inline_u16(struct nouveau_pushbuf * push,const uint16_t * map,unsigned start,unsigned count)528 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
529 unsigned start, unsigned count)
530 {
531 map += start;
532
533 if (count & 1) {
534 count &= ~1;
535 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
536 PUSH_DATA (push, *map++);
537 }
538 while (count) {
539 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
540
541 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
542 for (i = 0; i < nr; ++i) {
543 PUSH_DATA(push, (map[1] << 16) | map[0]);
544 map += 2;
545 }
546 count -= nr * 2;
547 }
548 }
549
550 static void
nv50_draw_elements_inline_u32(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)551 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
552 unsigned start, unsigned count)
553 {
554 map += start;
555
556 while (count) {
557 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
558
559 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
560 PUSH_DATAp(push, map, nr);
561
562 map += nr;
563 count -= nr;
564 }
565 }
566
567 static void
nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)568 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
569 const uint32_t *map,
570 unsigned start, unsigned count)
571 {
572 map += start;
573
574 if (count & 1) {
575 count--;
576 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
577 PUSH_DATA (push, *map++);
578 }
579 while (count) {
580 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
581
582 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
583 for (i = 0; i < nr; ++i) {
584 PUSH_DATA(push, (map[1] << 16) | map[0]);
585 map += 2;
586 }
587 count -= nr * 2;
588 }
589 }
590
591 static void
nv50_draw_elements(struct nv50_context * nv50,bool shorten,const struct pipe_draw_info * info,unsigned mode,unsigned start,unsigned count,unsigned instance_count,int32_t index_bias,unsigned index_size)592 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
593 const struct pipe_draw_info *info,
594 unsigned mode, unsigned start, unsigned count,
595 unsigned instance_count, int32_t index_bias,
596 unsigned index_size)
597 {
598 struct nouveau_pushbuf *push = nv50->base.pushbuf;
599 unsigned prim;
600
601 prim = nv50_prim_gl(mode);
602
603 if (index_bias != nv50->state.index_bias) {
604 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
605 PUSH_DATA (push, index_bias);
606 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
607 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
608 PUSH_DATA (push, index_bias);
609 }
610 nv50->state.index_bias = index_bias;
611 }
612
613 if (!info->has_user_indices) {
614 struct nv04_resource *buf = nv04_resource(info->index.resource);
615 unsigned pb_start;
616 unsigned pb_bytes;
617 const unsigned base = buf->offset & ~3;
618
619 start += (buf->offset & 3) >> (index_size >> 1);
620
621 assert(nouveau_resource_mapped_by_gpu(info->index.resource));
622
623 /* This shouldn't have to be here. The going theory is that the buffer
624 * is being filled in by PGRAPH, and it's not done yet by the time it
625 * gets submitted to PFIFO, which in turn starts immediately prefetching
626 * the not-yet-written data. Ideally this wait would only happen on
627 * pushbuf submit, but it's probably not a big performance difference.
628 */
629 if (buf->fence_wr)
630 nouveau_fence_wait(buf->fence_wr, &nv50->base.debug);
631
632 while (instance_count--) {
633 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
634 PUSH_DATA (push, prim);
635
636 PUSH_SPACE_EX(push, 16, 0, 1);
637 PUSH_REF1(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
638
639 switch (index_size) {
640 case 4:
641 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
642 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
643 break;
644 case 2:
645 pb_start = (start & ~1) * 2;
646 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
647
648 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
649 PUSH_DATA (push, (start << 31) | count);
650 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
651 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
652 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
653 PUSH_DATA (push, 0);
654 break;
655 default:
656 assert(index_size == 1);
657 pb_start = start & ~3;
658 pb_bytes = ((start + count + 3) & ~3) - pb_start;
659
660 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
661 PUSH_DATA (push, (start << 30) | count);
662 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
663 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
664 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
665 PUSH_DATA (push, 0);
666 break;
667 }
668 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
669 PUSH_DATA (push, 0);
670
671 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
672 }
673 } else {
674 const void *data = info->index.user;
675
676 while (instance_count--) {
677 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
678 PUSH_DATA (push, prim);
679 switch (index_size) {
680 case 1:
681 nv50_draw_elements_inline_u08(push, data, start, count);
682 break;
683 case 2:
684 nv50_draw_elements_inline_u16(push, data, start, count);
685 break;
686 case 4:
687 if (shorten)
688 nv50_draw_elements_inline_u32_short(push, data, start, count);
689 else
690 nv50_draw_elements_inline_u32(push, data, start, count);
691 break;
692 default:
693 assert(0);
694 return;
695 }
696 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
697 PUSH_DATA (push, 0);
698
699 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
700 }
701 }
702 NOUVEAU_DRV_STAT(&nv50->screen->base, draw_calls_indexed, 1);
703 }
704
705 static void
nva0_draw_stream_output(struct nv50_context * nv50,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect)706 nva0_draw_stream_output(struct nv50_context *nv50,
707 const struct pipe_draw_info *info,
708 const struct pipe_draw_indirect_info *indirect)
709 {
710 struct nouveau_pushbuf *push = nv50->base.pushbuf;
711 struct nv50_so_target *so = nv50_so_target(indirect->count_from_stream_output);
712 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
713 unsigned num_instances = info->instance_count;
714 unsigned mode = nv50_prim_gl(info->mode);
715
716 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
717 /* A proper implementation without waiting doesn't seem possible,
718 * so don't bother.
719 */
720 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
721 return;
722 }
723
724 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
725 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
726 PUSH_SPACE(push, 4);
727 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
728 PUSH_DATA (push, 0);
729 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
730 PUSH_DATA (push, 0);
731 }
732
733 assert(num_instances);
734 do {
735 PUSH_SPACE(push, 8);
736 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
737 PUSH_DATA (push, mode);
738 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
739 PUSH_DATA (push, 0);
740 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
741 PUSH_DATA (push, so->stride);
742 nv50_hw_query_pushbuf_submit(nv50, NVA0_3D_DRAW_TFB_BYTES,
743 nv50_query(so->pq), 0x4);
744 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
745 PUSH_DATA (push, 0);
746
747 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
748 } while (--num_instances);
749 }
750
751 static void
nv50_draw_vbo_kick_notify(struct nouveau_context * context)752 nv50_draw_vbo_kick_notify(struct nouveau_context *context)
753 {
754 _nouveau_fence_update(context->screen, true);
755 }
756
757 static void
nv50_draw_single_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws)758 nv50_draw_single_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
759 unsigned drawid_offset,
760 const struct pipe_draw_indirect_info *indirect,
761 const struct pipe_draw_start_count_bias *draws)
762 {
763 /* We don't actually support indirect draws, so add a fallback for ES 3.1's
764 * benefit.
765 */
766 if (indirect && indirect->buffer) {
767 util_draw_indirect(pipe, info, drawid_offset, indirect);
768 return;
769 }
770
771 struct nv50_context *nv50 = nv50_context(pipe);
772 struct nouveau_pushbuf *push = nv50->base.pushbuf;
773 bool tex_dirty = false;
774 int s;
775
776 simple_mtx_assert_locked(&nv50->screen->state_lock);
777
778 nv50->base.kick_notify = nv50_draw_vbo_kick_notify;
779
780 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES && !nv50->cb_dirty; ++s) {
781 if (nv50->constbuf_coherent[s])
782 nv50->cb_dirty = true;
783 }
784
785 /* If there are any coherent constbufs, flush the cache */
786 if (nv50->cb_dirty) {
787 BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
788 PUSH_DATA (push, 0);
789 nv50->cb_dirty = false;
790 }
791
792 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES && !tex_dirty; ++s) {
793 if (nv50->textures_coherent[s])
794 tex_dirty = true;
795 }
796
797 if (tex_dirty) {
798 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
799 PUSH_DATA (push, 0x20);
800 }
801
802 if (nv50->screen->base.class_3d >= NVA0_3D_CLASS &&
803 nv50->seamless_cube_map != nv50->state.seamless_cube_map) {
804 nv50->state.seamless_cube_map = nv50->seamless_cube_map;
805 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
806 PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
807 }
808
809 if (nv50->vertprog->mul_zero_wins != nv50->state.mul_zero_wins) {
810 nv50->state.mul_zero_wins = nv50->vertprog->mul_zero_wins;
811 BEGIN_NV04(push, NV50_3D(UNK1690), 1);
812 PUSH_DATA (push, 0x00010000 * !!nv50->state.mul_zero_wins);
813 }
814
815 /* Make starting/pausing streamout work pre-NVA0 enough for ES3.0. This
816 * means counting vertices in a vertex shader when it has so outputs.
817 */
818 if (nv50->screen->base.class_3d < NVA0_3D_CLASS &&
819 nv50->vertprog->stream_output.num_outputs) {
820 for (int i = 0; i < nv50->num_so_targets; i++) {
821 nv50->so_used[i] += info->instance_count *
822 u_stream_outputs_for_vertices(info->mode, draws[0].count) *
823 nv50->vertprog->stream_output.stride[i] * 4;
824 }
825 }
826
827 if (nv50->vbo_fifo) {
828 nv50_push_vbo(nv50, info, indirect, &draws[0]);
829 return;
830 }
831
832 if (nv50->state.instance_base != info->start_instance) {
833 nv50->state.instance_base = info->start_instance;
834 /* NOTE: this does not affect the shader input, should it ? */
835 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
836 PUSH_DATA (push, info->start_instance);
837 }
838
839 nv50->base.vbo_dirty |= !!nv50->vtxbufs_coherent;
840
841 if (nv50->base.vbo_dirty) {
842 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
843 PUSH_DATA (push, 0);
844 nv50->base.vbo_dirty = false;
845 }
846
847 if (info->index_size) {
848 bool shorten = info->index_bounds_valid && info->max_index <= 65535;
849
850 if (info->primitive_restart != nv50->state.prim_restart) {
851 if (info->primitive_restart) {
852 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
853 PUSH_DATA (push, 1);
854 PUSH_DATA (push, info->restart_index);
855
856 if (info->restart_index > 65535)
857 shorten = false;
858 } else {
859 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
860 PUSH_DATA (push, 0);
861 }
862 nv50->state.prim_restart = info->primitive_restart;
863 } else
864 if (info->primitive_restart) {
865 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
866 PUSH_DATA (push, info->restart_index);
867
868 if (info->restart_index > 65535)
869 shorten = false;
870 }
871
872 nv50_draw_elements(nv50, shorten, info,
873 info->mode, draws[0].start, draws[0].count,
874 info->instance_count, draws->index_bias, info->index_size);
875 } else
876 if (unlikely(indirect && indirect->count_from_stream_output)) {
877 nva0_draw_stream_output(nv50, info, indirect);
878 } else {
879 nv50_draw_arrays(nv50,
880 info->mode, draws[0].start, draws[0].count,
881 info->instance_count);
882 }
883 }
884
885 /* Thin wrapper to avoid kicking every 3 ns during multidraw */
886
887 void
nv50_draw_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)888 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
889 unsigned drawid_offset,
890 const struct pipe_draw_indirect_info *indirect,
891 const struct pipe_draw_start_count_bias *draws,
892 unsigned num_draws)
893 {
894 struct nv50_context *nv50 = nv50_context(pipe);
895 struct nouveau_pushbuf *push = nv50->base.pushbuf;
896
897 /* The rest is copied straight from util_multi_draw
898 *
899 * XXX: Properly rewrite vbo handling in nvc0/nv50
900 *
901 */
902
903 unsigned drawid = drawid_offset;
904
905 /* dont wanna start trippin */
906 simple_mtx_lock(&nv50->screen->state_lock);
907
908 if (info->index_size && !info->has_user_indices)
909 BCTX_REFN(nv50->bufctx_3d, 3D_INDEX, nv04_resource(info->index.resource), RD);
910
911 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
912 if (info->index_bounds_valid) {
913 nv50->vb_elt_first = info->min_index + (info->index_size ? draws->index_bias : 0);
914 nv50->vb_elt_limit = info->max_index - info->min_index;
915 } else {
916 nv50->vb_elt_first = 0;
917 nv50->vb_elt_limit = ~0;
918 }
919 nv50->instance_off = info->start_instance;
920 nv50->instance_max = info->instance_count - 1;
921
922 /* For picking only a few vertices from a large user buffer, push is better,
923 * if index count is larger and we expect repeated vertices, suggest upload.
924 */
925 nv50->vbo_push_hint = /* the 64 is heuristic */
926 !(info->index_size && ((nv50->vb_elt_limit + 64) < draws[0].count));
927
928 if (nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))
929 nv50->vbo_constant = nv50->vertex->vbo_constant & nv50->vbo_user;
930 if (nv50->vbo_user && !(nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))) {
931 if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
932 nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
933 else
934 if (!nv50->vbo_fifo)
935 nv50_update_user_vbufs(nv50);
936 }
937
938 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
939 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
940
941 nv50_state_validate_3d(nv50, ~0);
942
943 for (unsigned i = 0; i < num_draws; i++) {
944 if (indirect || (draws[i].count && info->instance_count))
945 nv50_draw_single_vbo(pipe, info, drawid, indirect, &draws[i]);
946 if (info->increment_draw_id)
947 drawid++;
948 }
949
950 PUSH_KICK(push);
951 simple_mtx_unlock(&nv50->screen->state_lock);
952
953 nv50->base.kick_notify = nv50_default_kick_notify;
954
955 nv50_release_user_vbufs(nv50);
956
957 nouveau_pushbuf_bufctx(push, NULL);
958
959 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_INDEX);
960 }
961