1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include "drm-uapi/nouveau_drm.h"
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30
31 #include "nv50_ir_driver.h"
32
33 #include "nv50/nv50_context.h"
34 #include "nv50/nv50_screen.h"
35
36 #include "nouveau_vp3_video.h"
37
38 #include "nv_object.xml.h"
39
40 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
41 #define LOCAL_WARPS_ALLOC 32
42 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
43 #define STACK_WARPS_ALLOC 32
44
45 #define THREADS_IN_WARP 32
46
47 static bool
nv50_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)48 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
49 enum pipe_format format,
50 enum pipe_texture_target target,
51 unsigned sample_count,
52 unsigned storage_sample_count,
53 unsigned bindings)
54 {
55 if (sample_count > 8)
56 return false;
57 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
58 return false;
59 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
60 return false;
61
62 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
63 return false;
64
65 /* Short-circuit the rest of the logic -- this is used by the gallium frontend
66 * to determine valid MS levels in a no-attachments scenario.
67 */
68 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
69 return true;
70
71 switch (format) {
72 case PIPE_FORMAT_Z16_UNORM:
73 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
74 return false;
75 break;
76 default:
77 break;
78 }
79
80 if (bindings & PIPE_BIND_LINEAR)
81 if (util_format_is_depth_or_stencil(format) ||
82 (target != PIPE_TEXTURE_1D &&
83 target != PIPE_TEXTURE_2D &&
84 target != PIPE_TEXTURE_RECT) ||
85 sample_count > 1)
86 return false;
87
88 /* shared is always supported */
89 bindings &= ~(PIPE_BIND_LINEAR |
90 PIPE_BIND_SHARED);
91
92 if (bindings & PIPE_BIND_INDEX_BUFFER) {
93 if (format != PIPE_FORMAT_R8_UINT &&
94 format != PIPE_FORMAT_R16_UINT &&
95 format != PIPE_FORMAT_R32_UINT)
96 return false;
97 bindings &= ~PIPE_BIND_INDEX_BUFFER;
98 }
99
100 return (( nv50_format_table[format].usage |
101 nv50_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
nv50_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)105 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 struct nouveau_screen *screen = nouveau_screen(pscreen);
108 const uint16_t class_3d = screen->class_3d;
109 struct nouveau_device *dev = screen->device;
110
111 switch (param) {
112 /* non-boolean caps */
113 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
114 return 8192;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
116 return 12;
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
118 return 14;
119 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
120 return 512;
121 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
122 case PIPE_CAP_MIN_TEXEL_OFFSET:
123 return -8;
124 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
125 case PIPE_CAP_MAX_TEXEL_OFFSET:
126 return 7;
127 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
128 return 128 * 1024 * 1024;
129 case PIPE_CAP_GLSL_FEATURE_LEVEL:
130 return 330;
131 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
132 return 330;
133 case PIPE_CAP_ESSL_FEATURE_LEVEL:
134 return class_3d >= NVA3_3D_CLASS ? 310 : 300;
135 case PIPE_CAP_MAX_RENDER_TARGETS:
136 return 8;
137 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
138 return 1;
139 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
140 return NV50_MAX_GLOBALS - 1;
141 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
142 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
143 return 8;
144 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
145 return 4;
146 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
147 return 64;
148 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
149 return 4;
150 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
151 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
152 return 1024;
153 case PIPE_CAP_MAX_VERTEX_STREAMS:
154 return 1;
155 case PIPE_CAP_MAX_GS_INVOCATIONS:
156 return 0;
157 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
158 return 1 << 27;
159 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
160 return 2048;
161 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
162 return 2047;
163 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
164 return 256;
165 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
166 return 16; /* 256 for binding as RT, but that's not possible in GL */
167 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
168 return 256; /* the access limit is aligned to 256 */
169 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
170 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
171 case PIPE_CAP_MAX_VIEWPORTS:
172 return NV50_MAX_VIEWPORTS;
173 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
174 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
175 case PIPE_CAP_ENDIANNESS:
176 return PIPE_ENDIAN_LITTLE;
177 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
178 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
179 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
180 return NV50_MAX_WINDOW_RECTANGLES;
181 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
182 return 16 * 1024 * 1024;
183 case PIPE_CAP_MAX_VARYINGS:
184 return 15;
185 case PIPE_CAP_MAX_VERTEX_BUFFERS:
186 return 16;
187 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
188 return 512 * 1024; /* TODO: Investigate tuning this */
189 case PIPE_CAP_MAX_TEXTURE_MB:
190 return 0; /* TODO: use 1/2 of VRAM for this? */
191
192 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
193 case PIPE_CAP_SUPPORTED_PRIM_MODES:
194 return BITFIELD_MASK(MESA_PRIM_COUNT);
195
196 /* supported caps */
197 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
198 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
199 case PIPE_CAP_TEXTURE_SWIZZLE:
200 case PIPE_CAP_NPOT_TEXTURES:
201 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
202 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
203 case PIPE_CAP_ANISOTROPIC_FILTER:
204 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
205 case PIPE_CAP_DEPTH_CLIP_DISABLE:
206 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
207 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
208 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
209 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
210 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
211 case PIPE_CAP_QUERY_TIMESTAMP:
212 case PIPE_CAP_QUERY_TIME_ELAPSED:
213 case PIPE_CAP_OCCLUSION_QUERY:
214 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
215 case PIPE_CAP_INDEP_BLEND_ENABLE:
216 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
217 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
218 case PIPE_CAP_PRIMITIVE_RESTART:
219 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
220 case PIPE_CAP_VS_INSTANCEID:
221 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
222 case PIPE_CAP_CONDITIONAL_RENDER:
223 case PIPE_CAP_TEXTURE_BARRIER:
224 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
225 case PIPE_CAP_START_INSTANCE:
226 case PIPE_CAP_USER_VERTEX_BUFFERS:
227 case PIPE_CAP_TEXTURE_MULTISAMPLE:
228 case PIPE_CAP_FS_FINE_DERIVATIVE:
229 case PIPE_CAP_SAMPLER_VIEW_TARGET:
230 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
231 case PIPE_CAP_CLIP_HALFZ:
232 case PIPE_CAP_MEMOBJ:
233 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
234 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
235 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
236 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
237 case PIPE_CAP_DEPTH_BOUNDS_TEST:
238 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
239 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
240 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
241 case PIPE_CAP_INVALIDATE_BUFFER:
242 case PIPE_CAP_STRING_MARKER:
243 case PIPE_CAP_CULL_DISTANCE:
244 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
245 case PIPE_CAP_LEGACY_MATH_RULES:
246 case PIPE_CAP_TGSI_TEX_TXF_LZ:
247 case PIPE_CAP_SHADER_CLOCK:
248 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
249 case PIPE_CAP_TGSI_DIV:
250 case PIPE_CAP_CLEAR_SCISSORED:
251 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
252 case PIPE_CAP_COMPUTE:
253 case PIPE_CAP_QUERY_MEMORY_INFO:
254 return 1;
255
256 case PIPE_CAP_ALPHA_TEST:
257 /* nvc0 has fixed function alpha test support, but nv50 doesn't. If we
258 * don't have it, then the frontend will lower it for us.
259 */
260 return class_3d >= NVC0_3D_CLASS;
261
262 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
263 return PIPE_TEXTURE_TRANSFER_BLIT;
264 case PIPE_CAP_SEAMLESS_CUBE_MAP:
265 return 1; /* class_3d >= NVA0_3D_CLASS; */
266 /* supported on nva0+ */
267 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
268 return class_3d >= NVA0_3D_CLASS;
269 /* supported on nva3+ */
270 case PIPE_CAP_CUBE_MAP_ARRAY:
271 case PIPE_CAP_INDEP_BLEND_FUNC:
272 case PIPE_CAP_TEXTURE_QUERY_LOD:
273 case PIPE_CAP_SAMPLE_SHADING:
274 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
275 return class_3d >= NVA3_3D_CLASS;
276
277 case PIPE_CAP_PCI_GROUP:
278 return dev->info.pci.domain;
279 case PIPE_CAP_PCI_BUS:
280 return dev->info.pci.bus;
281 case PIPE_CAP_PCI_DEVICE:
282 return dev->info.pci.dev;
283 case PIPE_CAP_PCI_FUNCTION:
284 return dev->info.pci.func;
285
286 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
287 case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
288 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE: /* when we fix MT stuff */
289 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
290 case PIPE_CAP_HARDWARE_GL_SELECT:
291 return 0;
292
293 case PIPE_CAP_VENDOR_ID:
294 return 0x10de;
295 case PIPE_CAP_DEVICE_ID:
296 return dev->info.device_id;
297 case PIPE_CAP_ACCELERATED:
298 return 1;
299 case PIPE_CAP_VIDEO_MEMORY:
300 return dev->vram_size >> 20;
301 case PIPE_CAP_UMA:
302 return nouveau_screen(pscreen)->is_uma;
303
304 default:
305 return u_pipe_screen_get_param_defaults(pscreen, param);
306 }
307 }
308
309 static int
nv50_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)310 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
311 enum pipe_shader_type shader,
312 enum pipe_shader_cap param)
313 {
314 switch (shader) {
315 case PIPE_SHADER_VERTEX:
316 case PIPE_SHADER_GEOMETRY:
317 case PIPE_SHADER_FRAGMENT:
318 case PIPE_SHADER_COMPUTE:
319 break;
320 default:
321 return 0;
322 }
323
324 switch (param) {
325 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
326 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
327 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
328 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
329 return 16384;
330 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
331 return 4;
332 case PIPE_SHADER_CAP_MAX_INPUTS:
333 if (shader == PIPE_SHADER_VERTEX)
334 return 32;
335 return 15;
336 case PIPE_SHADER_CAP_MAX_OUTPUTS:
337 return 16;
338 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
339 return 65536;
340 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
341 return NV50_MAX_PIPE_CONSTBUFS;
342 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
343 return shader != PIPE_SHADER_FRAGMENT;
344 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
345 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
346 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
347 return 1;
348 case PIPE_SHADER_CAP_MAX_TEMPS:
349 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
350 case PIPE_SHADER_CAP_CONT_SUPPORTED:
351 return 1;
352 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
353 return 1;
354 case PIPE_SHADER_CAP_INT64_ATOMICS:
355 case PIPE_SHADER_CAP_FP16:
356 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
357 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
358 case PIPE_SHADER_CAP_INT16:
359 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
360 case PIPE_SHADER_CAP_SUBROUTINES:
361 return 0; /* please inline, or provide function declarations */
362 case PIPE_SHADER_CAP_INTEGERS:
363 return 1;
364 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
365 /* The chip could handle more sampler views than samplers */
366 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
367 return MIN2(16, PIPE_MAX_SAMPLERS);
368 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
369 return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
370 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
371 return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
372 case PIPE_SHADER_CAP_SUPPORTED_IRS:
373 return 1 << PIPE_SHADER_IR_NIR;
374 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
375 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
376 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
377 return 0;
378 default:
379 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
380 return 0;
381 }
382 }
383
384 static float
nv50_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)385 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
386 {
387 switch (param) {
388 case PIPE_CAPF_MIN_LINE_WIDTH:
389 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
390 case PIPE_CAPF_MIN_POINT_SIZE:
391 case PIPE_CAPF_MIN_POINT_SIZE_AA:
392 return 1;
393 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
394 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
395 return 0.1;
396 case PIPE_CAPF_MAX_LINE_WIDTH:
397 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
398 return 10.0f;
399 case PIPE_CAPF_MAX_POINT_SIZE:
400 case PIPE_CAPF_MAX_POINT_SIZE_AA:
401 return 64.0f;
402 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
403 return 16.0f;
404 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
405 return 15.0f;
406 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
407 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
408 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
409 return 0.0f;
410 }
411
412 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
413 return 0.0f;
414 }
415
416 static int
nv50_screen_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * data)417 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
418 enum pipe_shader_ir ir_type,
419 enum pipe_compute_cap param, void *data)
420 {
421 struct nv50_screen *screen = nv50_screen(pscreen);
422 struct nouveau_device *dev = screen->base.device;
423
424 #define RET(x) do { \
425 if (data) \
426 memcpy(data, x, sizeof(x)); \
427 return sizeof(x); \
428 } while (0)
429
430 switch (param) {
431 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
432 RET((uint64_t []) { 3 });
433 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
434 RET(((uint64_t []) { 65535, 65535, 65535 }));
435 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
436 RET(((uint64_t []) { 512, 512, 64 }));
437 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
438 RET((uint64_t []) { 512 });
439 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
440 RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
441 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
442 RET((uint64_t []) { 16 << 10 });
443 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
444 RET((uint64_t []) { 16 << 10 });
445 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
446 RET((uint64_t []) { 4096 });
447 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
448 RET((uint32_t []) { 32 });
449 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
450 RET((uint32_t []) { 0 });
451 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
452 RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
453 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
454 RET((uint32_t []) { 0 });
455 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
456 RET((uint32_t []) { screen->mp_count });
457 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
458 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
459 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
460 RET((uint32_t []) { 32 });
461 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
462 RET((uint64_t []) { 0 });
463 default:
464 return 0;
465 }
466
467 #undef RET
468 }
469
470 static void
nv50_screen_destroy(struct pipe_screen * pscreen)471 nv50_screen_destroy(struct pipe_screen *pscreen)
472 {
473 struct nv50_screen *screen = nv50_screen(pscreen);
474
475 if (!nouveau_drm_screen_unref(&screen->base))
476 return;
477
478 if (screen->blitter)
479 nv50_blitter_destroy(screen);
480 if (screen->pm.prog) {
481 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
482 nv50_program_destroy(NULL, screen->pm.prog);
483 FREE(screen->pm.prog);
484 }
485
486 nouveau_bo_ref(NULL, &screen->code);
487 nouveau_bo_ref(NULL, &screen->tls_bo);
488 nouveau_bo_ref(NULL, &screen->stack_bo);
489 nouveau_bo_ref(NULL, &screen->txc);
490 nouveau_bo_ref(NULL, &screen->uniforms);
491 nouveau_bo_ref(NULL, &screen->fence.bo);
492
493 nouveau_heap_destroy(&screen->vp_code_heap);
494 nouveau_heap_destroy(&screen->gp_code_heap);
495 nouveau_heap_destroy(&screen->fp_code_heap);
496
497 FREE(screen->tic.entries);
498
499 nouveau_object_del(&screen->tesla);
500 nouveau_object_del(&screen->eng2d);
501 nouveau_object_del(&screen->m2mf);
502 nouveau_object_del(&screen->compute);
503 nouveau_object_del(&screen->sync);
504
505 nouveau_screen_fini(&screen->base);
506 simple_mtx_destroy(&screen->state_lock);
507
508 FREE(screen);
509 }
510
511 static void
nv50_screen_fence_emit(struct pipe_context * pcontext,u32 * sequence,struct nouveau_bo * wait)512 nv50_screen_fence_emit(struct pipe_context *pcontext, u32 *sequence,
513 struct nouveau_bo *wait)
514 {
515 struct nv50_context *nv50 = nv50_context(pcontext);
516 struct nv50_screen *screen = nv50->screen;
517 struct nouveau_pushbuf *push = nv50->base.pushbuf;
518 struct nouveau_pushbuf_refn ref = { wait, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR };
519
520 /* we need to do it after possible flush in MARK_RING */
521 *sequence = ++screen->base.fence.sequence;
522
523 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
524 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
525 PUSH_DATAh(push, screen->fence.bo->offset);
526 PUSH_DATA (push, screen->fence.bo->offset);
527 PUSH_DATA (push, *sequence);
528 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
529 NV50_3D_QUERY_GET_UNK4 |
530 NV50_3D_QUERY_GET_UNIT_CROP |
531 NV50_3D_QUERY_GET_TYPE_QUERY |
532 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
533 NV50_3D_QUERY_GET_SHORT);
534
535 nouveau_pushbuf_refn(push, &ref, 1);
536 }
537
538 static u32
nv50_screen_fence_update(struct pipe_screen * pscreen)539 nv50_screen_fence_update(struct pipe_screen *pscreen)
540 {
541 return nv50_screen(pscreen)->fence.map[0];
542 }
543
544 static void
nv50_screen_init_hwctx(struct nv50_screen * screen)545 nv50_screen_init_hwctx(struct nv50_screen *screen)
546 {
547 struct nouveau_pushbuf *push = screen->base.pushbuf;
548 struct nv04_fifo *fifo;
549 unsigned i;
550
551 fifo = (struct nv04_fifo *)screen->base.channel->data;
552
553 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
554 PUSH_DATA (push, screen->m2mf->handle);
555 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
556 PUSH_DATA (push, screen->sync->handle);
557 PUSH_DATA (push, fifo->vram);
558 PUSH_DATA (push, fifo->vram);
559
560 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
561 PUSH_DATA (push, screen->eng2d->handle);
562 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
563 PUSH_DATA (push, screen->sync->handle);
564 PUSH_DATA (push, fifo->vram);
565 PUSH_DATA (push, fifo->vram);
566 PUSH_DATA (push, fifo->vram);
567 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
568 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
569 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
570 PUSH_DATA (push, 0);
571 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
572 PUSH_DATA (push, 0);
573 BEGIN_NV04(push, NV50_2D(SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP), 1);
574 PUSH_DATA (push, 1);
575 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
576 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
577
578 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
579 PUSH_DATA (push, screen->tesla->handle);
580
581 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
582 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
583
584 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
585 PUSH_DATA (push, screen->sync->handle);
586 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
587 for (i = 0; i < 11; ++i)
588 PUSH_DATA(push, fifo->vram);
589 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
590 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
591 PUSH_DATA(push, fifo->vram);
592
593 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
594 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
595 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
596 PUSH_DATA (push, 0xf);
597
598 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
599 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
600 PUSH_DATA (push, 0x18);
601 }
602
603 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
604 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
605
606 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
607 for (i = 0; i < 8; ++i)
608 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
609
610 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
611 PUSH_DATA (push, 1);
612
613 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
614 PUSH_DATA (push, 0);
615 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
616 PUSH_DATA (push, 0);
617 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
618 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
619 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
620 PUSH_DATA (push, 0);
621 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
622 PUSH_DATA (push, 1);
623 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
624 PUSH_DATA (push, 1);
625
626 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
627 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
628 PUSH_DATA (push, 0);
629 }
630
631 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
632 PUSH_DATA (push, 0);
633 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
634 PUSH_DATA (push, 0);
635 PUSH_DATA (push, 0);
636 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
637 PUSH_DATA (push, 0x3f);
638
639 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
640 PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_VERTEX << NV50_CODE_BO_SIZE_LOG2));
641 PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_VERTEX << NV50_CODE_BO_SIZE_LOG2));
642
643 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
644 PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_FRAGMENT << NV50_CODE_BO_SIZE_LOG2));
645 PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_FRAGMENT << NV50_CODE_BO_SIZE_LOG2));
646
647 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
648 PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_GEOMETRY << NV50_CODE_BO_SIZE_LOG2));
649 PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_GEOMETRY << NV50_CODE_BO_SIZE_LOG2));
650
651 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
652 PUSH_DATAh(push, screen->tls_bo->offset);
653 PUSH_DATA (push, screen->tls_bo->offset);
654 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
655
656 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
657 PUSH_DATAh(push, screen->stack_bo->offset);
658 PUSH_DATA (push, screen->stack_bo->offset);
659 PUSH_DATA (push, 4);
660
661 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
662 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
663 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
664 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
665
666 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
667 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
668 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
669 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
670
671 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
672 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
673 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
674 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
675
676 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
677 PUSH_DATAh(push, screen->uniforms->offset + (4 << 16));
678 PUSH_DATA (push, screen->uniforms->offset + (4 << 16));
679 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
680
681 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
682 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
683 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
684 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
685
686 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
687 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
688 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
689 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
690 PUSH_DATAf(push, 0.0f);
691 PUSH_DATAf(push, 0.0f);
692 PUSH_DATAf(push, 0.0f);
693 PUSH_DATAf(push, 0.0f);
694 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
695 PUSH_DATAh(push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
696 PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
697
698 /* set the membar offset */
699 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
700 PUSH_DATA (push, (NV50_CB_AUX_MEMBAR_OFFSET << (8 - 2)) | NV50_CB_AUX);
701 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 1);
702 PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_MEMBAR_OFFSET);
703
704 nv50_upload_ms_info(push);
705
706 /* max TIC (bits 4:8) & TSC bindings, per program type */
707 for (i = 0; i < NV50_MAX_3D_SHADER_STAGES; ++i) {
708 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
709 PUSH_DATA (push, 0x54);
710 }
711
712 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
713 PUSH_DATAh(push, screen->txc->offset);
714 PUSH_DATA (push, screen->txc->offset);
715 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
716
717 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
718 PUSH_DATAh(push, screen->txc->offset + 65536);
719 PUSH_DATA (push, screen->txc->offset + 65536);
720 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
721
722 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
723 PUSH_DATA (push, 0);
724
725 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
726 PUSH_DATA (push, 0);
727 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
728 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
729 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
730 for (i = 0; i < 8 * 2; ++i)
731 PUSH_DATA(push, 0);
732 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
733 PUSH_DATA (push, 0);
734
735 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
736 PUSH_DATA (push, 1);
737 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
738 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
739 PUSH_DATAf(push, 0.0f);
740 PUSH_DATAf(push, 1.0f);
741 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
742 PUSH_DATA (push, 8192 << 16);
743 PUSH_DATA (push, 8192 << 16);
744 }
745
746 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
747 #ifdef NV50_SCISSORS_CLIPPING
748 PUSH_DATA (push, 0x0000);
749 #else
750 PUSH_DATA (push, 0x1080);
751 #endif
752
753 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
754 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
755
756 /* We use scissors instead of exact view volume clipping,
757 * so they're always enabled.
758 */
759 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
760 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
761 PUSH_DATA (push, 1);
762 PUSH_DATA (push, 8192 << 16);
763 PUSH_DATA (push, 8192 << 16);
764 }
765
766 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
767 PUSH_DATA (push, 1);
768 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
769 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
770 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
771 PUSH_DATA (push, 0x11111111);
772 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
773 PUSH_DATA (push, 1);
774
775 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
776 PUSH_DATA (push, 0);
777 if (screen->base.class_3d >= NV84_3D_CLASS) {
778 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
779 PUSH_DATA (push, 0);
780 }
781
782 BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
783 PUSH_DATA (push, 1);
784 BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
785 PUSH_DATA (push, 1);
786 }
787
nv50_tls_alloc(struct nv50_screen * screen,unsigned tls_space,uint64_t * tls_size)788 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
789 uint64_t *tls_size)
790 {
791 struct nouveau_device *dev = screen->base.device;
792 int ret;
793
794 assert(tls_space % ONE_TEMP_SIZE == 0);
795 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
796 ONE_TEMP_SIZE;
797 if (nouveau_mesa_debug)
798 debug_printf("allocating space for %u temps\n",
799 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
800 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
801 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
802
803 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
804 *tls_size, NULL, &screen->tls_bo);
805 if (ret) {
806 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
807 return ret;
808 }
809
810 return 0;
811 }
812
nv50_tls_realloc(struct nv50_screen * screen,unsigned tls_space)813 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
814 {
815 struct nouveau_pushbuf *push = screen->base.pushbuf;
816 int ret;
817 uint64_t tls_size;
818
819 if (tls_space < screen->cur_tls_space)
820 return 0;
821 if (tls_space > screen->max_tls_space) {
822 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
823 * LOCAL_WARPS_NO_CLAMP) */
824 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
825 (unsigned)(tls_space / ONE_TEMP_SIZE),
826 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
827 return -ENOMEM;
828 }
829
830 nouveau_bo_ref(NULL, &screen->tls_bo);
831 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
832 if (ret)
833 return ret;
834
835 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
836 PUSH_DATAh(push, screen->tls_bo->offset);
837 PUSH_DATA (push, screen->tls_bo->offset);
838 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
839
840 return 1;
841 }
842
843 static const void *
nv50_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)844 nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
845 enum pipe_shader_ir ir,
846 enum pipe_shader_type shader)
847 {
848 if (ir == PIPE_SHADER_IR_NIR)
849 return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
850 return NULL;
851 }
852
853 struct nouveau_screen *
nv50_screen_create(struct nouveau_device * dev)854 nv50_screen_create(struct nouveau_device *dev)
855 {
856 struct nv50_screen *screen;
857 struct pipe_screen *pscreen;
858 struct nouveau_object *chan;
859 uint64_t value;
860 uint32_t tesla_class;
861 unsigned stack_size;
862 int ret;
863
864 screen = CALLOC_STRUCT(nv50_screen);
865 if (!screen)
866 return NULL;
867 pscreen = &screen->base.base;
868 pscreen->destroy = nv50_screen_destroy;
869
870 simple_mtx_init(&screen->state_lock, mtx_plain);
871 ret = nouveau_screen_init(&screen->base, dev);
872 if (ret) {
873 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
874 goto fail;
875 }
876
877 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
878 * admit them to VRAM.
879 */
880 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
881 PIPE_BIND_VERTEX_BUFFER;
882 screen->base.sysmem_bindings |=
883 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
884
885 screen->base.pushbuf->rsvd_kick = 5;
886
887 chan = screen->base.channel;
888
889 pscreen->context_create = nv50_create;
890 pscreen->is_format_supported = nv50_screen_is_format_supported;
891 pscreen->get_param = nv50_screen_get_param;
892 pscreen->get_shader_param = nv50_screen_get_shader_param;
893 pscreen->get_paramf = nv50_screen_get_paramf;
894 pscreen->get_compute_param = nv50_screen_get_compute_param;
895 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
896 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
897
898 /* nir stuff */
899 pscreen->get_compiler_options = nv50_screen_get_compiler_options;
900
901 nv50_screen_init_resource_functions(pscreen);
902
903 if (screen->base.device->chipset < 0x84 ||
904 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
905 /* PMPEG */
906 nouveau_screen_init_vdec(&screen->base);
907 } else if (screen->base.device->chipset < 0x98 ||
908 screen->base.device->chipset == 0xa0) {
909 /* VP2 */
910 screen->base.base.get_video_param = nv84_screen_get_video_param;
911 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
912 } else {
913 /* VP3/4 */
914 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
915 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
916 }
917
918 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
919 NULL, &screen->fence.bo);
920 if (ret) {
921 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
922 goto fail;
923 }
924
925 BO_MAP(&screen->base, screen->fence.bo, 0, NULL);
926 screen->fence.map = screen->fence.bo->map;
927 screen->base.fence.emit = nv50_screen_fence_emit;
928 screen->base.fence.update = nv50_screen_fence_update;
929
930 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
931 &(struct nv04_notify){ .length = 32 },
932 sizeof(struct nv04_notify), &screen->sync);
933 if (ret) {
934 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
935 goto fail;
936 }
937
938 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
939 NULL, 0, &screen->m2mf);
940 if (ret) {
941 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
942 goto fail;
943 }
944
945 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
946 NULL, 0, &screen->eng2d);
947 if (ret) {
948 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
949 goto fail;
950 }
951
952 switch (dev->chipset & 0xf0) {
953 case 0x50:
954 tesla_class = NV50_3D_CLASS;
955 break;
956 case 0x80:
957 case 0x90:
958 tesla_class = NV84_3D_CLASS;
959 break;
960 case 0xa0:
961 switch (dev->chipset) {
962 case 0xa0:
963 case 0xaa:
964 case 0xac:
965 tesla_class = NVA0_3D_CLASS;
966 break;
967 case 0xaf:
968 tesla_class = NVAF_3D_CLASS;
969 break;
970 default:
971 tesla_class = NVA3_3D_CLASS;
972 break;
973 }
974 break;
975 default:
976 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
977 goto fail;
978 }
979 screen->base.class_3d = tesla_class;
980
981 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
982 NULL, 0, &screen->tesla);
983 if (ret) {
984 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
985 goto fail;
986 }
987
988 /* This over-allocates by a page. The GP, which would execute at the end of
989 * the last page, would trigger faults. The going theory is that it
990 * prefetches up to a certain amount.
991 */
992 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
993 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
994 NULL, &screen->code);
995 if (ret) {
996 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
997 goto fail;
998 }
999
1000 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1001 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1002 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1003
1004 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1005
1006 screen->TPs = util_bitcount(value & 0xffff);
1007 screen->MPsInTP = util_bitcount(value & 0x0f000000);
1008
1009 screen->mp_count = screen->TPs * screen->MPsInTP;
1010
1011 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1012 STACK_WARPS_ALLOC * 64 * 8;
1013
1014 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1015 &screen->stack_bo);
1016 if (ret) {
1017 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1018 goto fail;
1019 }
1020
1021 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1022 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
1023 ONE_TEMP_SIZE;
1024 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1025 screen->max_tls_space /= 2; /* half of vram */
1026
1027 /* hw can address max 64 KiB */
1028 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1029
1030 uint64_t tls_size;
1031 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1032 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1033 if (ret)
1034 goto fail;
1035
1036 if (nouveau_mesa_debug)
1037 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1038 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1039
1040 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 5 << 16, NULL,
1041 &screen->uniforms);
1042 if (ret) {
1043 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1044 goto fail;
1045 }
1046
1047 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1048 &screen->txc);
1049 if (ret) {
1050 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1051 goto fail;
1052 }
1053
1054 screen->tic.entries = CALLOC(4096, sizeof(void *));
1055 screen->tsc.entries = screen->tic.entries + 2048;
1056
1057 if (!nv50_blitter_create(screen))
1058 goto fail;
1059
1060 nv50_screen_init_hwctx(screen);
1061
1062 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1063 if (ret) {
1064 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1065 goto fail;
1066 }
1067
1068 // submit all initial state
1069 PUSH_KICK(screen->base.pushbuf);
1070
1071 return &screen->base;
1072
1073 fail:
1074 screen->base.base.context_create = NULL;
1075 return &screen->base;
1076 }
1077
1078 int
nv50_screen_tic_alloc(struct nv50_screen * screen,void * entry)1079 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1080 {
1081 int i = screen->tic.next;
1082
1083 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1084 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1085
1086 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1087
1088 if (screen->tic.entries[i])
1089 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1090
1091 screen->tic.entries[i] = entry;
1092 return i;
1093 }
1094
1095 int
nv50_screen_tsc_alloc(struct nv50_screen * screen,void * entry)1096 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1097 {
1098 int i = screen->tsc.next;
1099
1100 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1101 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1102
1103 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1104
1105 if (screen->tsc.entries[i])
1106 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1107
1108 screen->tsc.entries[i] = entry;
1109 return i;
1110 }
1111