1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28 #include "util/format_srgb.h"
29
30 #include "compiler/nir/nir.h"
31 #include "nir/tgsi_to_nir.h"
32
33 #include "nv50/nv50_stateobj.h"
34 #include "nv50/nv50_context.h"
35 #include "nv50/nv50_query_hw.h"
36
37 #include "nv50/nv50_3d.xml.h"
38 #include "nv50/g80_texture.xml.h"
39
40 #include "nouveau_gldefs.h"
41
42 /* Caveats:
43 * ! pipe_sampler_state.unnormalized_coords is ignored - rectangle textures
44 * will use non-normalized coordinates, everything else won't
45 * (The relevant bit is in the TIC entry and not the TSC entry.)
46 *
47 * ! pipe_sampler_state.seamless_cube_map is ignored - seamless filtering is
48 * always activated on NVA0 +
49 * (Give me the global bit, otherwise it's not worth the CPU work.)
50 *
51 * ! pipe_sampler_state.border_color is not swizzled according to the texture
52 * swizzle in pipe_sampler_view
53 * (This will be ugly with indirect independent texture/sampler access,
54 * we'd have to emulate the logic in the shader. GL doesn't have that,
55 * D3D doesn't have swizzle, if we knew what we were implementing we'd be
56 * good.)
57 *
58 * ! pipe_rasterizer_state.line_last_pixel is ignored - it is never drawn
59 *
60 * ! pipe_rasterizer_state.flatshade_first also applies to QUADS
61 * (There's a GL query for that, forcing an exception is just ridiculous.)
62 *
63 * ! pipe_rasterizer_state.sprite_coord_enable is masked with 0xff on NVC0
64 * (The hardware only has 8 slots meant for TexCoord and we have to assign
65 * in advance to maintain elegant separate shader objects.)
66 */
67
68 static inline uint32_t
nv50_colormask(unsigned mask)69 nv50_colormask(unsigned mask)
70 {
71 uint32_t ret = 0;
72
73 if (mask & PIPE_MASK_R)
74 ret |= 0x0001;
75 if (mask & PIPE_MASK_G)
76 ret |= 0x0010;
77 if (mask & PIPE_MASK_B)
78 ret |= 0x0100;
79 if (mask & PIPE_MASK_A)
80 ret |= 0x1000;
81
82 return ret;
83 }
84
85 #define NV50_BLEND_FACTOR_CASE(a, b) \
86 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
87
88 static inline uint32_t
nv50_blend_fac(unsigned factor)89 nv50_blend_fac(unsigned factor)
90 {
91 switch (factor) {
92 NV50_BLEND_FACTOR_CASE(ONE, ONE);
93 NV50_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
94 NV50_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
95 NV50_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
96 NV50_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
97 NV50_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
98 NV50_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
99 NV50_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
100 NV50_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
101 NV50_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
102 NV50_BLEND_FACTOR_CASE(ZERO, ZERO);
103 NV50_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
104 NV50_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
105 NV50_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
106 NV50_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
107 NV50_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
108 NV50_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
109 NV50_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
110 NV50_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
111 default:
112 return NV50_BLEND_FACTOR_ZERO;
113 }
114 }
115
116 static void *
nv50_blend_state_create(struct pipe_context * pipe,const struct pipe_blend_state * cso)117 nv50_blend_state_create(struct pipe_context *pipe,
118 const struct pipe_blend_state *cso)
119 {
120 struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj);
121 int i;
122 bool emit_common_func = cso->rt[0].blend_enable;
123 uint32_t ms;
124
125 if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
126 SB_BEGIN_3D(so, BLEND_INDEPENDENT, 1);
127 SB_DATA (so, cso->independent_blend_enable);
128 }
129
130 so->pipe = *cso;
131
132 SB_BEGIN_3D(so, COLOR_MASK_COMMON, 1);
133 SB_DATA (so, !cso->independent_blend_enable);
134
135 SB_BEGIN_3D(so, BLEND_ENABLE_COMMON, 1);
136 SB_DATA (so, !cso->independent_blend_enable);
137
138 if (cso->independent_blend_enable) {
139 SB_BEGIN_3D(so, BLEND_ENABLE(0), 8);
140 for (i = 0; i < 8; ++i) {
141 SB_DATA(so, cso->rt[i].blend_enable);
142 if (cso->rt[i].blend_enable)
143 emit_common_func = true;
144 }
145
146 if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
147 emit_common_func = false;
148
149 for (i = 0; i < 8; ++i) {
150 if (!cso->rt[i].blend_enable)
151 continue;
152 SB_BEGIN_3D_(so, NVA3_3D_IBLEND_EQUATION_RGB(i), 6);
153 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
154 SB_DATA (so, nv50_blend_fac(cso->rt[i].rgb_src_factor));
155 SB_DATA (so, nv50_blend_fac(cso->rt[i].rgb_dst_factor));
156 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
157 SB_DATA (so, nv50_blend_fac(cso->rt[i].alpha_src_factor));
158 SB_DATA (so, nv50_blend_fac(cso->rt[i].alpha_dst_factor));
159 }
160 }
161 } else {
162 SB_BEGIN_3D(so, BLEND_ENABLE(0), 1);
163 SB_DATA (so, cso->rt[0].blend_enable);
164 }
165
166 if (emit_common_func) {
167 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
168 SB_DATA (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
169 SB_DATA (so, nv50_blend_fac(cso->rt[0].rgb_src_factor));
170 SB_DATA (so, nv50_blend_fac(cso->rt[0].rgb_dst_factor));
171 SB_DATA (so, nvgl_blend_eqn(cso->rt[0].alpha_func));
172 SB_DATA (so, nv50_blend_fac(cso->rt[0].alpha_src_factor));
173 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
174 SB_DATA (so, nv50_blend_fac(cso->rt[0].alpha_dst_factor));
175 }
176
177 if (cso->logicop_enable) {
178 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
179 SB_DATA (so, 1);
180 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
181 } else {
182 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 1);
183 SB_DATA (so, 0);
184 }
185
186 if (cso->independent_blend_enable) {
187 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
188 for (i = 0; i < 8; ++i)
189 SB_DATA(so, nv50_colormask(cso->rt[i].colormask));
190 } else {
191 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
192 SB_DATA (so, nv50_colormask(cso->rt[0].colormask));
193 }
194
195 ms = 0;
196 if (cso->alpha_to_coverage)
197 ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
198 if (cso->alpha_to_one)
199 ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
200
201 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
202 SB_DATA (so, ms);
203
204 assert(so->size <= ARRAY_SIZE(so->state));
205 return so;
206 }
207
208 static void
nv50_blend_state_bind(struct pipe_context * pipe,void * hwcso)209 nv50_blend_state_bind(struct pipe_context *pipe, void *hwcso)
210 {
211 struct nv50_context *nv50 = nv50_context(pipe);
212
213 nv50->blend = hwcso;
214 nv50->dirty_3d |= NV50_NEW_3D_BLEND;
215 }
216
217 static void
nv50_blend_state_delete(struct pipe_context * pipe,void * hwcso)218 nv50_blend_state_delete(struct pipe_context *pipe, void *hwcso)
219 {
220 FREE(hwcso);
221 }
222
223 /* NOTE: ignoring line_last_pixel */
224 static void *
nv50_rasterizer_state_create(struct pipe_context * pipe,const struct pipe_rasterizer_state * cso)225 nv50_rasterizer_state_create(struct pipe_context *pipe,
226 const struct pipe_rasterizer_state *cso)
227 {
228 struct nv50_rasterizer_stateobj *so;
229 uint32_t reg;
230
231 so = CALLOC_STRUCT(nv50_rasterizer_stateobj);
232 if (!so)
233 return NULL;
234 so->pipe = *cso;
235
236 #ifndef NV50_SCISSORS_CLIPPING
237 for (int i = 0; i < NV50_MAX_VIEWPORTS; i++) {
238 SB_BEGIN_3D(so, SCISSOR_ENABLE(i), 1);
239 SB_DATA (so, cso->scissor);
240 }
241 #endif
242
243 SB_BEGIN_3D(so, SHADE_MODEL, 1);
244 SB_DATA (so, cso->flatshade ? NV50_3D_SHADE_MODEL_FLAT :
245 NV50_3D_SHADE_MODEL_SMOOTH);
246 SB_BEGIN_3D(so, PROVOKING_VERTEX_LAST, 1);
247 SB_DATA (so, !cso->flatshade_first);
248 SB_BEGIN_3D(so, VERTEX_TWO_SIDE_ENABLE, 1);
249 SB_DATA (so, cso->light_twoside);
250
251 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
252 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
253
254 SB_BEGIN_3D(so, MULTISAMPLE_ENABLE, 1);
255 SB_DATA (so, cso->multisample);
256
257 SB_BEGIN_3D(so, LINE_WIDTH, 1);
258 SB_DATA (so, fui(cso->line_width));
259 SB_BEGIN_3D(so, LINE_SMOOTH_ENABLE, 1);
260 SB_DATA (so, cso->line_smooth);
261
262 SB_BEGIN_3D(so, LINE_STIPPLE_ENABLE, 1);
263 if (cso->line_stipple_enable) {
264 SB_DATA (so, 1);
265 SB_BEGIN_3D(so, LINE_STIPPLE, 1);
266 SB_DATA (so, (cso->line_stipple_pattern << 8) |
267 cso->line_stipple_factor);
268 } else {
269 SB_DATA (so, 0);
270 }
271
272 if (!cso->point_size_per_vertex) {
273 SB_BEGIN_3D(so, POINT_SIZE, 1);
274 SB_DATA (so, fui(cso->point_size));
275 }
276 SB_BEGIN_3D(so, POINT_SPRITE_ENABLE, 1);
277 SB_DATA (so, cso->point_quad_rasterization);
278 SB_BEGIN_3D(so, POINT_SMOOTH_ENABLE, 1);
279 SB_DATA (so, cso->point_smooth);
280
281 SB_BEGIN_3D(so, POLYGON_MODE_FRONT, 3);
282 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
283 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
284 SB_DATA (so, cso->poly_smooth);
285
286 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
287 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
288 SB_DATA (so, cso->front_ccw ? NV50_3D_FRONT_FACE_CCW :
289 NV50_3D_FRONT_FACE_CW);
290 switch (cso->cull_face) {
291 case PIPE_FACE_FRONT_AND_BACK:
292 SB_DATA(so, NV50_3D_CULL_FACE_FRONT_AND_BACK);
293 break;
294 case PIPE_FACE_FRONT:
295 SB_DATA(so, NV50_3D_CULL_FACE_FRONT);
296 break;
297 case PIPE_FACE_BACK:
298 default:
299 SB_DATA(so, NV50_3D_CULL_FACE_BACK);
300 break;
301 }
302
303 SB_BEGIN_3D(so, POLYGON_STIPPLE_ENABLE, 1);
304 SB_DATA (so, cso->poly_stipple_enable);
305 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
306 SB_DATA (so, cso->offset_point);
307 SB_DATA (so, cso->offset_line);
308 SB_DATA (so, cso->offset_tri);
309
310 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
311 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
312 SB_DATA (so, fui(cso->offset_scale));
313 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
314 SB_DATA (so, fui(cso->offset_units * 2.0f));
315 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
316 SB_DATA (so, fui(cso->offset_clamp));
317 }
318
319 if (cso->depth_clip_near) {
320 reg = 0;
321 } else {
322 reg =
323 NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
324 NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
325 NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
326 }
327 #ifndef NV50_SCISSORS_CLIPPING
328 reg |=
329 NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK7 |
330 NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
331 #endif
332 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
333 SB_DATA (so, reg);
334
335 SB_BEGIN_3D(so, DEPTH_CLIP_NEGATIVE_Z, 1);
336 SB_DATA (so, cso->clip_halfz);
337
338 SB_BEGIN_3D(so, PIXEL_CENTER_INTEGER, 1);
339 SB_DATA (so, !cso->half_pixel_center);
340
341 assert(so->size <= ARRAY_SIZE(so->state));
342 return (void *)so;
343 }
344
345 static void
nv50_rasterizer_state_bind(struct pipe_context * pipe,void * hwcso)346 nv50_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
347 {
348 struct nv50_context *nv50 = nv50_context(pipe);
349
350 nv50->rast = hwcso;
351 nv50->dirty_3d |= NV50_NEW_3D_RASTERIZER;
352 }
353
354 static void
nv50_rasterizer_state_delete(struct pipe_context * pipe,void * hwcso)355 nv50_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
356 {
357 FREE(hwcso);
358 }
359
360 static void *
nv50_zsa_state_create(struct pipe_context * pipe,const struct pipe_depth_stencil_alpha_state * cso)361 nv50_zsa_state_create(struct pipe_context *pipe,
362 const struct pipe_depth_stencil_alpha_state *cso)
363 {
364 struct nv50_zsa_stateobj *so = CALLOC_STRUCT(nv50_zsa_stateobj);
365
366 so->pipe = *cso;
367
368 SB_BEGIN_3D(so, DEPTH_WRITE_ENABLE, 1);
369 SB_DATA (so, cso->depth_writemask);
370 SB_BEGIN_3D(so, DEPTH_TEST_ENABLE, 1);
371 if (cso->depth_enabled) {
372 SB_DATA (so, 1);
373 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374 SB_DATA (so, nvgl_comparison_op(cso->depth_func));
375 } else {
376 SB_DATA (so, 0);
377 }
378
379 SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1);
380 if (cso->depth_bounds_test) {
381 SB_DATA (so, 1);
382 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
383 SB_DATA (so, fui(cso->depth_bounds_min));
384 SB_DATA (so, fui(cso->depth_bounds_max));
385 } else {
386 SB_DATA (so, 0);
387 }
388
389 if (cso->stencil[0].enabled) {
390 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
391 SB_DATA (so, 1);
392 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
393 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
394 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
395 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
396 SB_BEGIN_3D(so, STENCIL_FRONT_MASK, 2);
397 SB_DATA (so, cso->stencil[0].writemask);
398 SB_DATA (so, cso->stencil[0].valuemask);
399 } else {
400 SB_BEGIN_3D(so, STENCIL_ENABLE, 1);
401 SB_DATA (so, 0);
402 }
403
404 if (cso->stencil[1].enabled) {
405 assert(cso->stencil[0].enabled);
406 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
407 SB_DATA (so, 1);
408 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
409 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
410 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
411 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
412 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
413 SB_DATA (so, cso->stencil[1].writemask);
414 SB_DATA (so, cso->stencil[1].valuemask);
415 } else {
416 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 1);
417 SB_DATA (so, 0);
418 }
419
420 SB_BEGIN_3D(so, ALPHA_TEST_ENABLE, 1);
421 if (cso->alpha_enabled) {
422 SB_DATA (so, 1);
423 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
424 SB_DATA (so, fui(cso->alpha_ref_value));
425 SB_DATA (so, nvgl_comparison_op(cso->alpha_func));
426 } else {
427 SB_DATA (so, 0);
428 }
429
430 SB_BEGIN_3D(so, CB_ADDR, 1);
431 SB_DATA (so, NV50_CB_AUX_ALPHATEST_OFFSET << (8 - 2) | NV50_CB_AUX);
432 SB_BEGIN_3D(so, CB_DATA(0), 1);
433 SB_DATA (so, fui(cso->alpha_ref_value));
434
435 assert(so->size <= ARRAY_SIZE(so->state));
436 return (void *)so;
437 }
438
439 static void
nv50_zsa_state_bind(struct pipe_context * pipe,void * hwcso)440 nv50_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
441 {
442 struct nv50_context *nv50 = nv50_context(pipe);
443
444 nv50->zsa = hwcso;
445 nv50->dirty_3d |= NV50_NEW_3D_ZSA;
446 }
447
448 static void
nv50_zsa_state_delete(struct pipe_context * pipe,void * hwcso)449 nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
450 {
451 FREE(hwcso);
452 }
453
454 /* ====================== SAMPLERS AND TEXTURES ================================
455 */
456
457 static inline unsigned
nv50_tsc_wrap_mode(unsigned wrap)458 nv50_tsc_wrap_mode(unsigned wrap)
459 {
460 switch (wrap) {
461 case PIPE_TEX_WRAP_REPEAT:
462 return G80_TSC_WRAP_WRAP;
463 case PIPE_TEX_WRAP_MIRROR_REPEAT:
464 return G80_TSC_WRAP_MIRROR;
465 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
466 return G80_TSC_WRAP_CLAMP_TO_EDGE;
467 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
468 return G80_TSC_WRAP_BORDER;
469 case PIPE_TEX_WRAP_CLAMP:
470 return G80_TSC_WRAP_CLAMP_OGL;
471 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
472 return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE;
473 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
474 return G80_TSC_WRAP_MIRROR_ONCE_BORDER;
475 case PIPE_TEX_WRAP_MIRROR_CLAMP:
476 return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL;
477 default:
478 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
479 return G80_TSC_WRAP_WRAP;
480 }
481 }
482
483 void *
nv50_sampler_state_create(struct pipe_context * pipe,const struct pipe_sampler_state * cso)484 nv50_sampler_state_create(struct pipe_context *pipe,
485 const struct pipe_sampler_state *cso)
486 {
487 struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
488 float f[2];
489
490 so->id = -1;
491
492 so->tsc[0] = (0x00026000 |
493 (nv50_tsc_wrap_mode(cso->wrap_s) << 0) |
494 (nv50_tsc_wrap_mode(cso->wrap_t) << 3) |
495 (nv50_tsc_wrap_mode(cso->wrap_r) << 6));
496
497 switch (cso->mag_img_filter) {
498 case PIPE_TEX_FILTER_LINEAR:
499 so->tsc[1] = G80_TSC_1_MAG_FILTER_LINEAR;
500 break;
501 case PIPE_TEX_FILTER_NEAREST:
502 default:
503 so->tsc[1] = G80_TSC_1_MAG_FILTER_NEAREST;
504 break;
505 }
506
507 switch (cso->min_img_filter) {
508 case PIPE_TEX_FILTER_LINEAR:
509 so->tsc[1] |= G80_TSC_1_MIN_FILTER_LINEAR;
510 break;
511 case PIPE_TEX_FILTER_NEAREST:
512 default:
513 so->tsc[1] |= G80_TSC_1_MIN_FILTER_NEAREST;
514 break;
515 }
516
517 switch (cso->min_mip_filter) {
518 case PIPE_TEX_MIPFILTER_LINEAR:
519 so->tsc[1] |= G80_TSC_1_MIP_FILTER_LINEAR;
520 break;
521 case PIPE_TEX_MIPFILTER_NEAREST:
522 so->tsc[1] |= G80_TSC_1_MIP_FILTER_NEAREST;
523 break;
524 case PIPE_TEX_MIPFILTER_NONE:
525 default:
526 so->tsc[1] |= G80_TSC_1_MIP_FILTER_NONE;
527 break;
528 }
529
530 if (nouveau_screen(pipe->screen)->class_3d >= NVE4_3D_CLASS) {
531 if (cso->seamless_cube_map)
532 so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
533 if (cso->unnormalized_coords)
534 so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
535 } else {
536 so->seamless_cube_map = cso->seamless_cube_map;
537 }
538
539 if (nouveau_screen(pipe->screen)->class_3d >= GM200_3D_CLASS) {
540 if (cso->reduction_mode == PIPE_TEX_REDUCTION_MIN)
541 so->tsc[1] |= GM204_TSC_1_REDUCTION_MODE_MIN;
542 if (cso->reduction_mode == PIPE_TEX_REDUCTION_MAX)
543 so->tsc[1] |= GM204_TSC_1_REDUCTION_MODE_MAX;
544 }
545
546 if (cso->max_anisotropy >= 16)
547 so->tsc[0] |= (7 << 20);
548 else
549 if (cso->max_anisotropy >= 12)
550 so->tsc[0] |= (6 << 20);
551 else {
552 so->tsc[0] |= (cso->max_anisotropy >> 1) << 20;
553
554 if (cso->max_anisotropy >= 4)
555 so->tsc[1] |= 6 << G80_TSC_1_TRILIN_OPT__SHIFT;
556 else
557 if (cso->max_anisotropy >= 2)
558 so->tsc[1] |= 4 << G80_TSC_1_TRILIN_OPT__SHIFT;
559 }
560
561 if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
562 /* NOTE: must be deactivated for non-shadow textures */
563 so->tsc[0] |= (1 << 9);
564 so->tsc[0] |= (nvgl_comparison_op(cso->compare_func) & 0x7) << 10;
565 }
566
567 f[0] = CLAMP(cso->lod_bias, -16.0f, 15.0f);
568 so->tsc[1] |= ((int)(f[0] * 256.0f) & 0x1fff) << 12;
569
570 f[0] = CLAMP(cso->min_lod, 0.0f, 15.0f);
571 f[1] = CLAMP(cso->max_lod, 0.0f, 15.0f);
572 so->tsc[2] =
573 (((int)(f[1] * 256.0f) & 0xfff) << 12) | ((int)(f[0] * 256.0f) & 0xfff);
574
575 so->tsc[2] |=
576 util_format_linear_float_to_srgb_8unorm(cso->border_color.f[0]) << 24;
577 so->tsc[3] =
578 util_format_linear_float_to_srgb_8unorm(cso->border_color.f[1]) << 12;
579 so->tsc[3] |=
580 util_format_linear_float_to_srgb_8unorm(cso->border_color.f[2]) << 20;
581
582 so->tsc[4] = fui(cso->border_color.f[0]);
583 so->tsc[5] = fui(cso->border_color.f[1]);
584 so->tsc[6] = fui(cso->border_color.f[2]);
585 so->tsc[7] = fui(cso->border_color.f[3]);
586
587 return (void *)so;
588 }
589
590 static void
nv50_sampler_state_delete(struct pipe_context * pipe,void * hwcso)591 nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
592 {
593 unsigned s, i;
594
595 for (s = 0; s < NV50_MAX_SHADER_STAGES; ++s) {
596 assert(nv50_context(pipe)->num_samplers[s] <= PIPE_MAX_SAMPLERS);
597 for (i = 0; i < nv50_context(pipe)->num_samplers[s]; ++i)
598 if (nv50_context(pipe)->samplers[s][i] == hwcso)
599 nv50_context(pipe)->samplers[s][i] = NULL;
600 }
601
602 nv50_screen_tsc_free(nv50_context(pipe)->screen, nv50_tsc_entry(hwcso));
603
604 FREE(hwcso);
605 }
606
607 static inline void
nv50_stage_sampler_states_bind(struct nv50_context * nv50,int s,unsigned nr,void ** hwcsos)608 nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
609 unsigned nr, void **hwcsos)
610 {
611 unsigned highest_found = 0;
612 unsigned i;
613
614 assert(nr <= PIPE_MAX_SAMPLERS);
615 for (i = 0; i < nr; ++i) {
616 struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
617 struct nv50_tsc_entry *old = nv50->samplers[s][i];
618
619 if (hwcso)
620 highest_found = i;
621
622 nv50->samplers[s][i] = hwcso;
623 if (old)
624 nv50_screen_tsc_unlock(nv50->screen, old);
625 }
626 assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
627 if (nr >= nv50->num_samplers[s])
628 nv50->num_samplers[s] = highest_found + 1;
629 }
630
631 static void
nv50_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned num_samplers,void ** samplers)632 nv50_bind_sampler_states(struct pipe_context *pipe,
633 enum pipe_shader_type shader, unsigned start,
634 unsigned num_samplers, void **samplers)
635 {
636 unsigned s = nv50_context_shader_stage(shader);
637
638 assert(start == 0);
639 nv50_stage_sampler_states_bind(nv50_context(pipe), s, num_samplers,
640 samplers);
641
642 if (unlikely(s == NV50_SHADER_STAGE_COMPUTE))
643 nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_SAMPLERS;
644 else
645 nv50_context(pipe)->dirty_3d |= NV50_NEW_3D_SAMPLERS;
646 }
647
648
649
650 /* NOTE: only called when not referenced anywhere, won't be bound */
651 static void
nv50_sampler_view_destroy(struct pipe_context * pipe,struct pipe_sampler_view * view)652 nv50_sampler_view_destroy(struct pipe_context *pipe,
653 struct pipe_sampler_view *view)
654 {
655 pipe_resource_reference(&view->texture, NULL);
656
657 nv50_screen_tic_free(nv50_context(pipe)->screen, nv50_tic_entry(view));
658
659 FREE(nv50_tic_entry(view));
660 }
661
662 static inline void
nv50_stage_set_sampler_views(struct nv50_context * nv50,int s,unsigned nr,bool take_ownership,struct pipe_sampler_view ** views)663 nv50_stage_set_sampler_views(struct nv50_context *nv50, int s,
664 unsigned nr, bool take_ownership,
665 struct pipe_sampler_view **views)
666 {
667 unsigned i;
668
669 assert(nr <= PIPE_MAX_SAMPLERS);
670 for (i = 0; i < nr; ++i) {
671 struct pipe_sampler_view *view = views ? views[i] : NULL;
672 struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
673 if (old)
674 nv50_screen_tic_unlock(nv50->screen, old);
675
676 if (view && view->texture) {
677 struct pipe_resource *res = view->texture;
678 if (res->target == PIPE_BUFFER &&
679 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
680 nv50->textures_coherent[s] |= 1 << i;
681 else
682 nv50->textures_coherent[s] &= ~(1 << i);
683 } else {
684 nv50->textures_coherent[s] &= ~(1 << i);
685 }
686
687 if (take_ownership) {
688 pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
689 nv50->textures[s][i] = view;
690 } else {
691 pipe_sampler_view_reference(&nv50->textures[s][i], view);
692 }
693 }
694
695 assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
696 for (i = nr; i < nv50->num_textures[s]; ++i) {
697 struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
698 if (!old)
699 continue;
700 nv50_screen_tic_unlock(nv50->screen, old);
701
702 pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
703 }
704
705 nv50->num_textures[s] = nr;
706 }
707
708 static void
nv50_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)709 nv50_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
710 unsigned start, unsigned nr,
711 unsigned unbind_num_trailing_slots,
712 bool take_ownership,
713 struct pipe_sampler_view **views)
714 {
715 struct nv50_context *nv50 = nv50_context(pipe);
716 unsigned s = nv50_context_shader_stage(shader);
717
718 assert(start == 0);
719 nv50_stage_set_sampler_views(nv50, s, nr, take_ownership, views);
720
721 if (unlikely(s == NV50_SHADER_STAGE_COMPUTE)) {
722 nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_TEXTURES);
723
724 nv50->dirty_cp |= NV50_NEW_CP_TEXTURES;
725 } else {
726 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
727
728 nv50->dirty_3d |= NV50_NEW_3D_TEXTURES;
729 }
730 }
731
732
733
734 /* ============================= SHADERS =======================================
735 */
736
737 static void *
nv50_sp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso,enum pipe_shader_type type)738 nv50_sp_state_create(struct pipe_context *pipe,
739 const struct pipe_shader_state *cso,
740 enum pipe_shader_type type)
741 {
742 struct nv50_program *prog;
743
744 prog = CALLOC_STRUCT(nv50_program);
745 if (!prog)
746 return NULL;
747
748 prog->type = type;
749
750 switch (cso->type) {
751 case PIPE_SHADER_IR_TGSI:
752 prog->nir = tgsi_to_nir(cso->tokens, pipe->screen, false);
753 break;
754 case PIPE_SHADER_IR_NIR:
755 prog->nir = cso->ir.nir;
756 break;
757 default:
758 assert(!"unsupported IR!");
759 free(prog);
760 return NULL;
761 }
762
763 if (cso->stream_output.num_outputs)
764 prog->stream_output = cso->stream_output;
765
766 prog->translated = nv50_program_translate(
767 prog, nv50_context(pipe)->screen->base.device->chipset,
768 &nouveau_context(pipe)->debug);
769
770 return (void *)prog;
771 }
772
773 static void
nv50_sp_state_delete(struct pipe_context * pipe,void * hwcso)774 nv50_sp_state_delete(struct pipe_context *pipe, void *hwcso)
775 {
776 struct nv50_context *nv50 = nv50_context(pipe);
777 struct nv50_program *prog = (struct nv50_program *)hwcso;
778
779 simple_mtx_lock(&nv50->screen->state_lock);
780 nv50_program_destroy(nv50, prog);
781 simple_mtx_unlock(&nv50->screen->state_lock);
782
783 ralloc_free(prog->nir);
784 FREE(prog);
785 }
786
787 static void *
nv50_vp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)788 nv50_vp_state_create(struct pipe_context *pipe,
789 const struct pipe_shader_state *cso)
790 {
791 return nv50_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
792 }
793
794 static void
nv50_vp_state_bind(struct pipe_context * pipe,void * hwcso)795 nv50_vp_state_bind(struct pipe_context *pipe, void *hwcso)
796 {
797 struct nv50_context *nv50 = nv50_context(pipe);
798
799 nv50->vertprog = hwcso;
800 nv50->dirty_3d |= NV50_NEW_3D_VERTPROG;
801 }
802
803 static void *
nv50_fp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)804 nv50_fp_state_create(struct pipe_context *pipe,
805 const struct pipe_shader_state *cso)
806 {
807 return nv50_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
808 }
809
810 static void
nv50_fp_state_bind(struct pipe_context * pipe,void * hwcso)811 nv50_fp_state_bind(struct pipe_context *pipe, void *hwcso)
812 {
813 struct nv50_context *nv50 = nv50_context(pipe);
814
815 nv50->fragprog = hwcso;
816 nv50->dirty_3d |= NV50_NEW_3D_FRAGPROG;
817 }
818
819 static void *
nv50_gp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)820 nv50_gp_state_create(struct pipe_context *pipe,
821 const struct pipe_shader_state *cso)
822 {
823 return nv50_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
824 }
825
826 static void
nv50_gp_state_bind(struct pipe_context * pipe,void * hwcso)827 nv50_gp_state_bind(struct pipe_context *pipe, void *hwcso)
828 {
829 struct nv50_context *nv50 = nv50_context(pipe);
830
831 nv50->gmtyprog = hwcso;
832 nv50->dirty_3d |= NV50_NEW_3D_GMTYPROG;
833 }
834
835 static void *
nv50_cp_state_create(struct pipe_context * pipe,const struct pipe_compute_state * cso)836 nv50_cp_state_create(struct pipe_context *pipe,
837 const struct pipe_compute_state *cso)
838 {
839 struct nv50_program *prog;
840
841 prog = CALLOC_STRUCT(nv50_program);
842 if (!prog)
843 return NULL;
844 prog->type = PIPE_SHADER_COMPUTE;
845
846 switch(cso->ir_type) {
847 case PIPE_SHADER_IR_TGSI: {
848 const struct tgsi_token *tokens = cso->prog;
849 prog->nir = tgsi_to_nir(tokens, pipe->screen, false);
850 break;
851 }
852 case PIPE_SHADER_IR_NIR:
853 prog->nir = (nir_shader *)cso->prog;
854 break;
855 default:
856 assert(!"unsupported IR!");
857 free(prog);
858 return NULL;
859 }
860
861 prog->cp.smem_size = cso->static_shared_mem;
862 prog->parm_size = cso->req_input_mem;
863
864 return (void *)prog;
865 }
866
867 static void
nv50_cp_state_bind(struct pipe_context * pipe,void * hwcso)868 nv50_cp_state_bind(struct pipe_context *pipe, void *hwcso)
869 {
870 struct nv50_context *nv50 = nv50_context(pipe);
871
872 nv50->compprog = hwcso;
873 nv50->dirty_cp |= NV50_NEW_CP_PROGRAM;
874 }
875
876 static void
nv50_get_compute_state_info(struct pipe_context * pipe,void * hwcso,struct pipe_compute_state_object_info * info)877 nv50_get_compute_state_info(struct pipe_context *pipe, void *hwcso,
878 struct pipe_compute_state_object_info *info)
879 {
880 struct nv50_context *nv50 = nv50_context(pipe);
881 struct nv50_program *prog = (struct nv50_program *)hwcso;
882 uint16_t obj_class = nv50->screen->compute->oclass;
883 uint32_t smregs = obj_class >= NVA3_COMPUTE_CLASS ? 16384 : 8192;
884 uint32_t threads = smregs / align(prog->max_gpr, 4);
885
886 info->max_threads = MIN2(ROUND_DOWN_TO(threads, 32), 512);
887 info->private_memory = prog->tls_space;
888 info->preferred_simd_size = 32;
889 info->simd_sizes = 32;
890 }
891
892 static void
nv50_set_constant_buffer(struct pipe_context * pipe,enum pipe_shader_type shader,uint index,bool take_ownership,const struct pipe_constant_buffer * cb)893 nv50_set_constant_buffer(struct pipe_context *pipe,
894 enum pipe_shader_type shader, uint index,
895 bool take_ownership,
896 const struct pipe_constant_buffer *cb)
897 {
898 struct nv50_context *nv50 = nv50_context(pipe);
899 struct pipe_resource *res = cb ? cb->buffer : NULL;
900 const unsigned s = nv50_context_shader_stage(shader);
901 const unsigned i = index;
902
903 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
904 if (nv50->constbuf[s][i].user)
905 nv50->constbuf[s][i].u.buf = NULL;
906 else
907 if (nv50->constbuf[s][i].u.buf)
908 nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_CB(i));
909
910 nv50->dirty_cp |= NV50_NEW_CP_CONSTBUF;
911 } else {
912 if (nv50->constbuf[s][i].user)
913 nv50->constbuf[s][i].u.buf = NULL;
914 else
915 if (nv50->constbuf[s][i].u.buf)
916 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_CB(s, i));
917
918 nv50->dirty_3d |= NV50_NEW_3D_CONSTBUF;
919 }
920 nv50->constbuf_dirty[s] |= 1 << i;
921
922 if (nv50->constbuf[s][i].u.buf)
923 nv04_resource(nv50->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
924
925 if (take_ownership) {
926 pipe_resource_reference(&nv50->constbuf[s][i].u.buf, NULL);
927 nv50->constbuf[s][i].u.buf = res;
928 } else {
929 pipe_resource_reference(&nv50->constbuf[s][i].u.buf, res);
930 }
931
932 nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
933 if (nv50->constbuf[s][i].user) {
934 nv50->constbuf[s][i].u.data = cb->user_buffer;
935 nv50->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
936 nv50->constbuf_valid[s] |= 1 << i;
937 nv50->constbuf_coherent[s] &= ~(1 << i);
938 } else
939 if (cb) {
940 nv50->constbuf[s][i].offset = cb->buffer_offset;
941 nv50->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
942 nv50->constbuf_valid[s] |= 1 << i;
943 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
944 nv50->constbuf_coherent[s] |= 1 << i;
945 else
946 nv50->constbuf_coherent[s] &= ~(1 << i);
947 }
948 else {
949 nv50->constbuf_valid[s] &= ~(1 << i);
950 nv50->constbuf_coherent[s] &= ~(1 << i);
951 }
952 }
953
954 /* =============================================================================
955 */
956
957 static void
nv50_set_blend_color(struct pipe_context * pipe,const struct pipe_blend_color * bcol)958 nv50_set_blend_color(struct pipe_context *pipe,
959 const struct pipe_blend_color *bcol)
960 {
961 struct nv50_context *nv50 = nv50_context(pipe);
962
963 nv50->blend_colour = *bcol;
964 nv50->dirty_3d |= NV50_NEW_3D_BLEND_COLOUR;
965 }
966
967 static void
nv50_set_stencil_ref(struct pipe_context * pipe,const struct pipe_stencil_ref sr)968 nv50_set_stencil_ref(struct pipe_context *pipe,
969 const struct pipe_stencil_ref sr)
970 {
971 struct nv50_context *nv50 = nv50_context(pipe);
972
973 nv50->stencil_ref = sr;
974 nv50->dirty_3d |= NV50_NEW_3D_STENCIL_REF;
975 }
976
977 static void
nv50_set_clip_state(struct pipe_context * pipe,const struct pipe_clip_state * clip)978 nv50_set_clip_state(struct pipe_context *pipe,
979 const struct pipe_clip_state *clip)
980 {
981 struct nv50_context *nv50 = nv50_context(pipe);
982
983 memcpy(nv50->clip.ucp, clip->ucp, sizeof(clip->ucp));
984
985 nv50->dirty_3d |= NV50_NEW_3D_CLIP;
986 }
987
988 static void
nv50_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)989 nv50_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
990 {
991 struct nv50_context *nv50 = nv50_context(pipe);
992
993 nv50->sample_mask = sample_mask;
994 nv50->dirty_3d |= NV50_NEW_3D_SAMPLE_MASK;
995 }
996
997 static void
nv50_set_min_samples(struct pipe_context * pipe,unsigned min_samples)998 nv50_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
999 {
1000 struct nv50_context *nv50 = nv50_context(pipe);
1001
1002 if (nv50->min_samples != min_samples) {
1003 nv50->min_samples = min_samples;
1004 nv50->dirty_3d |= NV50_NEW_3D_MIN_SAMPLES;
1005 }
1006 }
1007
1008 static void
nv50_set_framebuffer_state(struct pipe_context * pipe,const struct pipe_framebuffer_state * fb)1009 nv50_set_framebuffer_state(struct pipe_context *pipe,
1010 const struct pipe_framebuffer_state *fb)
1011 {
1012 struct nv50_context *nv50 = nv50_context(pipe);
1013
1014 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1015
1016 util_copy_framebuffer_state(&nv50->framebuffer, fb);
1017
1018 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_TEXTURES;
1019 }
1020
1021 static void
nv50_set_polygon_stipple(struct pipe_context * pipe,const struct pipe_poly_stipple * stipple)1022 nv50_set_polygon_stipple(struct pipe_context *pipe,
1023 const struct pipe_poly_stipple *stipple)
1024 {
1025 struct nv50_context *nv50 = nv50_context(pipe);
1026
1027 nv50->stipple = *stipple;
1028 nv50->dirty_3d |= NV50_NEW_3D_STIPPLE;
1029 }
1030
1031 static void
nv50_set_scissor_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * scissor)1032 nv50_set_scissor_states(struct pipe_context *pipe,
1033 unsigned start_slot,
1034 unsigned num_scissors,
1035 const struct pipe_scissor_state *scissor)
1036 {
1037 struct nv50_context *nv50 = nv50_context(pipe);
1038 int i;
1039
1040 assert(start_slot + num_scissors <= NV50_MAX_VIEWPORTS);
1041 for (i = 0; i < num_scissors; i++) {
1042 if (!memcmp(&nv50->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
1043 continue;
1044 nv50->scissors[start_slot + i] = scissor[i];
1045 nv50->scissors_dirty |= 1 << (start_slot + i);
1046 nv50->dirty_3d |= NV50_NEW_3D_SCISSOR;
1047 }
1048 }
1049
1050 static void
nv50_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt)1051 nv50_set_viewport_states(struct pipe_context *pipe,
1052 unsigned start_slot,
1053 unsigned num_viewports,
1054 const struct pipe_viewport_state *vpt)
1055 {
1056 struct nv50_context *nv50 = nv50_context(pipe);
1057 int i;
1058
1059 assert(start_slot + num_viewports <= NV50_MAX_VIEWPORTS);
1060 for (i = 0; i < num_viewports; i++) {
1061 if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1062 continue;
1063 nv50->viewports[start_slot + i] = vpt[i];
1064 nv50->viewports_dirty |= 1 << (start_slot + i);
1065 nv50->dirty_3d |= NV50_NEW_3D_VIEWPORT;
1066 }
1067 }
1068
1069 static void
nv50_set_window_rectangles(struct pipe_context * pipe,bool include,unsigned num_rectangles,const struct pipe_scissor_state * rectangles)1070 nv50_set_window_rectangles(struct pipe_context *pipe,
1071 bool include,
1072 unsigned num_rectangles,
1073 const struct pipe_scissor_state *rectangles)
1074 {
1075 struct nv50_context *nv50 = nv50_context(pipe);
1076
1077 nv50->window_rect.inclusive = include;
1078 nv50->window_rect.rects = MIN2(num_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1079 memcpy(nv50->window_rect.rect, rectangles,
1080 sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1081
1082 nv50->dirty_3d |= NV50_NEW_3D_WINDOW_RECTS;
1083 }
1084
1085 static void
nv50_set_vertex_buffers(struct pipe_context * pipe,unsigned count,const struct pipe_vertex_buffer * vb)1086 nv50_set_vertex_buffers(struct pipe_context *pipe,
1087 unsigned count,
1088 const struct pipe_vertex_buffer *vb)
1089 {
1090 struct nv50_context *nv50 = nv50_context(pipe);
1091 unsigned i;
1092
1093 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX);
1094 nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
1095
1096 unsigned last_count = nv50->num_vtxbufs;
1097 util_set_vertex_buffers_count(nv50->vtxbuf, &nv50->num_vtxbufs, vb,
1098 count, true);
1099
1100 unsigned clear_mask =
1101 last_count > count ? BITFIELD_RANGE(count, last_count - count) : 0;
1102 nv50->vbo_user &= clear_mask;
1103 nv50->vbo_constant &= clear_mask;
1104 nv50->vtxbufs_coherent &= clear_mask;
1105
1106 if (!vb) {
1107 clear_mask = ~u_bit_consecutive(0, count);
1108 nv50->vbo_user &= clear_mask;
1109 nv50->vbo_constant &= clear_mask;
1110 nv50->vtxbufs_coherent &= clear_mask;
1111 return;
1112 }
1113
1114 for (i = 0; i < count; ++i) {
1115 unsigned dst_index = i;
1116
1117 if (vb[i].is_user_buffer) {
1118 nv50->vbo_user |= 1 << dst_index;
1119 nv50->vtxbufs_coherent &= ~(1 << dst_index);
1120 } else {
1121 nv50->vbo_user &= ~(1 << dst_index);
1122
1123 if (vb[i].buffer.resource &&
1124 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1125 nv50->vtxbufs_coherent |= (1 << dst_index);
1126 else
1127 nv50->vtxbufs_coherent &= ~(1 << dst_index);
1128 }
1129 }
1130 }
1131
1132 static void
nv50_vertex_state_bind(struct pipe_context * pipe,void * hwcso)1133 nv50_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1134 {
1135 struct nv50_context *nv50 = nv50_context(pipe);
1136
1137 nv50->vertex = hwcso;
1138 nv50->dirty_3d |= NV50_NEW_3D_VERTEX;
1139 }
1140
1141 static struct pipe_stream_output_target *
nv50_so_target_create(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size)1142 nv50_so_target_create(struct pipe_context *pipe,
1143 struct pipe_resource *res,
1144 unsigned offset, unsigned size)
1145 {
1146 struct nv04_resource *buf = (struct nv04_resource *)res;
1147 struct nv50_so_target *targ = MALLOC_STRUCT(nv50_so_target);
1148 if (!targ)
1149 return NULL;
1150
1151 if (nouveau_context(pipe)->screen->class_3d >= NVA0_3D_CLASS) {
1152 targ->pq = pipe->create_query(pipe,
1153 NVA0_HW_QUERY_STREAM_OUTPUT_BUFFER_OFFSET, 0);
1154 if (!targ->pq) {
1155 FREE(targ);
1156 return NULL;
1157 }
1158 } else {
1159 targ->pq = NULL;
1160 }
1161 targ->clean = true;
1162
1163 targ->pipe.buffer_size = size;
1164 targ->pipe.buffer_offset = offset;
1165 targ->pipe.context = pipe;
1166 targ->pipe.buffer = NULL;
1167 pipe_resource_reference(&targ->pipe.buffer, res);
1168 pipe_reference_init(&targ->pipe.reference, 1);
1169
1170 assert(buf->base.target == PIPE_BUFFER);
1171 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1172
1173 return &targ->pipe;
1174 }
1175
1176 static void
nva0_so_target_save_offset(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg,unsigned index,bool serialize)1177 nva0_so_target_save_offset(struct pipe_context *pipe,
1178 struct pipe_stream_output_target *ptarg,
1179 unsigned index, bool serialize)
1180 {
1181 struct nv50_so_target *targ = nv50_so_target(ptarg);
1182
1183 if (serialize) {
1184 struct nouveau_pushbuf *push = nv50_context(pipe)->base.pushbuf;
1185 PUSH_SPACE(push, 2);
1186 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
1187 PUSH_DATA (push, 0);
1188 }
1189
1190 nv50_query(targ->pq)->index = index;
1191 pipe->end_query(pipe, targ->pq);
1192 }
1193
1194 static void
nv50_so_target_destroy(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg)1195 nv50_so_target_destroy(struct pipe_context *pipe,
1196 struct pipe_stream_output_target *ptarg)
1197 {
1198 struct nv50_so_target *targ = nv50_so_target(ptarg);
1199 if (targ->pq)
1200 pipe->destroy_query(pipe, targ->pq);
1201 pipe_resource_reference(&targ->pipe.buffer, NULL);
1202 FREE(targ);
1203 }
1204
1205 static void
nv50_set_stream_output_targets(struct pipe_context * pipe,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)1206 nv50_set_stream_output_targets(struct pipe_context *pipe,
1207 unsigned num_targets,
1208 struct pipe_stream_output_target **targets,
1209 const unsigned *offsets)
1210 {
1211 struct nv50_context *nv50 = nv50_context(pipe);
1212 unsigned i;
1213 bool serialize = true;
1214 const bool can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS;
1215
1216 assert(num_targets <= 4);
1217
1218 for (i = 0; i < num_targets; ++i) {
1219 const bool changed = nv50->so_target[i] != targets[i];
1220 const bool append = (offsets[i] == (unsigned)-1);
1221 if (!changed && append)
1222 continue;
1223 nv50->so_targets_dirty |= 1 << i;
1224
1225 if (can_resume && changed && nv50->so_target[i]) {
1226 nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1227 serialize = false;
1228 }
1229
1230 if (targets[i] && !append) {
1231 nv50_so_target(targets[i])->clean = true;
1232 nv50->so_used[i] = 0;
1233 }
1234
1235 pipe_so_target_reference(&nv50->so_target[i], targets[i]);
1236 }
1237 for (; i < nv50->num_so_targets; ++i) {
1238 if (can_resume && nv50->so_target[i]) {
1239 nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1240 serialize = false;
1241 }
1242 pipe_so_target_reference(&nv50->so_target[i], NULL);
1243 nv50->so_targets_dirty |= 1 << i;
1244 }
1245 nv50->num_so_targets = num_targets;
1246
1247 if (nv50->so_targets_dirty) {
1248 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_SO);
1249 nv50->dirty_3d |= NV50_NEW_3D_STRMOUT;
1250 }
1251 }
1252
1253 static bool
nv50_bind_images_range(struct nv50_context * nv50,unsigned start,unsigned nr,const struct pipe_image_view * pimages)1254 nv50_bind_images_range(struct nv50_context *nv50,
1255 unsigned start, unsigned nr,
1256 const struct pipe_image_view *pimages)
1257 {
1258 const unsigned end = start + nr;
1259 unsigned mask = 0;
1260 unsigned i;
1261
1262 if (pimages) {
1263 for (i = start; i < end; ++i) {
1264 struct pipe_image_view *img = &nv50->images[i];
1265 const unsigned p = i - start;
1266
1267 if (img->resource == pimages[p].resource &&
1268 img->format == pimages[p].format &&
1269 img->access == pimages[p].access) {
1270 if (img->resource == NULL)
1271 continue;
1272 if (img->resource->target == PIPE_BUFFER &&
1273 img->u.buf.offset == pimages[p].u.buf.offset &&
1274 img->u.buf.size == pimages[p].u.buf.size)
1275 continue;
1276 if (img->resource->target != PIPE_BUFFER &&
1277 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1278 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1279 img->u.tex.level == pimages[p].u.tex.level)
1280 continue;
1281 }
1282
1283 mask |= (1 << i);
1284 if (pimages[p].resource)
1285 nv50->images_valid |= (1 << i);
1286 else
1287 nv50->images_valid &= ~(1 << i);
1288
1289 img->format = pimages[p].format;
1290 img->access = pimages[p].access;
1291 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1292 img->u.buf = pimages[p].u.buf;
1293 else
1294 img->u.tex = pimages[p].u.tex;
1295
1296 pipe_resource_reference(
1297 &img->resource, pimages[p].resource);
1298 }
1299 if (!mask)
1300 return false;
1301 } else {
1302 mask = ((1 << nr) - 1) << start;
1303 if (!(nv50->images_valid & mask))
1304 return false;
1305 for (i = start; i < end; ++i) {
1306 pipe_resource_reference(&nv50->images[i].resource, NULL);
1307 }
1308 nv50->images_valid &= ~mask;
1309 }
1310 nv50->images_dirty |= mask;
1311
1312 nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_SUF);
1313
1314 return true;
1315 }
1316
1317 static void
nv50_set_shader_images(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,const struct pipe_image_view * images)1318 nv50_set_shader_images(struct pipe_context *pipe,
1319 enum pipe_shader_type shader,
1320 unsigned start, unsigned nr,
1321 unsigned unbind_num_trailing_slots,
1322 const struct pipe_image_view *images)
1323 {
1324 const unsigned s = nv50_context_shader_stage(shader);
1325
1326 if (s != NV50_SHADER_STAGE_COMPUTE)
1327 return;
1328
1329 nv50_bind_images_range(nv50_context(pipe), start + nr,
1330 unbind_num_trailing_slots, NULL);
1331
1332 if (!nv50_bind_images_range(nv50_context(pipe), start, nr, images))
1333 return;
1334
1335 nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_SURFACES;
1336 }
1337
1338 static void
nv50_set_compute_resources(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_surface ** resources)1339 nv50_set_compute_resources(struct pipe_context *pipe,
1340 unsigned start, unsigned nr,
1341 struct pipe_surface **resources)
1342 {
1343 /* TODO: bind surfaces */
1344 }
1345
1346 static bool
nv50_bind_buffers_range(struct nv50_context * nv50,unsigned start,unsigned nr,const struct pipe_shader_buffer * pbuffers)1347 nv50_bind_buffers_range(struct nv50_context *nv50,
1348 unsigned start, unsigned nr,
1349 const struct pipe_shader_buffer *pbuffers)
1350 {
1351 const unsigned end = start + nr;
1352 unsigned mask = 0;
1353 unsigned i;
1354
1355 if (pbuffers) {
1356 for (i = start; i < end; ++i) {
1357 struct pipe_shader_buffer *buf = &nv50->buffers[i];
1358 const unsigned p = i - start;
1359 if (buf->buffer == pbuffers[p].buffer &&
1360 buf->buffer_offset == pbuffers[p].buffer_offset &&
1361 buf->buffer_size == pbuffers[p].buffer_size)
1362 continue;
1363
1364 mask |= (1 << i);
1365 if (pbuffers[p].buffer)
1366 nv50->buffers_valid |= (1 << i);
1367 else
1368 nv50->buffers_valid &= ~(1 << i);
1369 buf->buffer_offset = pbuffers[p].buffer_offset;
1370 buf->buffer_size = pbuffers[p].buffer_size;
1371 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1372 }
1373 if (!mask)
1374 return false;
1375 } else {
1376 mask = ((1 << nr) - 1) << start;
1377 if (!(nv50->buffers_valid & mask))
1378 return false;
1379 for (i = start; i < end; ++i)
1380 pipe_resource_reference(&nv50->buffers[i].buffer, NULL);
1381 nv50->buffers_valid &= ~mask;
1382 }
1383 nv50->buffers_dirty |= mask;
1384
1385 nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_BUF);
1386
1387 return true;
1388 }
1389
1390 static void
nv50_set_shader_buffers(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,const struct pipe_shader_buffer * buffers,unsigned writable_bitmask)1391 nv50_set_shader_buffers(struct pipe_context *pipe,
1392 enum pipe_shader_type shader,
1393 unsigned start, unsigned nr,
1394 const struct pipe_shader_buffer *buffers,
1395 unsigned writable_bitmask)
1396 {
1397 const unsigned s = nv50_context_shader_stage(shader);
1398
1399 if (s != NV50_SHADER_STAGE_COMPUTE)
1400 return;
1401
1402 if (!nv50_bind_buffers_range(nv50_context(pipe), start, nr, buffers))
1403 return;
1404
1405 nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_BUFFERS;
1406 }
1407
1408 static inline void
nv50_set_global_handle(uint32_t * phandle,struct pipe_resource * res)1409 nv50_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1410 {
1411 struct nv04_resource *buf = nv04_resource(res);
1412 if (buf) {
1413 uint64_t limit = (buf->address + buf->base.width0) - 1;
1414 if (limit < (1ULL << 32)) {
1415 *phandle = (uint32_t)buf->address;
1416 } else {
1417 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1418 "resource not contained within 32-bit address space !\n");
1419 *phandle = 0;
1420 }
1421 } else {
1422 *phandle = 0;
1423 }
1424 }
1425
1426 static void
nv50_set_global_bindings(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_resource ** resources,uint32_t ** handles)1427 nv50_set_global_bindings(struct pipe_context *pipe,
1428 unsigned start, unsigned nr,
1429 struct pipe_resource **resources,
1430 uint32_t **handles)
1431 {
1432 struct nv50_context *nv50 = nv50_context(pipe);
1433 struct pipe_resource **ptr;
1434 unsigned i;
1435 const unsigned end = start + nr;
1436
1437 if (nv50->global_residents.size < (end * sizeof(struct pipe_resource *))) {
1438 const unsigned old_size = nv50->global_residents.size;
1439 if (util_dynarray_resize(&nv50->global_residents, struct pipe_resource *, end)) {
1440 memset((uint8_t *)nv50->global_residents.data + old_size, 0,
1441 nv50->global_residents.size - old_size);
1442 } else {
1443 NOUVEAU_ERR("Could not resize global residents array\n");
1444 return;
1445 }
1446 }
1447
1448 if (resources) {
1449 ptr = util_dynarray_element(
1450 &nv50->global_residents, struct pipe_resource *, start);
1451 for (i = 0; i < nr; ++i) {
1452 pipe_resource_reference(&ptr[i], resources[i]);
1453 nv50_set_global_handle(handles[i], resources[i]);
1454 }
1455 } else {
1456 ptr = util_dynarray_element(
1457 &nv50->global_residents, struct pipe_resource *, start);
1458 for (i = 0; i < nr; ++i)
1459 pipe_resource_reference(&ptr[i], NULL);
1460 }
1461
1462 nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_GLOBAL);
1463
1464 nv50->dirty_cp |= NV50_NEW_CP_GLOBALS;
1465 }
1466
1467 void
nv50_init_state_functions(struct nv50_context * nv50)1468 nv50_init_state_functions(struct nv50_context *nv50)
1469 {
1470 struct pipe_context *pipe = &nv50->base.pipe;
1471
1472 pipe->create_blend_state = nv50_blend_state_create;
1473 pipe->bind_blend_state = nv50_blend_state_bind;
1474 pipe->delete_blend_state = nv50_blend_state_delete;
1475
1476 pipe->create_rasterizer_state = nv50_rasterizer_state_create;
1477 pipe->bind_rasterizer_state = nv50_rasterizer_state_bind;
1478 pipe->delete_rasterizer_state = nv50_rasterizer_state_delete;
1479
1480 pipe->create_depth_stencil_alpha_state = nv50_zsa_state_create;
1481 pipe->bind_depth_stencil_alpha_state = nv50_zsa_state_bind;
1482 pipe->delete_depth_stencil_alpha_state = nv50_zsa_state_delete;
1483
1484 pipe->create_sampler_state = nv50_sampler_state_create;
1485 pipe->delete_sampler_state = nv50_sampler_state_delete;
1486 pipe->bind_sampler_states = nv50_bind_sampler_states;
1487
1488 pipe->create_sampler_view = nv50_create_sampler_view;
1489 pipe->sampler_view_destroy = nv50_sampler_view_destroy;
1490 pipe->set_sampler_views = nv50_set_sampler_views;
1491
1492 pipe->create_vs_state = nv50_vp_state_create;
1493 pipe->create_fs_state = nv50_fp_state_create;
1494 pipe->create_gs_state = nv50_gp_state_create;
1495 pipe->create_compute_state = nv50_cp_state_create;
1496 pipe->bind_vs_state = nv50_vp_state_bind;
1497 pipe->bind_fs_state = nv50_fp_state_bind;
1498 pipe->bind_gs_state = nv50_gp_state_bind;
1499 pipe->bind_compute_state = nv50_cp_state_bind;
1500 pipe->delete_vs_state = nv50_sp_state_delete;
1501 pipe->delete_fs_state = nv50_sp_state_delete;
1502 pipe->delete_gs_state = nv50_sp_state_delete;
1503 pipe->delete_compute_state = nv50_sp_state_delete;
1504
1505 pipe->get_compute_state_info = nv50_get_compute_state_info;
1506
1507 pipe->set_blend_color = nv50_set_blend_color;
1508 pipe->set_stencil_ref = nv50_set_stencil_ref;
1509 pipe->set_clip_state = nv50_set_clip_state;
1510 pipe->set_sample_mask = nv50_set_sample_mask;
1511 pipe->set_min_samples = nv50_set_min_samples;
1512 pipe->set_constant_buffer = nv50_set_constant_buffer;
1513 pipe->set_framebuffer_state = nv50_set_framebuffer_state;
1514 pipe->set_polygon_stipple = nv50_set_polygon_stipple;
1515 pipe->set_scissor_states = nv50_set_scissor_states;
1516 pipe->set_viewport_states = nv50_set_viewport_states;
1517 pipe->set_window_rectangles = nv50_set_window_rectangles;
1518
1519 pipe->create_vertex_elements_state = nv50_vertex_state_create;
1520 pipe->delete_vertex_elements_state = nv50_vertex_state_delete;
1521 pipe->bind_vertex_elements_state = nv50_vertex_state_bind;
1522
1523 pipe->set_vertex_buffers = nv50_set_vertex_buffers;
1524
1525 pipe->create_stream_output_target = nv50_so_target_create;
1526 pipe->stream_output_target_destroy = nv50_so_target_destroy;
1527 pipe->set_stream_output_targets = nv50_set_stream_output_targets;
1528
1529 pipe->set_global_binding = nv50_set_global_bindings;
1530 pipe->set_compute_resources = nv50_set_compute_resources;
1531 pipe->set_shader_images = nv50_set_shader_images;
1532 pipe->set_shader_buffers = nv50_set_shader_buffers;
1533
1534 nv50->sample_mask = ~0;
1535 nv50->min_samples = 1;
1536 }
1537