1 /*
2 * Copyright (c) 2021-2022, Stephan Gerhold <[email protected]>
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 #include <drivers/delay_timer.h>
10 #include <lib/mmio.h>
11
12 #include "msm8916_pm.h"
13
14 #define CPU_PWR_CTL 0x4
15 #define APC_PWR_GATE_CTL 0x14
16
17 #define CPU_PWR_CTL_CLAMP BIT_32(0)
18 #define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1)
19 #define CPU_PWR_CTL_L1_RST_DIS BIT_32(2)
20 #define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3)
21 #define CPU_PWR_CTL_CORE_RST BIT_32(4)
22 #define CPU_PWR_CTL_COREPOR_RST BIT_32(5)
23 #define CPU_PWR_CTL_GATE_CLK BIT_32(6)
24 #define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7)
25
26 #define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
27 #define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24)
28
29 #define PWR_CTL_OVERRIDE 0xc
30 #define L2_PWR_CTL 0x14
31 #define L2_PWR_STATUS 0x18
32 #define CORE_CBCR 0x58
33
34 #define PWR_CTL_OVERRIDE_PRESETDBG BIT_32(22)
35
36 #define L2_PWR_CTL_L2_ARRAY_HS BIT_32(0)
37 #define L2_PWR_CTL_SCU_ARRAY_HS BIT_32(1)
38 #define L2_PWR_CTL_L2_RST_DIS BIT_32(2)
39 #define L2_PWR_CTL_L2_HS_CLAMP BIT_32(8)
40 #define L2_PWR_CTL_L2_HS_EN BIT_32(9)
41 #define L2_PWR_CTL_L2_HS_RST BIT_32(10)
42 #define L2_PWR_CTL_L2_SLEEP_STATE BIT_32(11)
43 #define L2_PWR_CTL_SYS_RESET BIT_32(12)
44 #define L2_PWR_CTL_L2_RET_SLP BIT_32(13)
45 #define L2_PWR_CTL_SCU_ARRAY_HS_CLAMP BIT_32(14)
46 #define L2_PWR_CTL_L2_ARRAY_HS_CLAMP BIT_32(15)
47 #define L2_PWR_CTL_L2_HS_CNT(cnt) ((cnt) << 16)
48 #define L2_PWR_CTL_PMIC_APC_ON BIT_32(28)
49
50 #define L2_PWR_STATUS_L2_HS_STS BIT_32(9)
51
52 #define CORE_CBCR_CLK_ENABLE BIT_32(0)
53 #define CORE_CBCR_HW_CTL BIT_32(1)
54
55 /* Boot a secondary CPU core for the first time. */
msm8916_cpu_boot(uintptr_t acs)56 void msm8916_cpu_boot(uintptr_t acs)
57 {
58 uint32_t pwr_ctl;
59
60 VERBOSE("PSCI: Powering on CPU @ 0x%08lx\n", acs);
61
62 pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP |
63 CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST;
64 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
65 dsb();
66
67 mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN |
68 APC_PWR_GATE_CTL_GHDS_CNT(16));
69 dsb();
70 udelay(2);
71
72 pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP;
73 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
74 dsb();
75
76 pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS;
77 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
78 dsb();
79 udelay(2);
80
81 pwr_ctl &= ~CPU_PWR_CTL_CLAMP;
82 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
83 dsb();
84 udelay(2);
85
86 pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST);
87 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
88 dsb();
89
90 pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP;
91 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
92 dsb();
93 }
94
95 /* Power on cluster L2 cache for the first time. */
msm8916_l2_boot(uintptr_t base)96 void msm8916_l2_boot(uintptr_t base)
97 {
98 uint32_t pwr_ctl, cbcr, ovr;
99
100 /* Skip if cluster L2 is already powered on */
101 if (mmio_read_32(base + L2_PWR_STATUS) & L2_PWR_STATUS_L2_HS_STS) {
102 VERBOSE("PSCI: L2 cache @ 0x%08lx is already powered on\n", base);
103 return;
104 }
105
106 VERBOSE("PSCI: Powering on L2 cache @ 0x%08lx\n", base);
107
108 pwr_ctl = L2_PWR_CTL_L2_HS_CLAMP | L2_PWR_CTL_L2_HS_EN |
109 L2_PWR_CTL_L2_HS_RST | L2_PWR_CTL_SYS_RESET |
110 L2_PWR_CTL_SCU_ARRAY_HS_CLAMP | L2_PWR_CTL_L2_ARRAY_HS_CLAMP |
111 L2_PWR_CTL_L2_HS_CNT(16);
112 mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
113
114 ovr = PWR_CTL_OVERRIDE_PRESETDBG;
115 mmio_write_32(base + PWR_CTL_OVERRIDE, ovr);
116 dsb();
117 udelay(2);
118
119 pwr_ctl &= ~(L2_PWR_CTL_SCU_ARRAY_HS_CLAMP |
120 L2_PWR_CTL_L2_ARRAY_HS_CLAMP);
121 mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
122
123 pwr_ctl |= (L2_PWR_CTL_L2_ARRAY_HS | L2_PWR_CTL_SCU_ARRAY_HS);
124 mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
125 dsb();
126 udelay(2);
127
128 cbcr = CORE_CBCR_CLK_ENABLE;
129 mmio_write_32(base + CORE_CBCR, cbcr);
130
131 pwr_ctl &= ~L2_PWR_CTL_L2_HS_CLAMP;
132 mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
133 dsb();
134 udelay(2);
135
136 ovr &= ~PWR_CTL_OVERRIDE_PRESETDBG;
137 mmio_write_32(base + PWR_CTL_OVERRIDE, ovr);
138
139 pwr_ctl &= ~(L2_PWR_CTL_L2_HS_RST | L2_PWR_CTL_SYS_RESET);
140 mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
141 dsb();
142 udelay(54);
143
144 pwr_ctl |= L2_PWR_CTL_PMIC_APC_ON;
145 mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
146
147 cbcr |= CORE_CBCR_HW_CTL;
148 mmio_write_32(base + CORE_CBCR, cbcr);
149 dsb();
150 }
151