1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* coreboot UEFI PEI wrapper */ 3 4 #ifndef PEI_DATA_H 5 #define PEI_DATA_H 6 7 #include <stdint.h> 8 9 typedef struct { 10 uint16_t mode; /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ 11 uint16_t hs_port_switch_mask; /* 4 bit mask, 1: switchable, 0: not switchable */ 12 uint16_t preboot_support; /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ 13 uint16_t xhci_streams; /* 0: Disable, 1: Enable */ 14 } pch_usb3_controller_settings; 15 16 typedef void (*tx_byte_func)(unsigned char byte); 17 #define PEI_VERSION 6 18 19 struct pei_data 20 { 21 uint32_t pei_version; 22 uint32_t mchbar; 23 uint32_t dmibar; 24 uint32_t epbar; 25 uint32_t pciexbar; 26 uint16_t smbusbar; 27 uint32_t wdbbar; 28 uint32_t wdbsize; 29 uint32_t hpet_address; 30 uint32_t rcba; 31 uint32_t pmbase; 32 uint32_t gpiobase; 33 uint32_t thermalbase; 34 uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ 35 uint32_t tseg_size; 36 uint8_t spd_addresses[4]; 37 uint8_t ts_addresses[4]; 38 int boot_mode; 39 int ec_present; 40 int gbe_enable; 41 /* 42 * 0 = leave channel enabled 43 * 1 = disable dimm 0 on channel 44 * 2 = disable dimm 1 on channel 45 * 3 = disable dimm 0+1 on channel 46 */ 47 int dimm_channel0_disabled; 48 int dimm_channel1_disabled; 49 /* Seed values saved in CMOS */ 50 uint32_t scrambler_seed; 51 uint32_t scrambler_seed_s3; 52 /* Data read from flash and passed into MRC */ 53 uint32_t mrc_input_ptr; 54 unsigned int mrc_input_len; 55 /* Data from MRC that should be saved to flash */ 56 uint32_t mrc_output_ptr; 57 unsigned int mrc_output_len; 58 /* 59 * Max frequency DDR3 could be ran at. Could be one of four values: 60 * 800, 1067, 1333, 1600 61 */ 62 uint32_t max_ddr3_freq; 63 /* 64 * USB Port Configuration: 65 * [0] = enable 66 * [1] = overcurrent pin 67 * [2] = length 68 * 69 * Ports 0-7 can be mapped to OC0-OC3 70 * Ports 8-13 can be mapped to OC4-OC7 71 * 72 * Port Length 73 * MOBILE: 74 * < 0x050 = Setting 1 (back panel, 1 to 5 in, lowest tx amplitude) 75 * < 0x140 = Setting 2 (back panel, 5 to 14 in, highest tx amplitude) 76 * DESKTOP: 77 * < 0x080 = Setting 1 (front/back panel, less than 8 in, lowest tx amplitude) 78 * < 0x130 = Setting 2 (back panel, 8 to 13 in, higher tx amplitude) 79 * < 0x150 = Setting 3 (back panel, 13 to 15 in, highest tx amplitude) 80 */ 81 uint16_t usb_port_config[16][3]; 82 /* See the usb3 struct above for details */ 83 pch_usb3_controller_settings usb3; 84 /* 85 * SPD data array for onboard RAM. Note that spd_data [1..3] are ignored: instead, 86 * the "dimm_channel{0,1}_disabled" flag and the spd_addresses are used to determine 87 * which DIMMs should use the SPD from spd_data[0]. 88 */ 89 uint8_t spd_data[4][256]; 90 /* 32 bit pointer to tx_byte_func */ 91 uint32_t tx_byte_ptr; 92 93 int ddr3lv_support; 94 /* 95 * pcie_init needs to be set to 1 to have the system agent initialize PCIe. 96 * Note: This should only be required if your system has Gen3 devices and 97 * it will increase your boot time by at least 100ms. 98 */ 99 int pcie_init; 100 /* 101 * N mode functionality. Leave this setting at 0. 102 * 103 * 0: Auto 104 * 1: 1N 105 * 2: 2N 106 */ 107 int nmode; 108 /* 109 * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to 110 * specify whether double-rate is required for extended operating temperature range. 111 * 112 * 0: Enable double rate based upon temperature thresholds 113 * 1: Normal rate 114 * 2: Always enable double rate 115 */ 116 int ddr_refresh_rate_config; 117 } __packed; 118 119 void southbridge_fill_pei_data(struct pei_data *pei_data); 120 #endif 121