1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3
4 #include "dr_ste_v1.h"
5 #include "dr_ste_v2.h"
6
dr_ste_v3_set_encap(u8 * hw_ste_p,u8 * d_action,u32 reformat_id,int size)7 static void dr_ste_v3_set_encap(u8 *hw_ste_p, u8 *d_action,
8 u32 reformat_id, int size)
9 {
10 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, action_id,
11 DR_STE_V1_ACTION_ID_INSERT_POINTER);
12 /* The hardware expects here size in words (2 byte) */
13 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, size, size / 2);
14 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, pointer, reformat_id);
15 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, attributes,
16 DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
17 dr_ste_v1_set_reparse(hw_ste_p);
18 }
19
dr_ste_v3_set_push_vlan(u8 * ste,u8 * d_action,u32 vlan_hdr)20 static void dr_ste_v3_set_push_vlan(u8 *ste, u8 *d_action,
21 u32 vlan_hdr)
22 {
23 MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, action_id,
24 DR_STE_V1_ACTION_ID_INSERT_INLINE);
25 /* The hardware expects here offset to vlan header in words (2 byte) */
26 MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, start_offset,
27 HDR_LEN_L2_MACS >> 1);
28 MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, inline_data, vlan_hdr);
29 dr_ste_v1_set_reparse(ste);
30 }
31
dr_ste_v3_set_pop_vlan(u8 * hw_ste_p,u8 * s_action,u8 vlans_num)32 static void dr_ste_v3_set_pop_vlan(u8 *hw_ste_p, u8 *s_action,
33 u8 vlans_num)
34 {
35 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
36 action_id, DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
37 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
38 start_anchor, DR_STE_HEADER_ANCHOR_1ST_VLAN);
39 /* The hardware expects here size in words (2 byte) */
40 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
41 remove_size, (HDR_LEN_L2_VLAN >> 1) * vlans_num);
42
43 dr_ste_v1_set_reparse(hw_ste_p);
44 }
45
dr_ste_v3_set_encap_l3(u8 * hw_ste_p,u8 * frst_s_action,u8 * scnd_d_action,u32 reformat_id,int size)46 static void dr_ste_v3_set_encap_l3(u8 *hw_ste_p,
47 u8 *frst_s_action,
48 u8 *scnd_d_action,
49 u32 reformat_id,
50 int size)
51 {
52 /* Remove L2 headers */
53 MLX5_SET(ste_single_action_remove_header_v3, frst_s_action, action_id,
54 DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
55 MLX5_SET(ste_single_action_remove_header_v3, frst_s_action, end_anchor,
56 DR_STE_HEADER_ANCHOR_IPV6_IPV4);
57
58 /* Encapsulate with given reformat ID */
59 MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, action_id,
60 DR_STE_V1_ACTION_ID_INSERT_POINTER);
61 /* The hardware expects here size in words (2 byte) */
62 MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, size, size / 2);
63 MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, pointer, reformat_id);
64 MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, attributes,
65 DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
66
67 dr_ste_v1_set_reparse(hw_ste_p);
68 }
69
dr_ste_v3_set_rx_decap(u8 * hw_ste_p,u8 * s_action)70 static void dr_ste_v3_set_rx_decap(u8 *hw_ste_p, u8 *s_action)
71 {
72 MLX5_SET(ste_single_action_remove_header_v3, s_action, action_id,
73 DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
74 MLX5_SET(ste_single_action_remove_header_v3, s_action, decap, 1);
75 MLX5_SET(ste_single_action_remove_header_v3, s_action, vni_to_cqe, 1);
76 MLX5_SET(ste_single_action_remove_header_v3, s_action, end_anchor,
77 DR_STE_HEADER_ANCHOR_INNER_MAC);
78
79 dr_ste_v1_set_reparse(hw_ste_p);
80 }
81
dr_ste_v3_set_insert_hdr(u8 * hw_ste_p,u8 * d_action,u32 reformat_id,u8 anchor,u8 offset,int size)82 static void dr_ste_v3_set_insert_hdr(u8 *hw_ste_p, u8 *d_action,
83 u32 reformat_id, u8 anchor,
84 u8 offset, int size)
85 {
86 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
87 action_id, DR_STE_V1_ACTION_ID_INSERT_POINTER);
88 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
89 start_anchor, anchor);
90
91 /* The hardware expects here size and offset in words (2 byte) */
92 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
93 size, size / 2);
94 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
95 start_offset, offset / 2);
96
97 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
98 pointer, reformat_id);
99 MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
100 attributes, DR_STE_V1_ACTION_INSERT_PTR_ATTR_NONE);
101
102 dr_ste_v1_set_reparse(hw_ste_p);
103 }
104
dr_ste_v3_set_remove_hdr(u8 * hw_ste_p,u8 * s_action,u8 anchor,u8 offset,int size)105 static void dr_ste_v3_set_remove_hdr(u8 *hw_ste_p, u8 *s_action,
106 u8 anchor, u8 offset, int size)
107 {
108 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
109 action_id, DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
110 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
111 start_anchor, anchor);
112
113 /* The hardware expects here size and offset in words (2 byte) */
114 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
115 remove_size, size / 2);
116 MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
117 start_offset, offset / 2);
118
119 dr_ste_v1_set_reparse(hw_ste_p);
120 }
121
122 static int
dr_ste_v3_set_action_decap_l3_list(void * data,u32 data_sz,u8 * hw_action,u32 hw_action_sz,uint16_t * used_hw_action_num)123 dr_ste_v3_set_action_decap_l3_list(void *data, u32 data_sz,
124 u8 *hw_action, u32 hw_action_sz,
125 uint16_t *used_hw_action_num)
126 {
127 u8 padded_data[DR_STE_L2_HDR_MAX_SZ] = {};
128 void *data_ptr = padded_data;
129 u16 used_actions = 0;
130 u32 inline_data_sz;
131 u32 i;
132
133 if (hw_action_sz / DR_STE_ACTION_DOUBLE_SZ < DR_STE_DECAP_L3_ACTION_NUM)
134 return -EINVAL;
135
136 inline_data_sz =
137 MLX5_FLD_SZ_BYTES(ste_double_action_insert_with_inline_v3, inline_data);
138
139 /* Add an alignment padding */
140 memcpy(padded_data + data_sz % inline_data_sz, data, data_sz);
141
142 /* Remove L2L3 outer headers */
143 MLX5_SET(ste_single_action_remove_header_v3, hw_action, action_id,
144 DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
145 MLX5_SET(ste_single_action_remove_header_v3, hw_action, decap, 1);
146 MLX5_SET(ste_single_action_remove_header_v3, hw_action, vni_to_cqe, 1);
147 MLX5_SET(ste_single_action_remove_header_v3, hw_action, end_anchor,
148 DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4);
149 hw_action += DR_STE_ACTION_DOUBLE_SZ;
150 used_actions++; /* Remove and NOP are a single double action */
151
152 /* Point to the last dword of the header */
153 data_ptr += (data_sz / inline_data_sz) * inline_data_sz;
154
155 /* Add the new header using inline action 4Byte at a time, the header
156 * is added in reversed order to the beginning of the packet to avoid
157 * incorrect parsing by the HW. Since header is 14B or 18B an extra
158 * two bytes are padded and later removed.
159 */
160 for (i = 0; i < data_sz / inline_data_sz + 1; i++) {
161 void *addr_inline;
162
163 MLX5_SET(ste_double_action_insert_with_inline_v3, hw_action, action_id,
164 DR_STE_V1_ACTION_ID_INSERT_INLINE);
165 /* The hardware expects here offset to words (2 bytes) */
166 MLX5_SET(ste_double_action_insert_with_inline_v3, hw_action, start_offset, 0);
167
168 /* Copy bytes one by one to avoid endianness problem */
169 addr_inline = MLX5_ADDR_OF(ste_double_action_insert_with_inline_v3,
170 hw_action, inline_data);
171 memcpy(addr_inline, data_ptr - i * inline_data_sz, inline_data_sz);
172 hw_action += DR_STE_ACTION_DOUBLE_SZ;
173 used_actions++;
174 }
175
176 /* Remove first 2 extra bytes */
177 MLX5_SET(ste_single_action_remove_header_size_v3, hw_action, action_id,
178 DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
179 MLX5_SET(ste_single_action_remove_header_size_v3, hw_action, start_offset, 0);
180 /* The hardware expects here size in words (2 bytes) */
181 MLX5_SET(ste_single_action_remove_header_size_v3, hw_action, remove_size, 1);
182 used_actions++;
183
184 *used_hw_action_num = used_actions;
185
186 return 0;
187 }
188
189 static struct mlx5dr_ste_ctx ste_ctx_v3 = {
190 /* Builders */
191 .build_eth_l2_src_dst_init = &dr_ste_v1_build_eth_l2_src_dst_init,
192 .build_eth_l3_ipv6_src_init = &dr_ste_v1_build_eth_l3_ipv6_src_init,
193 .build_eth_l3_ipv6_dst_init = &dr_ste_v1_build_eth_l3_ipv6_dst_init,
194 .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init,
195 .build_eth_l2_src_init = &dr_ste_v1_build_eth_l2_src_init,
196 .build_eth_l2_dst_init = &dr_ste_v1_build_eth_l2_dst_init,
197 .build_eth_l2_tnl_init = &dr_ste_v1_build_eth_l2_tnl_init,
198 .build_eth_l3_ipv4_misc_init = &dr_ste_v1_build_eth_l3_ipv4_misc_init,
199 .build_eth_ipv6_l3_l4_init = &dr_ste_v1_build_eth_ipv6_l3_l4_init,
200 .build_mpls_init = &dr_ste_v1_build_mpls_init,
201 .build_tnl_gre_init = &dr_ste_v1_build_tnl_gre_init,
202 .build_tnl_mpls_init = &dr_ste_v1_build_tnl_mpls_init,
203 .build_tnl_mpls_over_udp_init = &dr_ste_v1_build_tnl_mpls_over_udp_init,
204 .build_tnl_mpls_over_gre_init = &dr_ste_v1_build_tnl_mpls_over_gre_init,
205 .build_icmp_init = &dr_ste_v1_build_icmp_init,
206 .build_general_purpose_init = &dr_ste_v1_build_general_purpose_init,
207 .build_eth_l4_misc_init = &dr_ste_v1_build_eth_l4_misc_init,
208 .build_tnl_vxlan_gpe_init = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,
209 .build_tnl_geneve_init = &dr_ste_v1_build_flex_parser_tnl_geneve_init,
210 .build_tnl_geneve_tlv_opt_init = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init,
211 .build_tnl_geneve_tlv_opt_exist_init =
212 &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init,
213 .build_register_0_init = &dr_ste_v1_build_register_0_init,
214 .build_register_1_init = &dr_ste_v1_build_register_1_init,
215 .build_src_gvmi_qpn_init = &dr_ste_v1_build_src_gvmi_qpn_init,
216 .build_flex_parser_0_init = &dr_ste_v1_build_flex_parser_0_init,
217 .build_flex_parser_1_init = &dr_ste_v1_build_flex_parser_1_init,
218 .build_tnl_gtpu_init = &dr_ste_v1_build_flex_parser_tnl_gtpu_init,
219 .build_tnl_header_0_1_init = &dr_ste_v1_build_tnl_header_0_1_init,
220 .build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init,
221 .build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init,
222
223 /* Getters and Setters */
224 .ste_init = &dr_ste_v1_init,
225 .set_next_lu_type = &dr_ste_v1_set_next_lu_type,
226 .get_next_lu_type = &dr_ste_v1_get_next_lu_type,
227 .is_miss_addr_set = &dr_ste_v1_is_miss_addr_set,
228 .set_miss_addr = &dr_ste_v1_set_miss_addr,
229 .get_miss_addr = &dr_ste_v1_get_miss_addr,
230 .set_hit_addr = &dr_ste_v1_set_hit_addr,
231 .set_byte_mask = &dr_ste_v1_set_byte_mask,
232 .get_byte_mask = &dr_ste_v1_get_byte_mask,
233
234 /* Actions */
235 .actions_caps = DR_STE_CTX_ACTION_CAP_TX_POP |
236 DR_STE_CTX_ACTION_CAP_RX_PUSH |
237 DR_STE_CTX_ACTION_CAP_RX_ENCAP,
238 .set_actions_rx = &dr_ste_v1_set_actions_rx,
239 .set_actions_tx = &dr_ste_v1_set_actions_tx,
240 .modify_field_arr_sz = ARRAY_SIZE(dr_ste_v2_action_modify_field_arr),
241 .modify_field_arr = dr_ste_v2_action_modify_field_arr,
242 .set_action_set = &dr_ste_v1_set_action_set,
243 .set_action_add = &dr_ste_v1_set_action_add,
244 .set_action_copy = &dr_ste_v1_set_action_copy,
245 .set_action_decap_l3_list = &dr_ste_v3_set_action_decap_l3_list,
246 .alloc_modify_hdr_chunk = &dr_ste_v1_alloc_modify_hdr_ptrn_arg,
247 .dealloc_modify_hdr_chunk = &dr_ste_v1_free_modify_hdr_ptrn_arg,
248 /* Actions bit set */
249 .set_encap = &dr_ste_v3_set_encap,
250 .set_push_vlan = &dr_ste_v3_set_push_vlan,
251 .set_pop_vlan = &dr_ste_v3_set_pop_vlan,
252 .set_rx_decap = &dr_ste_v3_set_rx_decap,
253 .set_encap_l3 = &dr_ste_v3_set_encap_l3,
254 .set_insert_hdr = &dr_ste_v3_set_insert_hdr,
255 .set_remove_hdr = &dr_ste_v3_set_remove_hdr,
256 /* Send */
257 .prepare_for_postsend = &dr_ste_v1_prepare_for_postsend,
258 };
259
mlx5dr_ste_get_ctx_v3(void)260 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v3(void)
261 {
262 return &ste_ctx_v3;
263 }
264