1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3
4 #include "dr_ste_v1.h"
5 #include "dr_ste_v2.h"
6
7 static struct mlx5dr_ste_ctx ste_ctx_v2 = {
8 /* Builders */
9 .build_eth_l2_src_dst_init = &dr_ste_v1_build_eth_l2_src_dst_init,
10 .build_eth_l3_ipv6_src_init = &dr_ste_v1_build_eth_l3_ipv6_src_init,
11 .build_eth_l3_ipv6_dst_init = &dr_ste_v1_build_eth_l3_ipv6_dst_init,
12 .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init,
13 .build_eth_l2_src_init = &dr_ste_v1_build_eth_l2_src_init,
14 .build_eth_l2_dst_init = &dr_ste_v1_build_eth_l2_dst_init,
15 .build_eth_l2_tnl_init = &dr_ste_v1_build_eth_l2_tnl_init,
16 .build_eth_l3_ipv4_misc_init = &dr_ste_v1_build_eth_l3_ipv4_misc_init,
17 .build_eth_ipv6_l3_l4_init = &dr_ste_v1_build_eth_ipv6_l3_l4_init,
18 .build_mpls_init = &dr_ste_v1_build_mpls_init,
19 .build_tnl_gre_init = &dr_ste_v1_build_tnl_gre_init,
20 .build_tnl_mpls_init = &dr_ste_v1_build_tnl_mpls_init,
21 .build_tnl_mpls_over_udp_init = &dr_ste_v1_build_tnl_mpls_over_udp_init,
22 .build_tnl_mpls_over_gre_init = &dr_ste_v1_build_tnl_mpls_over_gre_init,
23 .build_icmp_init = &dr_ste_v1_build_icmp_init,
24 .build_general_purpose_init = &dr_ste_v1_build_general_purpose_init,
25 .build_eth_l4_misc_init = &dr_ste_v1_build_eth_l4_misc_init,
26 .build_tnl_vxlan_gpe_init = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,
27 .build_tnl_geneve_init = &dr_ste_v1_build_flex_parser_tnl_geneve_init,
28 .build_tnl_geneve_tlv_opt_init = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init,
29 .build_tnl_geneve_tlv_opt_exist_init =
30 &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init,
31 .build_register_0_init = &dr_ste_v1_build_register_0_init,
32 .build_register_1_init = &dr_ste_v1_build_register_1_init,
33 .build_src_gvmi_qpn_init = &dr_ste_v1_build_src_gvmi_qpn_init,
34 .build_flex_parser_0_init = &dr_ste_v1_build_flex_parser_0_init,
35 .build_flex_parser_1_init = &dr_ste_v1_build_flex_parser_1_init,
36 .build_tnl_gtpu_init = &dr_ste_v1_build_flex_parser_tnl_gtpu_init,
37 .build_tnl_header_0_1_init = &dr_ste_v1_build_tnl_header_0_1_init,
38 .build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init,
39 .build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init,
40
41 /* Getters and Setters */
42 .ste_init = &dr_ste_v1_init,
43 .set_next_lu_type = &dr_ste_v1_set_next_lu_type,
44 .get_next_lu_type = &dr_ste_v1_get_next_lu_type,
45 .is_miss_addr_set = &dr_ste_v1_is_miss_addr_set,
46 .set_miss_addr = &dr_ste_v1_set_miss_addr,
47 .get_miss_addr = &dr_ste_v1_get_miss_addr,
48 .set_hit_addr = &dr_ste_v1_set_hit_addr,
49 .set_byte_mask = &dr_ste_v1_set_byte_mask,
50 .get_byte_mask = &dr_ste_v1_get_byte_mask,
51
52 /* Actions */
53 .actions_caps = DR_STE_CTX_ACTION_CAP_TX_POP |
54 DR_STE_CTX_ACTION_CAP_RX_PUSH |
55 DR_STE_CTX_ACTION_CAP_RX_ENCAP,
56 .set_actions_rx = &dr_ste_v1_set_actions_rx,
57 .set_actions_tx = &dr_ste_v1_set_actions_tx,
58 .modify_field_arr_sz = ARRAY_SIZE(dr_ste_v2_action_modify_field_arr),
59 .modify_field_arr = dr_ste_v2_action_modify_field_arr,
60 .set_action_set = &dr_ste_v1_set_action_set,
61 .set_action_add = &dr_ste_v1_set_action_add,
62 .set_action_copy = &dr_ste_v1_set_action_copy,
63 .set_action_decap_l3_list = &dr_ste_v1_set_action_decap_l3_list,
64 .alloc_modify_hdr_chunk = &dr_ste_v1_alloc_modify_hdr_ptrn_arg,
65 .dealloc_modify_hdr_chunk = &dr_ste_v1_free_modify_hdr_ptrn_arg,
66 /* Actions bit set */
67 .set_encap = &dr_ste_v1_set_encap,
68 .set_push_vlan = &dr_ste_v1_set_push_vlan,
69 .set_pop_vlan = &dr_ste_v1_set_pop_vlan,
70 .set_rx_decap = &dr_ste_v1_set_rx_decap,
71 .set_encap_l3 = &dr_ste_v1_set_encap_l3,
72 .set_insert_hdr = &dr_ste_v1_set_insert_hdr,
73 .set_remove_hdr = &dr_ste_v1_set_remove_hdr,
74 /* Send */
75 .prepare_for_postsend = &dr_ste_v1_prepare_for_postsend,
76 };
77
mlx5dr_ste_get_ctx_v2(void)78 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v2(void)
79 {
80 return &ste_ctx_v2;
81 }
82