1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file cm_hal_g8.h 24 //! \brief Common HAL CM Gen8 functions 25 //! 26 27 #ifndef __CM_HAL_G8_H__ 28 #define __CM_HAL_G8_H__ 29 30 #include "mos_os.h" 31 #include "renderhal_legacy.h" 32 #include "cm_def.h" 33 #include "cm_hal.h" 34 #include "mhw_vebox_hwcmd_g8_X.h" 35 #include "mhw_render_hwcmd_g8_X.h" 36 #include "mhw_mmio_g8.h" 37 38 #define CM_NUM_HW_POLYPHASE_TABLES_G8 17 39 40 #define CM_MAX_THREADSPACE_WIDTH_FOR_MW 511 41 #define CM_MAX_THREADSPACE_HEIGHT_FOR_MW 511 42 43 #define CM_BDW_L3_CONFIG_NUM 8 44 #define CM_NUM_CONVOLVE_ROWS_BDW 16 45 46 static const L3_CONFIG BDW_L3[CM_BDW_L3_CONFIG_NUM] = 47 { //8k unit 48 {0, 48, 48, 0, 0, 0, 0, 0, 96}, 49 {0, 48, 0, 16, 32, 0, 0, 0, 96}, 50 {0, 32, 0, 16, 48, 0, 0, 0, 96}, 51 {0, 32, 0, 0, 64, 0, 0, 0, 96}, 52 {0, 32, 64, 0, 0, 0, 0, 0, 96}, 53 {32, 16, 48, 0, 0, 0, 0, 0, 96}, 54 {32, 16, 0, 16, 32, 0, 0, 0, 96}, 55 {32, 16, 0, 32, 16, 0, 0, 0, 96} 56 }; 57 static const L3ConfigRegisterValues BDW_L3_PLANE[CM_BDW_L3_CONFIG_NUM] = 58 { // SLM URB Rest DC RO I/S C T Sum ( BDW GT2; for GT1, half of the values; for GT3, double the values ) 59 { 0, 0, 0, 0x60000060 }, //{ 0, 384, 384, 0, 0, 0, 0, 0, 768}, 60 { 0, 0, 0, 0x00410060 }, //{ 0, 384, 0, 128, 256, 0, 0, 0, 768}, 61 { 0, 0, 0, 0x00418040 }, //{ 0, 256, 0, 128, 384, 0, 0, 0, 768}, 62 { 0, 0, 0, 0x00020040 }, //{ 0, 256, 0, 0, 512, 0, 0, 0, 768}, 63 { 0, 0, 0, 0x80000040 }, //{ 0, 256, 512, 0, 0, 0, 0, 0, 768}, 64 { 0, 0, 0, 0x60000021 }, //{192, 128, 384, 0, 0, 0, 0, 0, 768}, 65 { 0, 0, 0, 0x00410021 }, //{192, 128, 0, 128, 256, 0, 0, 0, 768}, 66 { 0, 0, 0, 0x00808021 } //{192, 128, 0, 256, 128, 0, 0, 0, 768} 67 }; 68 69 70 71 //! \brief for BDW GT2 WA 72 //! SLM URB Rest DC RO I/S C T 73 //! { 256, 128, 384, 0, 0, 0, 0, 0, } 74 #define CM_L3_CACHE_CONFIG_CNTLREG_VALUE_ALLOCATE_SLM_E0F0_WA_G8 (0x60000021) 75 76 #define CM_RENDER_ENGINE_REG_L3_CACHE_SQCREG1_G8 0xB100 77 #define CM_RENDER_ENGINE_REG_L3_CACHE_CNTLREG_G8 0x7034 78 79 #define CM_PREMP_DBG_ADDRESS_OFFSET (0x2248) 80 #define CM_PREMP_DEFAULT_VALUE (0x00000000) 81 #define CM_PREMP_ON_MI_ARB_CHECK_ONLY (0x00000100) // Bit "8" of the Register needs to be set 82 83 typedef struct _MEDIA_OBJECT_WALKER_CMD_G6 84 { 85 // DWORD 0 86 union 87 { 88 struct 89 { 90 uint32_t length : 16; // OP_LENGTH 91 uint32_t instructionSubOpcode : 8; // 3h 92 uint32_t instructionOpcode : 3; // 1h 93 uint32_t instructionPipeline : 2; // 2h 94 uint32_t instructionType : 3; // 3h 95 }; 96 struct 97 { 98 uint32_t value; 99 }; 100 } DW0; 101 102 // DWORD 1 103 union 104 { 105 struct 106 { 107 uint32_t interfaceDescriptorOffset : 6; // 5 bits PreHSW, 6 bits HSW+ 108 uint32_t : 2; 109 uint32_t objectID : 24; 110 }; 111 struct 112 { 113 uint32_t value; 114 }; 115 } DW1; 116 117 // DWORD 2 118 union 119 { 120 struct 121 { 122 uint32_t indirectDataLength : 17; // U17 in bytes 123 uint32_t : 4; 124 uint32_t useScoreboard : 1; 125 uint32_t : 2; 126 uint32_t threadSynchronization : 1; // bool 127 uint32_t : 6; 128 uint32_t childrenPresent : 1; // bool 129 }; 130 struct 131 { 132 uint32_t value; 133 }; 134 } DW2; 135 136 // DWORD 3 137 union 138 { 139 struct 140 { 141 uint32_t indirectDataStartAddress; // GTT [31:0] [0-512MB] Bits 31:29 MBZ 142 }; 143 struct 144 { 145 uint32_t value; 146 }; 147 } DW3; 148 149 // DWORD 4 150 union 151 { 152 struct 153 { 154 uint32_t reserved : 32; 155 }; 156 struct 157 { 158 uint32_t value; 159 }; 160 } DW4; 161 162 // DWORD 5 163 union 164 { 165 struct 166 { 167 uint32_t scoreboardMask : 8; // Scoreboard Mask 168 uint32_t groupIdLoopSelect : 24; // Gen8+ 169 }; 170 struct 171 { 172 uint32_t value; 173 }; 174 } DW5; 175 176 // DWORD 6 177 union 178 { 179 struct 180 { 181 uint32_t : 8; 182 uint32_t midLoopUnitX : 2; 183 uint32_t : 2; 184 uint32_t midLoopUnitY : 2; 185 uint32_t : 2; 186 uint32_t midLoopExtraSteps : 5; // Middle Loop Extra Steps 187 uint32_t : 3; 188 uint32_t colorCountMinusOne : 4; // Color Count Minus One 189 uint32_t : 1; 190 uint32_t quadMode : 1; // Pre-Gen8. For products with 4 half-slices 191 uint32_t repel : 1; // Pre-Gen8 192 uint32_t dualMode : 1; // Pre-Gen8. For products with 2 half-slices 193 }; 194 struct 195 { 196 uint32_t value; 197 }; 198 } DW6; 199 200 // DWORD 7 201 union 202 { 203 struct 204 { 205 uint32_t localLoopExecCount : 10; 206 uint32_t : 6; 207 uint32_t globalLoopExecCount : 10; 208 uint32_t : 6; 209 }; 210 struct 211 { 212 uint32_t value; 213 }; 214 } DW7; 215 216 // DWORD 8 217 union 218 { 219 struct 220 { 221 uint32_t blockResolutionX : 9; 222 uint32_t : 7; 223 uint32_t blockResolutionY : 9; 224 uint32_t : 7; 225 }; 226 struct 227 { 228 uint32_t value; 229 }; 230 } DW8; 231 232 // DWORD 9 233 union 234 { 235 struct 236 { 237 uint32_t localStartX : 9; 238 uint32_t : 7; 239 uint32_t localStartY : 9; 240 uint32_t : 7; 241 }; 242 struct 243 { 244 uint32_t value; 245 }; 246 } DW9; 247 248 // DWORD 10 249 union 250 { 251 struct 252 { 253 uint32_t localEndX : 9; // Pre-Gen7.5. Reserved MBZ in Gen7.5+ 254 uint32_t : 7; 255 uint32_t localEndY : 9; // Pre-Gen7.5. Reserved MBZ in Gen7.5+ 256 uint32_t : 7; 257 }; 258 struct 259 { 260 uint32_t value; 261 }; 262 } DW10; 263 264 // DWORD 11 265 union 266 { 267 struct 268 { 269 uint32_t localOuterLoopStrideX : 10; 270 uint32_t : 6; 271 uint32_t localOuterLoopStrideY : 10; 272 uint32_t : 6; 273 }; 274 struct 275 { 276 uint32_t value; 277 }; 278 } DW11; 279 280 // DWORD 12 281 union 282 { 283 struct 284 { 285 uint32_t localInnerLoopUnitX : 10; 286 uint32_t : 6; 287 uint32_t localInnerLoopUnitY : 10; 288 uint32_t : 6; 289 }; 290 struct 291 { 292 uint32_t value; 293 }; 294 } DW12; 295 296 // DWORD 13 297 union 298 { 299 struct 300 { 301 uint32_t globalResolutionX : 9; 302 uint32_t : 7; 303 uint32_t globalResolutionY : 9; 304 uint32_t : 7; 305 }; 306 struct 307 { 308 uint32_t value; 309 }; 310 } DW13; 311 312 // DWORD 14 313 union 314 { 315 struct 316 { 317 uint32_t globalStartX : 10; 318 uint32_t : 6; 319 uint32_t globalStartY : 10; 320 uint32_t : 6; 321 }; 322 struct 323 { 324 uint32_t value; 325 }; 326 } DW14; 327 328 // DWORD 15 329 union 330 { 331 struct 332 { 333 uint32_t globalOuterLoopStrideX : 10; 334 uint32_t : 6; 335 uint32_t globalOuterLoopStrideY : 10; 336 uint32_t : 6; 337 }; 338 struct 339 { 340 uint32_t value; 341 }; 342 } DW15; 343 344 // DWORD 16 345 union 346 { 347 struct 348 { 349 uint32_t globalInnerLoopUnitX : 10; 350 uint32_t : 6; 351 uint32_t globalInnerLoopUnitY : 10; 352 uint32_t : 6; 353 }; 354 struct 355 { 356 uint32_t value; 357 }; 358 } DW16; 359 } MEDIA_OBJECT_WALKER_CMD_G6, *PMEDIA_OBJECT_WALKER_CMD_G6; 360 361 typedef struct _CM_VEBOX_STATE_G8 362 { 363 union 364 { 365 struct 366 { 367 uint32_t ColorGamutExpansionEnable : 1; 368 uint32_t ColorGamutCompressionEnable : 1; 369 uint32_t GlobalIECPEnable : 1; 370 uint32_t DNEnable : 1; 371 uint32_t DIEnable : 1; 372 uint32_t DNDIFirstFrame : 1; 373 uint32_t DownsampleMethod422to420 : 1; 374 uint32_t DownsampleMethod444to422 : 1; 375 uint32_t DIOutputFrames : 2; 376 uint32_t DemosaicEnable : 1; 377 uint32_t VignetteEnable : 1; 378 uint32_t AlphaPlaneEnable : 1; 379 uint32_t HotPixelFilteringEnable : 1; 380 uint32_t SingleSliceVeboxEnable : 1; 381 uint32_t: 11; // Reserved 382 uint32_t StateSurfaceControlBits : 6; 383 }; 384 struct 385 { 386 uint32_t Value; 387 }; 388 } DW0; 389 390 mhw_vebox_g8_X::VEBOX_GAMUT_STATE_CMD *pGamutState; 391 mhw_vebox_g8_X::VEBOX_VERTEX_TABLE_CMD *pVertexTable; 392 } CM_VEBOX_STATE_G8, *PCM_VEBOX_STATE_G8; 393 394 struct CM_HAL_G8_X:public CM_HAL_GENERIC 395 { 396 397 public: CM_HAL_G8_XCM_HAL_G8_X398 CM_HAL_G8_X(PCM_HAL_STATE cmState):CM_HAL_GENERIC(cmState){}; ~CM_HAL_G8_XCM_HAL_G8_X399 ~CM_HAL_G8_X(){}; 400 401 MOS_STATUS GetCopyKernelIsa(void *&isa, uint32_t &isaSize); 402 403 MOS_STATUS GetInitKernelIsa(void *&isa, uint32_t &isaSize); 404 405 MOS_STATUS SetMediaWalkerParams( 406 CM_WALKING_PARAMETERS engineeringParams, 407 PCM_HAL_WALKER_PARAMS walkerParams); 408 409 MOS_STATUS HwSetSurfaceMemoryObjectControl( 410 uint16_t memObjCtl, 411 PRENDERHAL_SURFACE_STATE_PARAMS surfStateParams); 412 413 MOS_STATUS RegisterSampler8x8( 414 PCM_HAL_SAMPLER_8X8_PARAM param); 415 416 MOS_STATUS SubmitCommands( 417 PMHW_BATCH_BUFFER batchBuffer, 418 int32_t taskId, 419 PCM_HAL_KERNEL_PARAM *kernelParam, 420 void **cmdBuffer); 421 422 #if (_RELEASE_INTERNAL || _DEBUG) 423 #if defined(CM_DIRECT_GUC_SUPPORT) 424 MOS_STATUS SubmitDummyCommands( 425 PMHW_BATCH_BUFFER batchBuffer, 426 int32_t taskId, 427 PCM_HAL_KERNEL_PARAM *kernelParam, 428 void **cmdBuffer); 429 #endif 430 #endif 431 MOS_STATUS UpdatePlatformInfoFromPower( 432 PCM_PLATFORM_INFO platformInfo, 433 bool euSaturated); 434 435 MOS_STATUS GetExpectedGtSystemConfig( 436 PCM_EXPECTED_GT_SYSTEM_INFO expectedConfig); 437 438 uint32_t GetMediaWalkerMaxThreadWidth(); 439 uint32_t GetMediaWalkerMaxThreadHeight(); 440 441 MOS_STATUS GetHwSurfaceBTIInfo( 442 PCM_SURFACE_BTI_INFO btiInfo); 443 444 MOS_STATUS SetSuggestedL3Conf( 445 L3_SUGGEST_CONFIG l3Config); 446 447 MOS_STATUS AllocateSIPCSRResource(); 448 449 MOS_STATUS GetGenStepInfo(char*& stepInfoStr); 450 IsSurf3DQpitchSupportedbyHwCM_HAL_G8_X451 bool IsSurf3DQpitchSupportedbyHw(){ return false;}; 452 IsCompareMaskSupportedbyHwCM_HAL_G8_X453 bool IsCompareMaskSupportedbyHw(){ return false;}; 454 IsAdjacentSamplerIndexRequiredbyHwCM_HAL_G8_X455 bool IsAdjacentSamplerIndexRequiredbyHw(){ return true;}; 456 IsSurfaceCompressionWARequiredCM_HAL_G8_X457 bool IsSurfaceCompressionWARequired(){ return false;}; 458 459 int32_t ColorCountSanityCheck(uint32_t colorCount); 460 461 bool MemoryObjectCtrlPolicyCheck(uint32_t memCtrl); 462 IsGPUCopySurfaceNoCacheWARequiredCM_HAL_G8_X463 bool IsGPUCopySurfaceNoCacheWARequired(){ return false;}; 464 IsP010SinglePassSupportedCM_HAL_G8_X465 bool IsP010SinglePassSupported() { return false; }; 466 467 int32_t GetConvSamplerIndex( 468 PMHW_SAMPLER_STATE_PARAM samplerParam, 469 char *samplerIndexTable, 470 int32_t nSamp8X8Num, 471 int32_t nSampConvNum); 472 473 MOS_STATUS SetL3CacheConfig( 474 const L3ConfigRegisterValues *values, 475 PCmHalL3Settings cmHalL3Setting); 476 477 MOS_STATUS GetSamplerParamInfoForSamplerType( 478 PMHW_SAMPLER_STATE_PARAM mhwSamplerParam, 479 SamplerParam &samplerParam); 480 481 uint64_t ConverTicksToNanoSecondsDefault(uint64_t ticks); 482 483 484 private: 485 486 MOS_STATUS RegisterSampler8x8AVSTable( 487 PCM_HAL_SAMPLER_8X8_TABLE sampler8x8AvsTable, 488 PCM_AVS_TABLE_STATE_PARAMS avsTable); 489 490 MOS_STATUS SetupHwDebugControl( 491 PRENDERHAL_INTERFACE renderHal, 492 PMOS_COMMAND_BUFFER cmdBuffer); 493 494 }; 495 496 #endif // __CM_HAL_G8_H__ 497