1 /* 2 * Copyright (c) 2015-2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mmio.h 24 //! \brief Define the common MMIO registers for all Gens 25 //! \details 26 //! 27 28 #ifndef __MHW_MMIO_H__ 29 #define __MHW_MMIO_H__ 30 31 // VEBOX 32 #define MHW__PWR_CLK_STATE_REG 0x20C8 //MMIO register for power clock state 33 34 // RCS register 35 #define CS_GPR_R0 0x2600 36 37 //| MMIO register offsets used for the EU debug support 38 #define INSTPM 0x20c0 39 #define INSTPM_GLOBAL_DEBUG_ENABLE (1 << 4) 40 #define CS_DEBUG_MODE1 0x20ec 41 #define CS_DEBUG_MODE2 0x20d8 42 #define CS_DEBUG_MODE1_GLOBAL_DEBUG (1 << 6) 43 #define CS_DEBUG_MODE2_GLOBAL_DEBUG (1 << 5) 44 #define TD_CTL 0xe400 45 #define TD_CTL_FORCE_THREAD_BKPT_ENABLE (1 << 4) 46 #define TD_CTL_FORCE_EXT_EXCEPTION_ENABLE (1 << 7) 47 // RENDER 48 #define MHW_RENDER_ENGINE_PREEMPTION_CONTROL_OFFSET 0x2580 49 #define MHW_RENDER_ENGINE_MID_THREAD_PREEMPT_VALUE 0x00060000 50 #define MHW_RENDER_ENGINE_THREAD_GROUP_PREEMPT_VALUE 0x00060002 51 #define MHW_RENDER_ENGINE_MID_BATCH_PREEMPT_VALUE 0x00060004 52 53 #define M_L3_CACHE_CNTL_REG_OFFSET 0x7034 54 #define M_L3_CACHE_CNTL_REG_VALUE_DEFAULT 0 55 56 typedef struct _MHW_MI_MMIOREGISTERS 57 { 58 uint32_t generalPurposeRegister0LoOffset; 59 uint32_t generalPurposeRegister0HiOffset; 60 uint32_t generalPurposeRegister4LoOffset; 61 uint32_t generalPurposeRegister4HiOffset; 62 uint32_t generalPurposeRegister11LoOffset; //!< __OCA_BUFFER_ADDR_LOW_MMIO 63 uint32_t generalPurposeRegister11HiOffset; //!< __OCA_BUFFER_ADDR_HIGH_MMIO 64 uint32_t generalPurposeRegister12LoOffset; //!< __OCA_BUFFER_IND_STATE_SECTION_OFFSET_MMIO 65 uint32_t generalPurposeRegister12HiOffset; //!< __OCA_BUFFER_BB_SECTION_OFFSET_MMIO 66 } MHW_MI_MMIOREGISTERS, *PMHW_MI_MMIOREGISTERS; 67 68 69 //! 70 //! \struct MmioRegistersHcp 71 //! \brief MMIO registers HCP 72 //! 73 struct MmioRegistersHcp 74 { 75 uint32_t watchdogCountCtrlOffset; 76 uint32_t watchdogCountThresholdOffset; 77 uint32_t hcpDebugFEStreamOutSizeRegOffset; 78 uint32_t hcpEncImageStatusMaskRegOffset; 79 uint32_t hcpEncImageStatusCtrlRegOffset; 80 uint32_t hcpEncBitstreamBytecountFrameRegOffset; 81 uint32_t hcpEncBitstreamSeBitcountFrameRegOffset; 82 uint32_t hcpEncBitstreamBytecountFrameNoHeaderRegOffset; 83 uint32_t hcpEncQpStatusCountRegOffset; 84 uint32_t hcpEncSliceCountRegOffset; 85 uint32_t hcpEncVdencModeTimerRegOffset; 86 uint32_t hcpVp9EncBitstreamBytecountFrameRegOffset; 87 uint32_t hcpVp9EncBitstreamBytecountFrameNoHeaderRegOffset; 88 uint32_t hcpVp9EncImageStatusMaskRegOffset; 89 uint32_t hcpVp9EncImageStatusCtrlRegOffset; 90 uint32_t csEngineIdOffset; 91 uint32_t hcpDecStatusRegOffset; 92 uint32_t hcpCabacStatusRegOffset; 93 uint32_t hcpFrameCrcRegOffset; 94 }; 95 96 97 struct MmioRegistersHuc 98 { 99 uint32_t hucStatusRegOffset = 0; 100 uint32_t hucUKernelHdrInfoRegOffset = 0; 101 uint32_t hucStatus2RegOffset = 0; 102 uint32_t hucLoadInfoOffset = 0; 103 }; 104 105 //! 106 //! \struct MmioRegistersMfx 107 //! \brief MM IO register MFX 108 //! 109 struct MmioRegistersMfx 110 { 111 uint32_t generalPurposeRegister0LoOffset = 0; 112 uint32_t generalPurposeRegister0HiOffset = 0; 113 uint32_t generalPurposeRegister4LoOffset = 0; 114 uint32_t generalPurposeRegister4HiOffset = 0; 115 uint32_t generalPurposeRegister11LoOffset = 0; //!< __OCA_BUFFER_ADDR_LOW_MMIO 116 uint32_t generalPurposeRegister11HiOffset = 0; //!< __OCA_BUFFER_ADDR_HIGH_MMIO 117 uint32_t generalPurposeRegister12LoOffset = 0; //!< __OCA_BUFFER_IND_STATE_SECTION_OFFSET_MMIO 118 uint32_t generalPurposeRegister12HiOffset = 0; //!< __OCA_BUFFER_BB_SECTION_OFFSET_MMIO 119 uint32_t mfcImageStatusMaskRegOffset = 0; 120 uint32_t mfcImageStatusCtrlRegOffset = 0; 121 uint32_t mfcAvcNumSlicesRegOffset = 0; 122 uint32_t mfcQPStatusCountOffset = 0; 123 uint32_t mfxErrorFlagsRegOffset = 0; 124 uint32_t mfxFrameCrcRegOffset = 0; 125 uint32_t mfxMBCountRegOffset = 0; 126 uint32_t mfcBitstreamBytecountFrameRegOffset = 0; 127 uint32_t mfcBitstreamSeBitcountFrameRegOffset = 0; 128 uint32_t mfcBitstreamBytecountSliceRegOffset = 0; 129 uint32_t mfcVP8BitstreamBytecountFrameRegOffset = 0; 130 uint32_t mfcVP8ImageStatusMaskRegOffset = 0; 131 uint32_t mfcVP8ImageStatusCtrlRegOffset = 0; 132 uint32_t mfxVP8BrcDQIndexRegOffset = 0; 133 uint32_t mfxVP8BrcDLoopFilterRegOffset = 0; 134 uint32_t mfxVP8BrcCumulativeDQIndex01RegOffset = 0; 135 uint32_t mfxVP8BrcCumulativeDQIndex23RegOffset = 0; 136 uint32_t mfxVP8BrcCumulativeDLoopFilter01RegOffset = 0; 137 uint32_t mfxVP8BrcCumulativeDLoopFilter23RegOffset = 0; 138 uint32_t mfxVP8BrcConvergenceStatusRegOffset = 0; 139 uint32_t mfxLra0RegOffset = 0; 140 uint32_t mfxLra1RegOffset = 0; 141 uint32_t mfxLra2RegOffset = 0; 142 }; 143 144 typedef MmioRegistersMfx MmioRegistersVdbox; 145 146 //! 147 //! \brief MHW VEBOX MMIO Structure 148 //! 149 typedef struct _MHW_VEBOX_MMIO 150 { 151 uint32_t dwWatchdogCountCtrlOffset; 152 uint32_t dwWatchdogCountThresholdOffset; 153 } MHW_VEBOX_MMIO, *PMHW_VEBOX_MMIO; 154 155 156 #endif // __MHW_MMIO_H__ 157