1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <cbmem.h>
4 #include <romstage_handoff.h>
5 #include <console/console.h>
6 #include <device/pci_ops.h>
7 #include <arch/romstage.h>
8 #include <northbridge/intel/gm45/gm45.h>
9 #include <southbridge/intel/i82801ix/i82801ix.h>
10 #include <southbridge/intel/common/gpio.h>
11 #include <southbridge/intel/common/pmclib.h>
12 #include <southbridge/intel/common/pmutil.h>
13 #include <string.h>
14
15 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
16 #define MCH_DEV PCI_DEV(0, 0, 0)
17
mb_setup_superio(void)18 void __weak mb_setup_superio(void)
19 {
20 }
21
mb_pre_raminit_setup(sysinfo_t * sysinfo)22 void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo)
23 {
24 }
25
mb_post_raminit_setup(void)26 void __weak mb_post_raminit_setup(void)
27 {
28 }
29
30 /* Platform has no romstage entry point under mainboard directory,
31 * so this one is named with prefix mainboard.
32 */
mainboard_romstage_entry(void)33 void mainboard_romstage_entry(void)
34 {
35 sysinfo_t sysinfo;
36 int s3resume = 0;
37 int cbmem_initted;
38 u16 reg16;
39
40 /* basic northbridge setup, including MMCONF BAR */
41 gm45_early_init();
42
43 /* First, run everything needed for console output. */
44 i82801ix_early_init();
45 setup_pch_gpios(&mainboard_gpio_map);
46
47 reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
48 pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
49 if ((mchbar_read16(SSKPD_MCHBAR) == 0xcafe) && !(reg16 & (1 << 9))) {
50 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
51 gm45_early_reset();
52 }
53
54 /* ASPM related setting, set early by original BIOS. */
55 dmibar_clrbits16(0x204, 3 << 10);
56
57 /* Check for S3 resume. */
58 s3resume = southbridge_detect_s3_resume();
59
60 /* RAM initialization */
61 enter_raminit_or_reset();
62 memset(&sysinfo, 0, sizeof(sysinfo));
63 get_mb_spd_addrmap(sysinfo.spd_map);
64 const struct device *dev;
65 dev = pcidev_on_root(2, 0);
66 if (dev)
67 sysinfo.enable_igd = dev->enabled;
68 dev = pcidev_on_root(1, 0);
69 if (dev)
70 sysinfo.enable_peg = dev->enabled;
71 get_gmch_info(&sysinfo);
72
73 mb_pre_raminit_setup(&sysinfo);
74
75 raminit(&sysinfo, s3resume);
76
77 /* Disable D4F0 (unknown signal controller). */
78 pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000);
79
80 init_pm(&sysinfo, 0);
81
82 i82801ix_dmi_setup();
83 gm45_late_init(sysinfo.stepping);
84 i82801ix_dmi_poll_vc1();
85
86 mchbar_write16(SSKPD_MCHBAR, 0xcafe);
87
88 init_iommu();
89
90 cbmem_initted = !cbmem_recovery(s3resume);
91
92 setup_sdram_meminfo(&sysinfo);
93
94 mb_post_raminit_setup();
95
96 romstage_handoff_init(cbmem_initted && s3resume);
97
98 printk(BIOS_SPEW, "exit main()\n");
99 }
100