1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 /* CSI reveiver has 3 ports. */ 8 #define N_CSI_PORTS (3) 9 10 #include "system_local.h" 11 #include "isys_dma_global.h" /* isys2401_dma_channel, 12 * isys2401_dma_cfg_t 13 */ 14 15 #include "ibuf_ctrl_local.h" /* ibuf_cfg_t, 16 * ibuf_ctrl_cfg_t 17 */ 18 19 #include "isys_stream2mmio.h" /* stream2mmio_cfg_t */ 20 21 #include "csi_rx.h" /* csi_rx_frontend_cfg_t, 22 * csi_rx_backend_cfg_t, 23 * csi_rx_backend_lut_entry_t 24 */ 25 #include "pixelgen.h" 26 27 #define INPUT_SYSTEM_N_STREAM_ID 6 /* maximum number of simultaneous 28 virtual channels supported*/ 29 30 typedef enum { 31 INPUT_SYSTEM_SOURCE_TYPE_UNDEFINED = 0, 32 INPUT_SYSTEM_SOURCE_TYPE_SENSOR, 33 INPUT_SYSTEM_SOURCE_TYPE_PRBS, 34 N_INPUT_SYSTEM_SOURCE_TYPE 35 } input_system_source_type_t; 36 37 typedef struct input_system_channel_s input_system_channel_t; 38 struct input_system_channel_s { 39 stream2mmio_ID_t stream2mmio_id; 40 stream2mmio_sid_ID_t stream2mmio_sid_id; 41 42 ibuf_ctrl_ID_t ibuf_ctrl_id; 43 isp2401_ib_buffer_t ib_buffer; 44 45 isys2401_dma_ID_t dma_id; 46 isys2401_dma_channel dma_channel; 47 }; 48 49 typedef struct input_system_channel_cfg_s input_system_channel_cfg_t; 50 struct input_system_channel_cfg_s { 51 stream2mmio_cfg_t stream2mmio_cfg; 52 ibuf_ctrl_cfg_t ibuf_ctrl_cfg; 53 isys2401_dma_cfg_t dma_cfg; 54 isys2401_dma_port_cfg_t dma_src_port_cfg; 55 isys2401_dma_port_cfg_t dma_dest_port_cfg; 56 }; 57 58 typedef struct input_system_input_port_s input_system_input_port_t; 59 struct input_system_input_port_s { 60 input_system_source_type_t source_type; 61 62 struct { 63 csi_rx_frontend_ID_t frontend_id; 64 csi_rx_backend_ID_t backend_id; 65 csi_mipi_packet_type_t packet_type; 66 csi_rx_backend_lut_entry_t backend_lut_entry; 67 } csi_rx; 68 69 struct { 70 csi_mipi_packet_type_t packet_type; 71 csi_rx_backend_lut_entry_t backend_lut_entry; 72 } metadata; 73 74 struct { 75 pixelgen_ID_t pixelgen_id; 76 } pixelgen; 77 }; 78 79 typedef struct input_system_input_port_cfg_s input_system_input_port_cfg_t; 80 struct input_system_input_port_cfg_s { 81 struct { 82 csi_rx_frontend_cfg_t frontend_cfg; 83 csi_rx_backend_cfg_t backend_cfg; 84 csi_rx_backend_cfg_t md_backend_cfg; 85 } csi_rx_cfg; 86 87 struct { 88 pixelgen_tpg_cfg_t tpg_cfg; 89 pixelgen_prbs_cfg_t prbs_cfg; 90 } pixelgen_cfg; 91 }; 92 93 typedef struct isp2401_input_system_cfg_s isp2401_input_system_cfg_t; 94 struct isp2401_input_system_cfg_s { 95 input_system_input_port_ID_t input_port_id; 96 97 input_system_source_type_t mode; 98 99 bool online; 100 bool raw_packed; 101 s8 linked_isys_stream_id; 102 103 struct { 104 bool comp_enable; 105 s32 active_lanes; 106 s32 fmt_type; 107 s32 ch_id; 108 s32 comp_predictor; 109 s32 comp_scheme; 110 } csi_port_attr; 111 112 pixelgen_tpg_cfg_t tpg_port_attr; 113 114 pixelgen_prbs_cfg_t prbs_port_attr; 115 116 struct { 117 s32 align_req_in_bytes; 118 s32 bits_per_pixel; 119 s32 pixels_per_line; 120 s32 lines_per_frame; 121 } input_port_resolution; 122 123 struct { 124 s32 left_padding; 125 s32 max_isp_input_width; 126 } output_port_attr; 127 128 struct { 129 bool enable; 130 s32 fmt_type; 131 s32 align_req_in_bytes; 132 s32 bits_per_pixel; 133 s32 pixels_per_line; 134 s32 lines_per_frame; 135 } metadata; 136 }; 137 138 typedef struct virtual_input_system_stream_s virtual_input_system_stream_t; 139 struct virtual_input_system_stream_s { 140 u32 id; /*Used when multiple MIPI data types and/or virtual channels are used. 141 Must be unique within one CSI RX 142 and lower than SH_CSS_MAX_ISYS_CHANNEL_NODES */ 143 u8 enable_metadata; 144 input_system_input_port_t input_port; 145 input_system_channel_t channel; 146 input_system_channel_t md_channel; /* metadata channel */ 147 u8 online; 148 s8 linked_isys_stream_id; 149 u8 valid; 150 }; 151 152 typedef struct virtual_input_system_stream_cfg_s 153 virtual_input_system_stream_cfg_t; 154 struct virtual_input_system_stream_cfg_s { 155 u8 enable_metadata; 156 input_system_input_port_cfg_t input_port_cfg; 157 input_system_channel_cfg_t channel_cfg; 158 input_system_channel_cfg_t md_channel_cfg; 159 u8 valid; 160 }; 161 162 #define ISP_INPUT_BUF_START_ADDR 0 163 #define NUM_OF_INPUT_BUF 2 164 #define NUM_OF_LINES_PER_BUF 2 165 #define LINES_OF_ISP_INPUT_BUF (NUM_OF_INPUT_BUF * NUM_OF_LINES_PER_BUF) 166 #define ISP_INPUT_BUF_STRIDE SH_CSS_MAX_SENSOR_WIDTH 167