1 #ifndef __BDK_CSRS_GIC_H__
2 #define __BDK_CSRS_GIC_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium GIC.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration gic_bar_e
57 *
58 * GIC Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_GIC_BAR_E_GIC_PF_BAR0 (0x801000000000ll)
62 #define BDK_GIC_BAR_E_GIC_PF_BAR0_SIZE 0x20000ull
63 #define BDK_GIC_BAR_E_GIC_PF_BAR2 (0x801000020000ll)
64 #define BDK_GIC_BAR_E_GIC_PF_BAR2_SIZE 0x20000ull
65 #define BDK_GIC_BAR_E_GIC_PF_BAR4 (0x801080000000ll)
66 #define BDK_GIC_BAR_E_GIC_PF_BAR4_SIZE 0x1000000ull
67
68 /**
69 * Enumeration gic_int_req_e
70 *
71 * GIC Performance Counter Enumeration
72 * Enumerates the index of GIC_INT_REQ()_PC.
73 */
74 #define BDK_GIC_INT_REQ_E_GICD_CLRSPI_NSR_PC (1)
75 #define BDK_GIC_INT_REQ_E_GICD_CLRSPI_SR_PC (3)
76 #define BDK_GIC_INT_REQ_E_GICD_SETSPI_NSR_PC (0)
77 #define BDK_GIC_INT_REQ_E_GICD_SETSPI_SR_PC (2)
78 #define BDK_GIC_INT_REQ_E_GICR_CLRLPIR (6)
79 #define BDK_GIC_INT_REQ_E_GICR_SETLPIR (5)
80 #define BDK_GIC_INT_REQ_E_GITS_TRANSLATER (4)
81
82 /**
83 * Enumeration gits_cmd_err_e
84 *
85 * GIC ITS Command Error Enumeration
86 * The actual 24-bit ITS command SEI is defined as {8'h01,
87 * GITS_CMD_TYPE_E(8-bit), GITS_CMD_ERR_E(8-bit)}.
88 */
89 #define BDK_GITS_CMD_ERR_E_CSEI_CMD_TO (0xe0)
90 #define BDK_GITS_CMD_ERR_E_CSEI_COLLECTION_OOR (3)
91 #define BDK_GITS_CMD_ERR_E_CSEI_DEVICE_OOR (1)
92 #define BDK_GITS_CMD_ERR_E_CSEI_ID_OOR (5)
93 #define BDK_GITS_CMD_ERR_E_CSEI_ITE_INVALID (0x10)
94 #define BDK_GITS_CMD_ERR_E_CSEI_ITTSIZE_OOR (2)
95 #define BDK_GITS_CMD_ERR_E_CSEI_PHYSICALID_OOR (6)
96 #define BDK_GITS_CMD_ERR_E_CSEI_SYNCACK_INVALID (0xe1)
97 #define BDK_GITS_CMD_ERR_E_CSEI_TA_INVALID (0xfe)
98 #define BDK_GITS_CMD_ERR_E_CSEI_UNMAPPED_COLLECTION (9)
99 #define BDK_GITS_CMD_ERR_E_CSEI_UNMAPPED_DEVICE (4)
100 #define BDK_GITS_CMD_ERR_E_CSEI_UNMAPPED_INTERRUPT (7)
101 #define BDK_GITS_CMD_ERR_E_CSEI_UNSUPPORTED_CMD (0xff)
102
103 /**
104 * Enumeration gits_cmd_type_e
105 *
106 * GIC ITS Command Type Enumeration
107 * Enumerates the ITS commands.
108 */
109 #define BDK_GITS_CMD_TYPE_E_CMD_CLEAR (4)
110 #define BDK_GITS_CMD_TYPE_E_CMD_DISCARD (0xf)
111 #define BDK_GITS_CMD_TYPE_E_CMD_INT (3)
112 #define BDK_GITS_CMD_TYPE_E_CMD_INV (0xc)
113 #define BDK_GITS_CMD_TYPE_E_CMD_INVALL (0xd)
114 #define BDK_GITS_CMD_TYPE_E_CMD_MAPC (9)
115 #define BDK_GITS_CMD_TYPE_E_CMD_MAPD (8)
116 #define BDK_GITS_CMD_TYPE_E_CMD_MAPI (0xb)
117 #define BDK_GITS_CMD_TYPE_E_CMD_MAPVI (0xa)
118 #define BDK_GITS_CMD_TYPE_E_CMD_MOVALL (0xe)
119 #define BDK_GITS_CMD_TYPE_E_CMD_MOVI (1)
120 #define BDK_GITS_CMD_TYPE_E_CMD_SYNC (5)
121 #define BDK_GITS_CMD_TYPE_E_CMD_UDF (0)
122
123 /**
124 * Structure gits_cmd_clear_s
125 *
126 * GIC ITS Clear Command Structure
127 */
128 union bdk_gits_cmd_clear_s
129 {
130 uint64_t u[4];
131 struct bdk_gits_cmd_clear_s_s
132 {
133 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
134 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
135 uint64_t reserved_8_31 : 24;
136 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_CLEAR. */
137 #else /* Word 0 - Little Endian */
138 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_CLEAR. */
139 uint64_t reserved_8_31 : 24;
140 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
141 #endif /* Word 0 - End */
142 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
143 uint64_t reserved_96_127 : 32;
144 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID to be translated. */
145 #else /* Word 1 - Little Endian */
146 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID to be translated. */
147 uint64_t reserved_96_127 : 32;
148 #endif /* Word 1 - End */
149 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
150 uint64_t reserved_128_191 : 64;
151 #else /* Word 2 - Little Endian */
152 uint64_t reserved_128_191 : 64;
153 #endif /* Word 2 - End */
154 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
155 uint64_t reserved_192_255 : 64;
156 #else /* Word 3 - Little Endian */
157 uint64_t reserved_192_255 : 64;
158 #endif /* Word 3 - End */
159 } s;
160 /* struct bdk_gits_cmd_clear_s_s cn; */
161 };
162
163 /**
164 * Structure gits_cmd_discard_s
165 *
166 * GIC ITS Discard Command Structure
167 */
168 union bdk_gits_cmd_discard_s
169 {
170 uint64_t u[4];
171 struct bdk_gits_cmd_discard_s_s
172 {
173 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
174 uint64_t dev_id : 32; /**< [ 63: 32] Device ID. */
175 uint64_t reserved_8_31 : 24;
176 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_DISCARD. */
177 #else /* Word 0 - Little Endian */
178 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_DISCARD. */
179 uint64_t reserved_8_31 : 24;
180 uint64_t dev_id : 32; /**< [ 63: 32] Device ID. */
181 #endif /* Word 0 - End */
182 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
183 uint64_t reserved_96_127 : 32;
184 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID. */
185 #else /* Word 1 - Little Endian */
186 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID. */
187 uint64_t reserved_96_127 : 32;
188 #endif /* Word 1 - End */
189 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
190 uint64_t reserved_128_191 : 64;
191 #else /* Word 2 - Little Endian */
192 uint64_t reserved_128_191 : 64;
193 #endif /* Word 2 - End */
194 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
195 uint64_t reserved_192_255 : 64;
196 #else /* Word 3 - Little Endian */
197 uint64_t reserved_192_255 : 64;
198 #endif /* Word 3 - End */
199 } s;
200 /* struct bdk_gits_cmd_discard_s_s cn; */
201 };
202
203 /**
204 * Structure gits_cmd_int_s
205 *
206 * GIC ITS INT Command Structure
207 */
208 union bdk_gits_cmd_int_s
209 {
210 uint64_t u[4];
211 struct bdk_gits_cmd_int_s_s
212 {
213 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
214 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
215 uint64_t reserved_8_31 : 24;
216 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_INT. */
217 #else /* Word 0 - Little Endian */
218 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_INT. */
219 uint64_t reserved_8_31 : 24;
220 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
221 #endif /* Word 0 - End */
222 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
223 uint64_t reserved_96_127 : 32;
224 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID to be translated. */
225 #else /* Word 1 - Little Endian */
226 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID to be translated. */
227 uint64_t reserved_96_127 : 32;
228 #endif /* Word 1 - End */
229 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
230 uint64_t reserved_128_191 : 64;
231 #else /* Word 2 - Little Endian */
232 uint64_t reserved_128_191 : 64;
233 #endif /* Word 2 - End */
234 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
235 uint64_t reserved_192_255 : 64;
236 #else /* Word 3 - Little Endian */
237 uint64_t reserved_192_255 : 64;
238 #endif /* Word 3 - End */
239 } s;
240 /* struct bdk_gits_cmd_int_s_s cn; */
241 };
242
243 /**
244 * Structure gits_cmd_inv_s
245 *
246 * GIC ITS INV Command Structure
247 */
248 union bdk_gits_cmd_inv_s
249 {
250 uint64_t u[4];
251 struct bdk_gits_cmd_inv_s_s
252 {
253 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
254 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
255 uint64_t reserved_8_31 : 24;
256 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_INV. */
257 #else /* Word 0 - Little Endian */
258 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_INV. */
259 uint64_t reserved_8_31 : 24;
260 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
261 #endif /* Word 0 - End */
262 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
263 uint64_t reserved_96_127 : 32;
264 uint64_t int_id : 32; /**< [ 95: 64] Reserved. */
265 #else /* Word 1 - Little Endian */
266 uint64_t int_id : 32; /**< [ 95: 64] Reserved. */
267 uint64_t reserved_96_127 : 32;
268 #endif /* Word 1 - End */
269 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
270 uint64_t reserved_128_191 : 64;
271 #else /* Word 2 - Little Endian */
272 uint64_t reserved_128_191 : 64;
273 #endif /* Word 2 - End */
274 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
275 uint64_t reserved_192_255 : 64;
276 #else /* Word 3 - Little Endian */
277 uint64_t reserved_192_255 : 64;
278 #endif /* Word 3 - End */
279 } s;
280 /* struct bdk_gits_cmd_inv_s_s cn; */
281 };
282
283 /**
284 * Structure gits_cmd_invall_s
285 *
286 * GIC ITS INVALL Command Structure
287 */
288 union bdk_gits_cmd_invall_s
289 {
290 uint64_t u[4];
291 struct bdk_gits_cmd_invall_s_s
292 {
293 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
294 uint64_t reserved_8_63 : 56;
295 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_INVALL. */
296 #else /* Word 0 - Little Endian */
297 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_INVALL. */
298 uint64_t reserved_8_63 : 56;
299 #endif /* Word 0 - End */
300 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
301 uint64_t reserved_64_127 : 64;
302 #else /* Word 1 - Little Endian */
303 uint64_t reserved_64_127 : 64;
304 #endif /* Word 1 - End */
305 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
306 uint64_t reserved_144_191 : 48;
307 uint64_t cid : 16; /**< [143:128] Interrupt collection ID. */
308 #else /* Word 2 - Little Endian */
309 uint64_t cid : 16; /**< [143:128] Interrupt collection ID. */
310 uint64_t reserved_144_191 : 48;
311 #endif /* Word 2 - End */
312 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
313 uint64_t reserved_192_255 : 64;
314 #else /* Word 3 - Little Endian */
315 uint64_t reserved_192_255 : 64;
316 #endif /* Word 3 - End */
317 } s;
318 /* struct bdk_gits_cmd_invall_s_s cn; */
319 };
320
321 /**
322 * Structure gits_cmd_mapc_s
323 *
324 * GIC ITS MAPC Command Structure
325 */
326 union bdk_gits_cmd_mapc_s
327 {
328 uint64_t u[4];
329 struct bdk_gits_cmd_mapc_s_s
330 {
331 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
332 uint64_t reserved_8_63 : 56;
333 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPC. */
334 #else /* Word 0 - Little Endian */
335 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPC. */
336 uint64_t reserved_8_63 : 56;
337 #endif /* Word 0 - End */
338 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
339 uint64_t reserved_64_127 : 64;
340 #else /* Word 1 - Little Endian */
341 uint64_t reserved_64_127 : 64;
342 #endif /* Word 1 - End */
343 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
344 uint64_t v : 1; /**< [191:191] Valid bit. Specifies whether the ITT address and size are valid. When [V] is
345 zero, this command unmaps the specified device and translation request from
346 that device will be discarded. */
347 uint64_t reserved_176_190 : 15;
348 uint64_t ta : 32; /**< [175:144] Target address. Specifies the physical address of the redistributor to which
349 interrupts for the collection will be forwarded. */
350 uint64_t cid : 16; /**< [143:128] Interrupt collection ID. */
351 #else /* Word 2 - Little Endian */
352 uint64_t cid : 16; /**< [143:128] Interrupt collection ID. */
353 uint64_t ta : 32; /**< [175:144] Target address. Specifies the physical address of the redistributor to which
354 interrupts for the collection will be forwarded. */
355 uint64_t reserved_176_190 : 15;
356 uint64_t v : 1; /**< [191:191] Valid bit. Specifies whether the ITT address and size are valid. When [V] is
357 zero, this command unmaps the specified device and translation request from
358 that device will be discarded. */
359 #endif /* Word 2 - End */
360 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
361 uint64_t reserved_192_255 : 64;
362 #else /* Word 3 - Little Endian */
363 uint64_t reserved_192_255 : 64;
364 #endif /* Word 3 - End */
365 } s;
366 /* struct bdk_gits_cmd_mapc_s_s cn; */
367 };
368
369 /**
370 * Structure gits_cmd_mapd_s
371 *
372 * GIC ITS MAPD Command Structure
373 */
374 union bdk_gits_cmd_mapd_s
375 {
376 uint64_t u[4];
377 struct bdk_gits_cmd_mapd_s_s
378 {
379 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
380 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
381 uint64_t reserved_8_31 : 24;
382 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPD. */
383 #else /* Word 0 - Little Endian */
384 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPD. */
385 uint64_t reserved_8_31 : 24;
386 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
387 #endif /* Word 0 - End */
388 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
389 uint64_t reserved_69_127 : 59;
390 uint64_t size : 5; /**< [ 68: 64] Number of bits of interrupt ID supported for this device, minus one. */
391 #else /* Word 1 - Little Endian */
392 uint64_t size : 5; /**< [ 68: 64] Number of bits of interrupt ID supported for this device, minus one. */
393 uint64_t reserved_69_127 : 59;
394 #endif /* Word 1 - End */
395 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
396 uint64_t v : 1; /**< [191:191] Valid bit. Specifies whether the ITT address and size are valid. When [V] is zero,
397 this command unmaps the specified device and translation request from that
398 device will be discarded. */
399 uint64_t reserved_176_190 : 15;
400 uint64_t itta : 40; /**< [175:136] ITT address. Specifies bits \<47:8\> of the physical address of the interrupt
401 translation table. Bits \<7:0\> of the physical address are zero. */
402 uint64_t reserved_128_135 : 8;
403 #else /* Word 2 - Little Endian */
404 uint64_t reserved_128_135 : 8;
405 uint64_t itta : 40; /**< [175:136] ITT address. Specifies bits \<47:8\> of the physical address of the interrupt
406 translation table. Bits \<7:0\> of the physical address are zero. */
407 uint64_t reserved_176_190 : 15;
408 uint64_t v : 1; /**< [191:191] Valid bit. Specifies whether the ITT address and size are valid. When [V] is zero,
409 this command unmaps the specified device and translation request from that
410 device will be discarded. */
411 #endif /* Word 2 - End */
412 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
413 uint64_t reserved_192_255 : 64;
414 #else /* Word 3 - Little Endian */
415 uint64_t reserved_192_255 : 64;
416 #endif /* Word 3 - End */
417 } s;
418 /* struct bdk_gits_cmd_mapd_s_s cn; */
419 };
420
421 /**
422 * Structure gits_cmd_mapi_s
423 *
424 * GIC ITS MAPI Command Structure
425 */
426 union bdk_gits_cmd_mapi_s
427 {
428 uint64_t u[4];
429 struct bdk_gits_cmd_mapi_s_s
430 {
431 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
432 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
433 uint64_t reserved_8_31 : 24;
434 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPI. */
435 #else /* Word 0 - Little Endian */
436 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPI. */
437 uint64_t reserved_8_31 : 24;
438 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
439 #endif /* Word 0 - End */
440 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
441 uint64_t reserved_96_127 : 32;
442 uint64_t int_id : 32; /**< [ 95: 64] Reserved. */
443 #else /* Word 1 - Little Endian */
444 uint64_t int_id : 32; /**< [ 95: 64] Reserved. */
445 uint64_t reserved_96_127 : 32;
446 #endif /* Word 1 - End */
447 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
448 uint64_t reserved_144_191 : 48;
449 uint64_t cid : 16; /**< [143:128] Collection. Specifies the interrupt collection of which the interrupt with identifier
450 physical ID is a member. */
451 #else /* Word 2 - Little Endian */
452 uint64_t cid : 16; /**< [143:128] Collection. Specifies the interrupt collection of which the interrupt with identifier
453 physical ID is a member. */
454 uint64_t reserved_144_191 : 48;
455 #endif /* Word 2 - End */
456 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
457 uint64_t reserved_192_255 : 64;
458 #else /* Word 3 - Little Endian */
459 uint64_t reserved_192_255 : 64;
460 #endif /* Word 3 - End */
461 } s;
462 /* struct bdk_gits_cmd_mapi_s_s cn; */
463 };
464
465 /**
466 * Structure gits_cmd_mapvi_s
467 *
468 * GIC ITS MAPVI Command Structure
469 */
470 union bdk_gits_cmd_mapvi_s
471 {
472 uint64_t u[4];
473 struct bdk_gits_cmd_mapvi_s_s
474 {
475 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
476 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
477 uint64_t reserved_8_31 : 24;
478 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPVI. */
479 #else /* Word 0 - Little Endian */
480 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MAPVI. */
481 uint64_t reserved_8_31 : 24;
482 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
483 #endif /* Word 0 - End */
484 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
485 uint64_t phy_id : 32; /**< [127: 96] Reserved. */
486 uint64_t int_id : 32; /**< [ 95: 64] Reserved. */
487 #else /* Word 1 - Little Endian */
488 uint64_t int_id : 32; /**< [ 95: 64] Reserved. */
489 uint64_t phy_id : 32; /**< [127: 96] Reserved. */
490 #endif /* Word 1 - End */
491 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
492 uint64_t reserved_144_191 : 48;
493 uint64_t cid : 16; /**< [143:128] Collection. Specifies the interrupt collection of which the interrupt with identifier
494 physical ID is a member. */
495 #else /* Word 2 - Little Endian */
496 uint64_t cid : 16; /**< [143:128] Collection. Specifies the interrupt collection of which the interrupt with identifier
497 physical ID is a member. */
498 uint64_t reserved_144_191 : 48;
499 #endif /* Word 2 - End */
500 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
501 uint64_t reserved_192_255 : 64;
502 #else /* Word 3 - Little Endian */
503 uint64_t reserved_192_255 : 64;
504 #endif /* Word 3 - End */
505 } s;
506 /* struct bdk_gits_cmd_mapvi_s_s cn; */
507 };
508
509 /**
510 * Structure gits_cmd_movall_s
511 *
512 * GIC ITS MOVALL Command Structure
513 */
514 union bdk_gits_cmd_movall_s
515 {
516 uint64_t u[4];
517 struct bdk_gits_cmd_movall_s_s
518 {
519 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
520 uint64_t reserved_8_63 : 56;
521 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MOVALL. */
522 #else /* Word 0 - Little Endian */
523 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MOVALL. */
524 uint64_t reserved_8_63 : 56;
525 #endif /* Word 0 - End */
526 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
527 uint64_t reserved_64_127 : 64;
528 #else /* Word 1 - Little Endian */
529 uint64_t reserved_64_127 : 64;
530 #endif /* Word 1 - End */
531 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
532 uint64_t reserved_176_191 : 16;
533 uint64_t ta1 : 32; /**< [175:144] Target address 1. Specifies the old redistributor. */
534 uint64_t reserved_128_143 : 16;
535 #else /* Word 2 - Little Endian */
536 uint64_t reserved_128_143 : 16;
537 uint64_t ta1 : 32; /**< [175:144] Target address 1. Specifies the old redistributor. */
538 uint64_t reserved_176_191 : 16;
539 #endif /* Word 2 - End */
540 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
541 uint64_t reserved_240_255 : 16;
542 uint64_t ta2 : 32; /**< [239:208] Target address 2. Specifies the new redistributor. */
543 uint64_t reserved_192_207 : 16;
544 #else /* Word 3 - Little Endian */
545 uint64_t reserved_192_207 : 16;
546 uint64_t ta2 : 32; /**< [239:208] Target address 2. Specifies the new redistributor. */
547 uint64_t reserved_240_255 : 16;
548 #endif /* Word 3 - End */
549 } s;
550 /* struct bdk_gits_cmd_movall_s_s cn; */
551 };
552
553 /**
554 * Structure gits_cmd_movi_s
555 *
556 * GIC ITS MOVI Command Structure
557 */
558 union bdk_gits_cmd_movi_s
559 {
560 uint64_t u[4];
561 struct bdk_gits_cmd_movi_s_s
562 {
563 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
564 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
565 uint64_t reserved_8_31 : 24;
566 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MOVI. */
567 #else /* Word 0 - Little Endian */
568 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_MOVI. */
569 uint64_t reserved_8_31 : 24;
570 uint64_t dev_id : 32; /**< [ 63: 32] Interrupt device ID. */
571 #endif /* Word 0 - End */
572 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
573 uint64_t reserved_96_127 : 32;
574 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID to be translated. */
575 #else /* Word 1 - Little Endian */
576 uint64_t int_id : 32; /**< [ 95: 64] Interrupt ID to be translated. */
577 uint64_t reserved_96_127 : 32;
578 #endif /* Word 1 - End */
579 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
580 uint64_t reserved_144_191 : 48;
581 uint64_t cid : 16; /**< [143:128] Interrupt collection ID. */
582 #else /* Word 2 - Little Endian */
583 uint64_t cid : 16; /**< [143:128] Interrupt collection ID. */
584 uint64_t reserved_144_191 : 48;
585 #endif /* Word 2 - End */
586 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
587 uint64_t reserved_192_255 : 64;
588 #else /* Word 3 - Little Endian */
589 uint64_t reserved_192_255 : 64;
590 #endif /* Word 3 - End */
591 } s;
592 /* struct bdk_gits_cmd_movi_s_s cn; */
593 };
594
595 /**
596 * Structure gits_cmd_sync_s
597 *
598 * GIC ITS SYNC Command Structure
599 */
600 union bdk_gits_cmd_sync_s
601 {
602 uint64_t u[4];
603 struct bdk_gits_cmd_sync_s_s
604 {
605 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
606 uint64_t reserved_8_63 : 56;
607 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_SYNC. */
608 #else /* Word 0 - Little Endian */
609 uint64_t cmd_type : 8; /**< [ 7: 0] Command type. Indicates GITS_CMD_TYPE_E::CMD_SYNC. */
610 uint64_t reserved_8_63 : 56;
611 #endif /* Word 0 - End */
612 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
613 uint64_t reserved_64_127 : 64;
614 #else /* Word 1 - Little Endian */
615 uint64_t reserved_64_127 : 64;
616 #endif /* Word 1 - End */
617 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 2 - Big Endian */
618 uint64_t reserved_176_191 : 16;
619 uint64_t ta : 32; /**< [175:144] Target address of the redistributor 0. */
620 uint64_t reserved_128_143 : 16;
621 #else /* Word 2 - Little Endian */
622 uint64_t reserved_128_143 : 16;
623 uint64_t ta : 32; /**< [175:144] Target address of the redistributor 0. */
624 uint64_t reserved_176_191 : 16;
625 #endif /* Word 2 - End */
626 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 3 - Big Endian */
627 uint64_t reserved_192_255 : 64;
628 #else /* Word 3 - Little Endian */
629 uint64_t reserved_192_255 : 64;
630 #endif /* Word 3 - End */
631 } s;
632 /* struct bdk_gits_cmd_sync_s_s cn; */
633 };
634
635 /**
636 * Register (NCB) gic_bist_statusr
637 *
638 * GIC Implementation BIST Status Register
639 * This register contains the BIST status for the GIC memories (including ITS and RDB).
640 */
641 union bdk_gic_bist_statusr
642 {
643 uint64_t u;
644 struct bdk_gic_bist_statusr_s
645 {
646 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
647 uint64_t reserved_9_63 : 55;
648 uint64_t bist : 9; /**< [ 8: 0](RO/H) Memory BIST status:
649 0 = Pass.
650 1 = Fail.
651
652 Internal:
653 [8:0]= [cic2cic_ig_buf, lpi_cfg_buf, lip_rmw_buf,
654 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
655 #else /* Word 0 - Little Endian */
656 uint64_t bist : 9; /**< [ 8: 0](RO/H) Memory BIST status:
657 0 = Pass.
658 1 = Fail.
659
660 Internal:
661 [8:0]= [cic2cic_ig_buf, lpi_cfg_buf, lip_rmw_buf,
662 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
663 uint64_t reserved_9_63 : 55;
664 #endif /* Word 0 - End */
665 } s;
666 /* struct bdk_gic_bist_statusr_s cn; */
667 };
668 typedef union bdk_gic_bist_statusr bdk_gic_bist_statusr_t;
669
670 #define BDK_GIC_BIST_STATUSR BDK_GIC_BIST_STATUSR_FUNC()
671 static inline uint64_t BDK_GIC_BIST_STATUSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_BIST_STATUSR_FUNC(void)672 static inline uint64_t BDK_GIC_BIST_STATUSR_FUNC(void)
673 {
674 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
675 return 0x801000010020ll;
676 __bdk_csr_fatal("GIC_BIST_STATUSR", 0, 0, 0, 0, 0);
677 }
678
679 #define typedef_BDK_GIC_BIST_STATUSR bdk_gic_bist_statusr_t
680 #define bustype_BDK_GIC_BIST_STATUSR BDK_CSR_TYPE_NCB
681 #define basename_BDK_GIC_BIST_STATUSR "GIC_BIST_STATUSR"
682 #define device_bar_BDK_GIC_BIST_STATUSR 0x0 /* PF_BAR0 */
683 #define busnum_BDK_GIC_BIST_STATUSR 0
684 #define arguments_BDK_GIC_BIST_STATUSR -1,-1,-1,-1
685
686 /**
687 * Register (NCB) gic_bp_test0
688 *
689 * INTERNAL: GIC Backpressure Test Register
690 */
691 union bdk_gic_bp_test0
692 {
693 uint64_t u;
694 struct bdk_gic_bp_test0_s
695 {
696 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
697 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
698 Internal:
699 Once a bit is set, random backpressure is generated
700 at the corresponding point to allow for more frequent backpressure.
701 \<63\> = Limit RDB NCBI transactions. Never limit 100% of the time.
702 \<62\> = Limit ITS NCBI transactions. Never limit 100% of the time.
703 \<61\> = Limit RDB interrupt message handling via NCBO. Never limit 100% of the time.
704 \<60\> = Limit ITS interrupt message handling via NCBO. Never limit 100% of the time. */
705 uint64_t reserved_24_59 : 36;
706 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
707 Internal:
708 There are 2 backpressure configuration bits per enable, with the two bits
709 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
710 0x3=25% of the time.
711 \<23:22\> = Config 3.
712 \<21:20\> = Config 2.
713 \<19:18\> = Config 1.
714 \<17:16\> = Config 0. */
715 uint64_t reserved_12_15 : 4;
716 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
717 #else /* Word 0 - Little Endian */
718 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
719 uint64_t reserved_12_15 : 4;
720 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
721 Internal:
722 There are 2 backpressure configuration bits per enable, with the two bits
723 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
724 0x3=25% of the time.
725 \<23:22\> = Config 3.
726 \<21:20\> = Config 2.
727 \<19:18\> = Config 1.
728 \<17:16\> = Config 0. */
729 uint64_t reserved_24_59 : 36;
730 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
731 Internal:
732 Once a bit is set, random backpressure is generated
733 at the corresponding point to allow for more frequent backpressure.
734 \<63\> = Limit RDB NCBI transactions. Never limit 100% of the time.
735 \<62\> = Limit ITS NCBI transactions. Never limit 100% of the time.
736 \<61\> = Limit RDB interrupt message handling via NCBO. Never limit 100% of the time.
737 \<60\> = Limit ITS interrupt message handling via NCBO. Never limit 100% of the time. */
738 #endif /* Word 0 - End */
739 } s;
740 /* struct bdk_gic_bp_test0_s cn; */
741 };
742 typedef union bdk_gic_bp_test0 bdk_gic_bp_test0_t;
743
744 #define BDK_GIC_BP_TEST0 BDK_GIC_BP_TEST0_FUNC()
745 static inline uint64_t BDK_GIC_BP_TEST0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_BP_TEST0_FUNC(void)746 static inline uint64_t BDK_GIC_BP_TEST0_FUNC(void)
747 {
748 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
749 return 0x8010000100a0ll;
750 __bdk_csr_fatal("GIC_BP_TEST0", 0, 0, 0, 0, 0);
751 }
752
753 #define typedef_BDK_GIC_BP_TEST0 bdk_gic_bp_test0_t
754 #define bustype_BDK_GIC_BP_TEST0 BDK_CSR_TYPE_NCB
755 #define basename_BDK_GIC_BP_TEST0 "GIC_BP_TEST0"
756 #define device_bar_BDK_GIC_BP_TEST0 0x0 /* PF_BAR0 */
757 #define busnum_BDK_GIC_BP_TEST0 0
758 #define arguments_BDK_GIC_BP_TEST0 -1,-1,-1,-1
759
760 /**
761 * Register (NCB) gic_bp_test1
762 *
763 * INTERNAL: GIC Backpressure Test Register
764 */
765 union bdk_gic_bp_test1
766 {
767 uint64_t u;
768 struct bdk_gic_bp_test1_s
769 {
770 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
771 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
772 Internal:
773 Once a bit is set, random backpressure is generated
774 at the corresponding point to allow for more frequent backpressure.
775 \<63\> = Reserved.
776 \<62\> = Reserved.
777 \<61\> = Reserved.
778 \<60\> = Reserved. TBD?: Limit messages to AP CIMs. */
779 uint64_t reserved_24_59 : 36;
780 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
781 Internal:
782 There are 2 backpressure configuration bits per enable, with the two bits
783 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
784 0x3=25% of the time.
785 \<23:22\> = Reserved.
786 \<21:20\> = Config 2.
787 \<19:18\> = Config 1.
788 \<17:16\> = Config 0. */
789 uint64_t reserved_12_15 : 4;
790 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
791 #else /* Word 0 - Little Endian */
792 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
793 uint64_t reserved_12_15 : 4;
794 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
795 Internal:
796 There are 2 backpressure configuration bits per enable, with the two bits
797 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
798 0x3=25% of the time.
799 \<23:22\> = Reserved.
800 \<21:20\> = Config 2.
801 \<19:18\> = Config 1.
802 \<17:16\> = Config 0. */
803 uint64_t reserved_24_59 : 36;
804 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
805 Internal:
806 Once a bit is set, random backpressure is generated
807 at the corresponding point to allow for more frequent backpressure.
808 \<63\> = Reserved.
809 \<62\> = Reserved.
810 \<61\> = Reserved.
811 \<60\> = Reserved. TBD?: Limit messages to AP CIMs. */
812 #endif /* Word 0 - End */
813 } s;
814 /* struct bdk_gic_bp_test1_s cn; */
815 };
816 typedef union bdk_gic_bp_test1 bdk_gic_bp_test1_t;
817
818 #define BDK_GIC_BP_TEST1 BDK_GIC_BP_TEST1_FUNC()
819 static inline uint64_t BDK_GIC_BP_TEST1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_BP_TEST1_FUNC(void)820 static inline uint64_t BDK_GIC_BP_TEST1_FUNC(void)
821 {
822 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
823 return 0x8010000100b0ll;
824 __bdk_csr_fatal("GIC_BP_TEST1", 0, 0, 0, 0, 0);
825 }
826
827 #define typedef_BDK_GIC_BP_TEST1 bdk_gic_bp_test1_t
828 #define bustype_BDK_GIC_BP_TEST1 BDK_CSR_TYPE_NCB
829 #define basename_BDK_GIC_BP_TEST1 "GIC_BP_TEST1"
830 #define device_bar_BDK_GIC_BP_TEST1 0x0 /* PF_BAR0 */
831 #define busnum_BDK_GIC_BP_TEST1 0
832 #define arguments_BDK_GIC_BP_TEST1 -1,-1,-1,-1
833
834 /**
835 * Register (NCB) gic_cfg_ctlr
836 *
837 * GIC Implementation Secure Configuration Control Register
838 * This register configures GIC features.
839 */
840 union bdk_gic_cfg_ctlr
841 {
842 uint64_t u;
843 struct bdk_gic_cfg_ctlr_s
844 {
845 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
846 uint64_t reserved_34_63 : 30;
847 uint64_t dis_redist_lpi_aggr_merge : 1;/**< [ 33: 33](SR/W) Disable aggressive SETLPIR merging in redistributors. */
848 uint64_t dis_cpu_if_load_balancer : 1;/**< [ 32: 32](SR/W) Disable the CPU interface load balancer. */
849 uint64_t reserved_10_31 : 22;
850 uint64_t dis_lpi_pend_cache : 1; /**< [ 9: 9](SR/W) Disable the LPI pending table cache. */
851 uint64_t dis_lpi_cfg_cache : 1; /**< [ 8: 8](SR/W) Disable the LPI configuration cache. */
852 uint64_t dis_inv_hct : 1; /**< [ 7: 7](SR/W) Disable HW invalidating ITS HCT during ITS disable process. */
853 uint64_t dis_its_cdtc : 1; /**< [ 6: 6](SR/W) Disable 1-entry device table cache in ITS CEU. */
854 uint64_t dis_its_itlb : 1; /**< [ 5: 5](SR/W) Disable ITS ITLB (interrupt translation entry lookup buffer). */
855 uint64_t dis_its_dtlb : 1; /**< [ 4: 4](SR/W) Disable ITS DTLB (device table entry lookup buffer). */
856 uint64_t reserved_3 : 1;
857 uint64_t root_dist : 1; /**< [ 2: 2](SR/W) Specifies whether the distributor on this socket is root.
858 0 = Distributor is not root.
859 1 = Distributor is root.
860
861 Out of reset, this field is set. EL3 firmware will clear this field as required for multi-
862 socket operation. */
863 uint64_t om : 2; /**< [ 1: 0](SR/W) Operation mode.
864 0x0 = Single-socket single-root mode.
865 0x1 = Reserved.
866 0x2 = Multisocket single-root mode.
867 0x3 = Multisocket multiroot mode. */
868 #else /* Word 0 - Little Endian */
869 uint64_t om : 2; /**< [ 1: 0](SR/W) Operation mode.
870 0x0 = Single-socket single-root mode.
871 0x1 = Reserved.
872 0x2 = Multisocket single-root mode.
873 0x3 = Multisocket multiroot mode. */
874 uint64_t root_dist : 1; /**< [ 2: 2](SR/W) Specifies whether the distributor on this socket is root.
875 0 = Distributor is not root.
876 1 = Distributor is root.
877
878 Out of reset, this field is set. EL3 firmware will clear this field as required for multi-
879 socket operation. */
880 uint64_t reserved_3 : 1;
881 uint64_t dis_its_dtlb : 1; /**< [ 4: 4](SR/W) Disable ITS DTLB (device table entry lookup buffer). */
882 uint64_t dis_its_itlb : 1; /**< [ 5: 5](SR/W) Disable ITS ITLB (interrupt translation entry lookup buffer). */
883 uint64_t dis_its_cdtc : 1; /**< [ 6: 6](SR/W) Disable 1-entry device table cache in ITS CEU. */
884 uint64_t dis_inv_hct : 1; /**< [ 7: 7](SR/W) Disable HW invalidating ITS HCT during ITS disable process. */
885 uint64_t dis_lpi_cfg_cache : 1; /**< [ 8: 8](SR/W) Disable the LPI configuration cache. */
886 uint64_t dis_lpi_pend_cache : 1; /**< [ 9: 9](SR/W) Disable the LPI pending table cache. */
887 uint64_t reserved_10_31 : 22;
888 uint64_t dis_cpu_if_load_balancer : 1;/**< [ 32: 32](SR/W) Disable the CPU interface load balancer. */
889 uint64_t dis_redist_lpi_aggr_merge : 1;/**< [ 33: 33](SR/W) Disable aggressive SETLPIR merging in redistributors. */
890 uint64_t reserved_34_63 : 30;
891 #endif /* Word 0 - End */
892 } s;
893 /* struct bdk_gic_cfg_ctlr_s cn9; */
894 /* struct bdk_gic_cfg_ctlr_s cn81xx; */
895 struct bdk_gic_cfg_ctlr_cn88xx
896 {
897 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
898 uint64_t reserved_33_63 : 31;
899 uint64_t dis_cpu_if_load_balancer : 1;/**< [ 32: 32](SR/W) Disable the CPU interface load balancer. */
900 uint64_t reserved_10_31 : 22;
901 uint64_t dis_lpi_pend_cache : 1; /**< [ 9: 9](SR/W) Disable the LPI pending table cache. */
902 uint64_t dis_lpi_cfg_cache : 1; /**< [ 8: 8](SR/W) Disable the LPI configuration cache. */
903 uint64_t dis_inv_hct : 1; /**< [ 7: 7](SR/W) Disable HW invalidating ITS HCT during ITS disable process. */
904 uint64_t dis_its_cdtc : 1; /**< [ 6: 6](SR/W) Disable 1-entry device table cache in ITS CEU. */
905 uint64_t dis_its_itlb : 1; /**< [ 5: 5](SR/W) Disable ITS ITLB (interrupt translation entry lookup buffer). */
906 uint64_t dis_its_dtlb : 1; /**< [ 4: 4](SR/W) Disable ITS DTLB (device table entry lookup buffer). */
907 uint64_t reserved_3 : 1;
908 uint64_t root_dist : 1; /**< [ 2: 2](SR/W) Specifies whether the distributor on this socket is root.
909 0 = Distributor is not root.
910 1 = Distributor is root.
911
912 Out of reset, this field is set. EL3 firmware will clear this field as required for multi-
913 socket operation. */
914 uint64_t om : 2; /**< [ 1: 0](SR/W) Operation mode.
915 0x0 = Single-socket single-root mode.
916 0x1 = Reserved.
917 0x2 = Multisocket single-root mode.
918 0x3 = Multisocket multiroot mode. */
919 #else /* Word 0 - Little Endian */
920 uint64_t om : 2; /**< [ 1: 0](SR/W) Operation mode.
921 0x0 = Single-socket single-root mode.
922 0x1 = Reserved.
923 0x2 = Multisocket single-root mode.
924 0x3 = Multisocket multiroot mode. */
925 uint64_t root_dist : 1; /**< [ 2: 2](SR/W) Specifies whether the distributor on this socket is root.
926 0 = Distributor is not root.
927 1 = Distributor is root.
928
929 Out of reset, this field is set. EL3 firmware will clear this field as required for multi-
930 socket operation. */
931 uint64_t reserved_3 : 1;
932 uint64_t dis_its_dtlb : 1; /**< [ 4: 4](SR/W) Disable ITS DTLB (device table entry lookup buffer). */
933 uint64_t dis_its_itlb : 1; /**< [ 5: 5](SR/W) Disable ITS ITLB (interrupt translation entry lookup buffer). */
934 uint64_t dis_its_cdtc : 1; /**< [ 6: 6](SR/W) Disable 1-entry device table cache in ITS CEU. */
935 uint64_t dis_inv_hct : 1; /**< [ 7: 7](SR/W) Disable HW invalidating ITS HCT during ITS disable process. */
936 uint64_t dis_lpi_cfg_cache : 1; /**< [ 8: 8](SR/W) Disable the LPI configuration cache. */
937 uint64_t dis_lpi_pend_cache : 1; /**< [ 9: 9](SR/W) Disable the LPI pending table cache. */
938 uint64_t reserved_10_31 : 22;
939 uint64_t dis_cpu_if_load_balancer : 1;/**< [ 32: 32](SR/W) Disable the CPU interface load balancer. */
940 uint64_t reserved_33_63 : 31;
941 #endif /* Word 0 - End */
942 } cn88xx;
943 /* struct bdk_gic_cfg_ctlr_s cn83xx; */
944 };
945 typedef union bdk_gic_cfg_ctlr bdk_gic_cfg_ctlr_t;
946
947 #define BDK_GIC_CFG_CTLR BDK_GIC_CFG_CTLR_FUNC()
948 static inline uint64_t BDK_GIC_CFG_CTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_CFG_CTLR_FUNC(void)949 static inline uint64_t BDK_GIC_CFG_CTLR_FUNC(void)
950 {
951 return 0x801000010000ll;
952 }
953
954 #define typedef_BDK_GIC_CFG_CTLR bdk_gic_cfg_ctlr_t
955 #define bustype_BDK_GIC_CFG_CTLR BDK_CSR_TYPE_NCB
956 #define basename_BDK_GIC_CFG_CTLR "GIC_CFG_CTLR"
957 #define device_bar_BDK_GIC_CFG_CTLR 0x0 /* PF_BAR0 */
958 #define busnum_BDK_GIC_CFG_CTLR 0
959 #define arguments_BDK_GIC_CFG_CTLR -1,-1,-1,-1
960
961 /**
962 * Register (NCB) gic_const
963 *
964 * GIC Constants Register
965 * This register contains constant for software discovery.
966 */
967 union bdk_gic_const
968 {
969 uint64_t u;
970 struct bdk_gic_const_s
971 {
972 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
973 uint64_t reserved_0_63 : 64;
974 #else /* Word 0 - Little Endian */
975 uint64_t reserved_0_63 : 64;
976 #endif /* Word 0 - End */
977 } s;
978 /* struct bdk_gic_const_s cn; */
979 };
980 typedef union bdk_gic_const bdk_gic_const_t;
981
982 #define BDK_GIC_CONST BDK_GIC_CONST_FUNC()
983 static inline uint64_t BDK_GIC_CONST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_CONST_FUNC(void)984 static inline uint64_t BDK_GIC_CONST_FUNC(void)
985 {
986 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
987 return 0x801000010088ll;
988 __bdk_csr_fatal("GIC_CONST", 0, 0, 0, 0, 0);
989 }
990
991 #define typedef_BDK_GIC_CONST bdk_gic_const_t
992 #define bustype_BDK_GIC_CONST BDK_CSR_TYPE_NCB
993 #define basename_BDK_GIC_CONST "GIC_CONST"
994 #define device_bar_BDK_GIC_CONST 0x0 /* PF_BAR0 */
995 #define busnum_BDK_GIC_CONST 0
996 #define arguments_BDK_GIC_CONST -1,-1,-1,-1
997
998 /**
999 * Register (NCB) gic_csclk_active_pc
1000 *
1001 * GIC Conditional Sclk Clock Counter Register
1002 * This register counts conditional clocks for power management.
1003 */
1004 union bdk_gic_csclk_active_pc
1005 {
1006 uint64_t u;
1007 struct bdk_gic_csclk_active_pc_s
1008 {
1009 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1010 uint64_t count : 64; /**< [ 63: 0](R/W/H) Count of conditional coprocessor-clock cycles since reset. */
1011 #else /* Word 0 - Little Endian */
1012 uint64_t count : 64; /**< [ 63: 0](R/W/H) Count of conditional coprocessor-clock cycles since reset. */
1013 #endif /* Word 0 - End */
1014 } s;
1015 /* struct bdk_gic_csclk_active_pc_s cn; */
1016 };
1017 typedef union bdk_gic_csclk_active_pc bdk_gic_csclk_active_pc_t;
1018
1019 #define BDK_GIC_CSCLK_ACTIVE_PC BDK_GIC_CSCLK_ACTIVE_PC_FUNC()
1020 static inline uint64_t BDK_GIC_CSCLK_ACTIVE_PC_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_CSCLK_ACTIVE_PC_FUNC(void)1021 static inline uint64_t BDK_GIC_CSCLK_ACTIVE_PC_FUNC(void)
1022 {
1023 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1024 return 0x801000010090ll;
1025 __bdk_csr_fatal("GIC_CSCLK_ACTIVE_PC", 0, 0, 0, 0, 0);
1026 }
1027
1028 #define typedef_BDK_GIC_CSCLK_ACTIVE_PC bdk_gic_csclk_active_pc_t
1029 #define bustype_BDK_GIC_CSCLK_ACTIVE_PC BDK_CSR_TYPE_NCB
1030 #define basename_BDK_GIC_CSCLK_ACTIVE_PC "GIC_CSCLK_ACTIVE_PC"
1031 #define device_bar_BDK_GIC_CSCLK_ACTIVE_PC 0x0 /* PF_BAR0 */
1032 #define busnum_BDK_GIC_CSCLK_ACTIVE_PC 0
1033 #define arguments_BDK_GIC_CSCLK_ACTIVE_PC -1,-1,-1,-1
1034
1035 /**
1036 * Register (NCB) gic_del3t_ctlr
1037 *
1038 * GIC Debug EL3 Trap Secure Control Register
1039 * This register allows disabling the signaling of some DEL3T errors.
1040 */
1041 union bdk_gic_del3t_ctlr
1042 {
1043 uint64_t u;
1044 struct bdk_gic_del3t_ctlr_s
1045 {
1046 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1047 uint64_t reserved_38_63 : 26;
1048 uint64_t del3t_core_id : 6; /**< [ 37: 32](SR/W) Target CoreID for signaling of GIC DEL3T Errors. Legal range is [0,47]. */
1049 uint64_t reserved_0_31 : 32;
1050 #else /* Word 0 - Little Endian */
1051 uint64_t reserved_0_31 : 32;
1052 uint64_t del3t_core_id : 6; /**< [ 37: 32](SR/W) Target CoreID for signaling of GIC DEL3T Errors. Legal range is [0,47]. */
1053 uint64_t reserved_38_63 : 26;
1054 #endif /* Word 0 - End */
1055 } s;
1056 struct bdk_gic_del3t_ctlr_cn8
1057 {
1058 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1059 uint64_t reserved_38_63 : 26;
1060 uint64_t del3t_core_id : 6; /**< [ 37: 32](SR/W) Target CoreID for signaling of GIC DEL3T Errors. Legal range is [0,47]. */
1061 uint64_t reserved_11_31 : 21;
1062 uint64_t del3t_dis : 11; /**< [ 10: 0](SR/W) Disable signaling of DEL3T Errors.
1063 Internal:
1064 for del3t_dis[10:0]=
1065 [ncbr_stdn,ncbr_fill,cic2cic_ig_buf, lpi_cfg_buf,
1066 lip_rmw_buf,
1067 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1068 #else /* Word 0 - Little Endian */
1069 uint64_t del3t_dis : 11; /**< [ 10: 0](SR/W) Disable signaling of DEL3T Errors.
1070 Internal:
1071 for del3t_dis[10:0]=
1072 [ncbr_stdn,ncbr_fill,cic2cic_ig_buf, lpi_cfg_buf,
1073 lip_rmw_buf,
1074 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1075 uint64_t reserved_11_31 : 21;
1076 uint64_t del3t_core_id : 6; /**< [ 37: 32](SR/W) Target CoreID for signaling of GIC DEL3T Errors. Legal range is [0,47]. */
1077 uint64_t reserved_38_63 : 26;
1078 #endif /* Word 0 - End */
1079 } cn8;
1080 struct bdk_gic_del3t_ctlr_cn9
1081 {
1082 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1083 uint64_t reserved_38_63 : 26;
1084 uint64_t del3t_core_id : 6; /**< [ 37: 32](SR/W) Target CoreID for signaling of GIC DEL3T Errors. Legal range is [0,23]. */
1085 uint64_t reserved_11_31 : 21;
1086 uint64_t del3t_dis : 2; /**< [ 10: 9](SR/W) Disable signaling of DEL3T Errors.
1087 Internal:
1088 for del3t_dis[10:9]=
1089 [ncbr_stdn,ncbr_fill] in GIC. */
1090 uint64_t reserved_0_8 : 9;
1091 #else /* Word 0 - Little Endian */
1092 uint64_t reserved_0_8 : 9;
1093 uint64_t del3t_dis : 2; /**< [ 10: 9](SR/W) Disable signaling of DEL3T Errors.
1094 Internal:
1095 for del3t_dis[10:9]=
1096 [ncbr_stdn,ncbr_fill] in GIC. */
1097 uint64_t reserved_11_31 : 21;
1098 uint64_t del3t_core_id : 6; /**< [ 37: 32](SR/W) Target CoreID for signaling of GIC DEL3T Errors. Legal range is [0,23]. */
1099 uint64_t reserved_38_63 : 26;
1100 #endif /* Word 0 - End */
1101 } cn9;
1102 };
1103 typedef union bdk_gic_del3t_ctlr bdk_gic_del3t_ctlr_t;
1104
1105 #define BDK_GIC_DEL3T_CTLR BDK_GIC_DEL3T_CTLR_FUNC()
1106 static inline uint64_t BDK_GIC_DEL3T_CTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_DEL3T_CTLR_FUNC(void)1107 static inline uint64_t BDK_GIC_DEL3T_CTLR_FUNC(void)
1108 {
1109 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
1110 return 0x801000010060ll;
1111 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
1112 return 0x801000010060ll;
1113 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
1114 return 0x801000010060ll;
1115 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1116 return 0x801000010060ll;
1117 __bdk_csr_fatal("GIC_DEL3T_CTLR", 0, 0, 0, 0, 0);
1118 }
1119
1120 #define typedef_BDK_GIC_DEL3T_CTLR bdk_gic_del3t_ctlr_t
1121 #define bustype_BDK_GIC_DEL3T_CTLR BDK_CSR_TYPE_NCB
1122 #define basename_BDK_GIC_DEL3T_CTLR "GIC_DEL3T_CTLR"
1123 #define device_bar_BDK_GIC_DEL3T_CTLR 0x0 /* PF_BAR0 */
1124 #define busnum_BDK_GIC_DEL3T_CTLR 0
1125 #define arguments_BDK_GIC_DEL3T_CTLR -1,-1,-1,-1
1126
1127 /**
1128 * Register (NCB) gic_ecc_ctlr
1129 *
1130 * INTERNAL: GIC Implementation Secure ECC Control Register
1131 *
1132 * This register is reserved for backwards compatibility.
1133 */
1134 union bdk_gic_ecc_ctlr
1135 {
1136 uint64_t u;
1137 struct bdk_gic_ecc_ctlr_s
1138 {
1139 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1140 uint64_t reserved_49_63 : 15;
1141 uint64_t ram_flip1 : 9; /**< [ 48: 40](SR/W) Flip syndrome bits on write. Flip syndrome bits \<1\> on writes to the corresponding ram to
1142 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1143 uint64_t reserved_29_39 : 11;
1144 uint64_t ram_flip0 : 9; /**< [ 28: 20](SR/W) Flip syndrome bits on write. Flip syndrome bits \<0\> on writes to the corresponding ram to
1145 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1146 uint64_t reserved_9_19 : 11;
1147 uint64_t cor_dis : 9; /**< [ 8: 0](SR/W) RAM ECC correction disable.
1148 Internal:
1149 for cor_dis[8:0]= [cic2cic_ig_buf, lpi_cfg_buf,
1150 lip_rmw_buf,
1151 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1152 #else /* Word 0 - Little Endian */
1153 uint64_t cor_dis : 9; /**< [ 8: 0](SR/W) RAM ECC correction disable.
1154 Internal:
1155 for cor_dis[8:0]= [cic2cic_ig_buf, lpi_cfg_buf,
1156 lip_rmw_buf,
1157 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1158 uint64_t reserved_9_19 : 11;
1159 uint64_t ram_flip0 : 9; /**< [ 28: 20](SR/W) Flip syndrome bits on write. Flip syndrome bits \<0\> on writes to the corresponding ram to
1160 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1161 uint64_t reserved_29_39 : 11;
1162 uint64_t ram_flip1 : 9; /**< [ 48: 40](SR/W) Flip syndrome bits on write. Flip syndrome bits \<1\> on writes to the corresponding ram to
1163 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1164 uint64_t reserved_49_63 : 15;
1165 #endif /* Word 0 - End */
1166 } s;
1167 struct bdk_gic_ecc_ctlr_cn8
1168 {
1169 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1170 uint64_t reserved_60_63 : 4;
1171 uint64_t reserved_49_59 : 11;
1172 uint64_t ram_flip1 : 9; /**< [ 48: 40](SR/W) Flip syndrome bits on write. Flip syndrome bits \<1\> on writes to the corresponding ram to
1173 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1174 uint64_t reserved_29_39 : 11;
1175 uint64_t ram_flip0 : 9; /**< [ 28: 20](SR/W) Flip syndrome bits on write. Flip syndrome bits \<0\> on writes to the corresponding ram to
1176 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1177 uint64_t reserved_9_19 : 11;
1178 uint64_t cor_dis : 9; /**< [ 8: 0](SR/W) RAM ECC correction disable.
1179 Internal:
1180 for cor_dis[8:0]= [cic2cic_ig_buf, lpi_cfg_buf,
1181 lip_rmw_buf,
1182 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1183 #else /* Word 0 - Little Endian */
1184 uint64_t cor_dis : 9; /**< [ 8: 0](SR/W) RAM ECC correction disable.
1185 Internal:
1186 for cor_dis[8:0]= [cic2cic_ig_buf, lpi_cfg_buf,
1187 lip_rmw_buf,
1188 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1189 uint64_t reserved_9_19 : 11;
1190 uint64_t ram_flip0 : 9; /**< [ 28: 20](SR/W) Flip syndrome bits on write. Flip syndrome bits \<0\> on writes to the corresponding ram to
1191 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1192 uint64_t reserved_29_39 : 11;
1193 uint64_t ram_flip1 : 9; /**< [ 48: 40](SR/W) Flip syndrome bits on write. Flip syndrome bits \<1\> on writes to the corresponding ram to
1194 test single-bit or double-bit error handling. See COR_DIS bit definitions. */
1195 uint64_t reserved_49_59 : 11;
1196 uint64_t reserved_60_63 : 4;
1197 #endif /* Word 0 - End */
1198 } cn8;
1199 struct bdk_gic_ecc_ctlr_cn9
1200 {
1201 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1202 uint64_t reserved_0_63 : 64;
1203 #else /* Word 0 - Little Endian */
1204 uint64_t reserved_0_63 : 64;
1205 #endif /* Word 0 - End */
1206 } cn9;
1207 };
1208 typedef union bdk_gic_ecc_ctlr bdk_gic_ecc_ctlr_t;
1209
1210 #define BDK_GIC_ECC_CTLR BDK_GIC_ECC_CTLR_FUNC()
1211 static inline uint64_t BDK_GIC_ECC_CTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_ECC_CTLR_FUNC(void)1212 static inline uint64_t BDK_GIC_ECC_CTLR_FUNC(void)
1213 {
1214 return 0x801000010008ll;
1215 }
1216
1217 #define typedef_BDK_GIC_ECC_CTLR bdk_gic_ecc_ctlr_t
1218 #define bustype_BDK_GIC_ECC_CTLR BDK_CSR_TYPE_NCB
1219 #define basename_BDK_GIC_ECC_CTLR "GIC_ECC_CTLR"
1220 #define device_bar_BDK_GIC_ECC_CTLR 0x0 /* PF_BAR0 */
1221 #define busnum_BDK_GIC_ECC_CTLR 0
1222 #define arguments_BDK_GIC_ECC_CTLR -1,-1,-1,-1
1223
1224 /**
1225 * Register (NCB) gic_ecc_int_statusr
1226 *
1227 * GIC Implementation ECC Error Interrupt Status Register
1228 * This register contains the ECC error status for the GIC memories (including ITS and RDB).
1229 */
1230 union bdk_gic_ecc_int_statusr
1231 {
1232 uint64_t u;
1233 struct bdk_gic_ecc_int_statusr_s
1234 {
1235 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1236 uint64_t reserved_41_63 : 23;
1237 uint64_t dbe : 9; /**< [ 40: 32](R/W1C/H) RAM ECC DBE detected.
1238 Internal:
1239 [8:0] = [cic2cic_ig_buf, lpi_cfg_buf, lip_rmw_buf,
1240 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1241 uint64_t reserved_9_31 : 23;
1242 uint64_t sbe : 9; /**< [ 8: 0](R/W1C/H) RAM ECC SBE detected.
1243 Internal:
1244 [8:0] = [cic2cic_ig_buf, lpi_cfg_buf, lip_rmw_buf,
1245 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1246 #else /* Word 0 - Little Endian */
1247 uint64_t sbe : 9; /**< [ 8: 0](R/W1C/H) RAM ECC SBE detected.
1248 Internal:
1249 [8:0] = [cic2cic_ig_buf, lpi_cfg_buf, lip_rmw_buf,
1250 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1251 uint64_t reserved_9_31 : 23;
1252 uint64_t dbe : 9; /**< [ 40: 32](R/W1C/H) RAM ECC DBE detected.
1253 Internal:
1254 [8:0] = [cic2cic_ig_buf, lpi_cfg_buf, lip_rmw_buf,
1255 dtlb_mem,itlb_mem,hct_mem,cqf_mem,rdb_pktf_mem,aprf_mem] in GIC. */
1256 uint64_t reserved_41_63 : 23;
1257 #endif /* Word 0 - End */
1258 } s;
1259 /* struct bdk_gic_ecc_int_statusr_s cn; */
1260 };
1261 typedef union bdk_gic_ecc_int_statusr bdk_gic_ecc_int_statusr_t;
1262
1263 #define BDK_GIC_ECC_INT_STATUSR BDK_GIC_ECC_INT_STATUSR_FUNC()
1264 static inline uint64_t BDK_GIC_ECC_INT_STATUSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_ECC_INT_STATUSR_FUNC(void)1265 static inline uint64_t BDK_GIC_ECC_INT_STATUSR_FUNC(void)
1266 {
1267 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1268 return 0x801000010030ll;
1269 __bdk_csr_fatal("GIC_ECC_INT_STATUSR", 0, 0, 0, 0, 0);
1270 }
1271
1272 #define typedef_BDK_GIC_ECC_INT_STATUSR bdk_gic_ecc_int_statusr_t
1273 #define bustype_BDK_GIC_ECC_INT_STATUSR BDK_CSR_TYPE_NCB
1274 #define basename_BDK_GIC_ECC_INT_STATUSR "GIC_ECC_INT_STATUSR"
1275 #define device_bar_BDK_GIC_ECC_INT_STATUSR 0x0 /* PF_BAR0 */
1276 #define busnum_BDK_GIC_ECC_INT_STATUSR 0
1277 #define arguments_BDK_GIC_ECC_INT_STATUSR -1,-1,-1,-1
1278
1279 /**
1280 * Register (NCB) gic_int_req#_pc
1281 *
1282 * GIC Performance Counter Register
1283 * Index enumerated by GIC_INT_REQ_E.
1284 */
1285 union bdk_gic_int_reqx_pc
1286 {
1287 uint64_t u;
1288 struct bdk_gic_int_reqx_pc_s
1289 {
1290 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1291 uint64_t count : 64; /**< [ 63: 0](R/W/H) Performance count for each register. Increments each time the corresponding register is written. */
1292 #else /* Word 0 - Little Endian */
1293 uint64_t count : 64; /**< [ 63: 0](R/W/H) Performance count for each register. Increments each time the corresponding register is written. */
1294 #endif /* Word 0 - End */
1295 } s;
1296 /* struct bdk_gic_int_reqx_pc_s cn; */
1297 };
1298 typedef union bdk_gic_int_reqx_pc bdk_gic_int_reqx_pc_t;
1299
1300 static inline uint64_t BDK_GIC_INT_REQX_PC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GIC_INT_REQX_PC(unsigned long a)1301 static inline uint64_t BDK_GIC_INT_REQX_PC(unsigned long a)
1302 {
1303 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=6))
1304 return 0x801000010100ll + 8ll * ((a) & 0x7);
1305 __bdk_csr_fatal("GIC_INT_REQX_PC", 1, a, 0, 0, 0);
1306 }
1307
1308 #define typedef_BDK_GIC_INT_REQX_PC(a) bdk_gic_int_reqx_pc_t
1309 #define bustype_BDK_GIC_INT_REQX_PC(a) BDK_CSR_TYPE_NCB
1310 #define basename_BDK_GIC_INT_REQX_PC(a) "GIC_INT_REQX_PC"
1311 #define device_bar_BDK_GIC_INT_REQX_PC(a) 0x0 /* PF_BAR0 */
1312 #define busnum_BDK_GIC_INT_REQX_PC(a) (a)
1313 #define arguments_BDK_GIC_INT_REQX_PC(a) (a),-1,-1,-1
1314
1315 /**
1316 * Register (NCB) gic_rdb_its_if_err_statusr
1317 *
1318 * GIC Redistributor Network ITS Interface Error Status Register
1319 * This register holds the status of errors detected on the redistributor network interface to ITS.
1320 */
1321 union bdk_gic_rdb_its_if_err_statusr
1322 {
1323 uint64_t u;
1324 struct bdk_gic_rdb_its_if_err_statusr_s
1325 {
1326 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1327 uint64_t reserved_62_63 : 2;
1328 uint64_t v : 1; /**< [ 61: 61](R/W1C/H) When set, the command error is valid. */
1329 uint64_t m : 1; /**< [ 60: 60](RO/H) When set, it means multiple errors have happened. It is meaningful only when [V]=1. */
1330 uint64_t reserved_59 : 1;
1331 uint64_t cmd : 3; /**< [ 58: 56](RO/H) ITS Command. Relevant only when [V]=1. Command encodings are
1332 SETLPIR = 0x1,
1333 CLRLPIR = 0x2,
1334 INVLPIR = 0x3,
1335 INVALLR = 0x4,
1336 SYNCR = 0x5,
1337 MOVLPIR = 0x6, and
1338 MOVALLR = 0x7. */
1339 uint64_t reserved_52_55 : 4;
1340 uint64_t err_multi_socket : 1; /**< [ 51: 51](RO/H) Invalid multi-socket message. Relevant only when [V]=1. Indicates incompatibility between
1341 operation mode setting (GIC_CFG_CTLR[OM]) and the ITS message. */
1342 uint64_t err_dest_gicr_id : 1; /**< [ 50: 50](RO/H) Invalid destination GICR (redistributor). Relevant only when [V]=1 and [CMD]=MOVLPIR or MOVALLR. */
1343 uint64_t err_src_gicr_id : 1; /**< [ 49: 49](RO/H) Invalid source GICR (Redistributor). Relevant only when [V]=1. */
1344 uint64_t err_int_id_range : 1; /**< [ 48: 48](RO/H) LPI interrupt ID out of range. Relevant only when [V]=1. */
1345 uint64_t reserved_44_47 : 4;
1346 uint64_t dst_id : 8; /**< [ 43: 36](RO/H) DestID, specified as node_id[1:0], gicr_id[5:0]. Relevant only when [V]=1 and
1347 [CMD]=MOVLPIR or MOVALLR. */
1348 uint64_t src_id : 8; /**< [ 35: 28](RO/H) SourceID, specified as node_id[1:0], gicr_id[5:0]. It is meaningful only when [V]=1. */
1349 uint64_t reserved_20_27 : 8;
1350 uint64_t int_id : 20; /**< [ 19: 0](RO/H) Interrrupt ID in the ITS message (except for INVALLR, SYNCR, MOVALLR). It is meaningful
1351 only when [V]=1. */
1352 #else /* Word 0 - Little Endian */
1353 uint64_t int_id : 20; /**< [ 19: 0](RO/H) Interrrupt ID in the ITS message (except for INVALLR, SYNCR, MOVALLR). It is meaningful
1354 only when [V]=1. */
1355 uint64_t reserved_20_27 : 8;
1356 uint64_t src_id : 8; /**< [ 35: 28](RO/H) SourceID, specified as node_id[1:0], gicr_id[5:0]. It is meaningful only when [V]=1. */
1357 uint64_t dst_id : 8; /**< [ 43: 36](RO/H) DestID, specified as node_id[1:0], gicr_id[5:0]. Relevant only when [V]=1 and
1358 [CMD]=MOVLPIR or MOVALLR. */
1359 uint64_t reserved_44_47 : 4;
1360 uint64_t err_int_id_range : 1; /**< [ 48: 48](RO/H) LPI interrupt ID out of range. Relevant only when [V]=1. */
1361 uint64_t err_src_gicr_id : 1; /**< [ 49: 49](RO/H) Invalid source GICR (Redistributor). Relevant only when [V]=1. */
1362 uint64_t err_dest_gicr_id : 1; /**< [ 50: 50](RO/H) Invalid destination GICR (redistributor). Relevant only when [V]=1 and [CMD]=MOVLPIR or MOVALLR. */
1363 uint64_t err_multi_socket : 1; /**< [ 51: 51](RO/H) Invalid multi-socket message. Relevant only when [V]=1. Indicates incompatibility between
1364 operation mode setting (GIC_CFG_CTLR[OM]) and the ITS message. */
1365 uint64_t reserved_52_55 : 4;
1366 uint64_t cmd : 3; /**< [ 58: 56](RO/H) ITS Command. Relevant only when [V]=1. Command encodings are
1367 SETLPIR = 0x1,
1368 CLRLPIR = 0x2,
1369 INVLPIR = 0x3,
1370 INVALLR = 0x4,
1371 SYNCR = 0x5,
1372 MOVLPIR = 0x6, and
1373 MOVALLR = 0x7. */
1374 uint64_t reserved_59 : 1;
1375 uint64_t m : 1; /**< [ 60: 60](RO/H) When set, it means multiple errors have happened. It is meaningful only when [V]=1. */
1376 uint64_t v : 1; /**< [ 61: 61](R/W1C/H) When set, the command error is valid. */
1377 uint64_t reserved_62_63 : 2;
1378 #endif /* Word 0 - End */
1379 } s;
1380 /* struct bdk_gic_rdb_its_if_err_statusr_s cn; */
1381 };
1382 typedef union bdk_gic_rdb_its_if_err_statusr bdk_gic_rdb_its_if_err_statusr_t;
1383
1384 #define BDK_GIC_RDB_ITS_IF_ERR_STATUSR BDK_GIC_RDB_ITS_IF_ERR_STATUSR_FUNC()
1385 static inline uint64_t BDK_GIC_RDB_ITS_IF_ERR_STATUSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_RDB_ITS_IF_ERR_STATUSR_FUNC(void)1386 static inline uint64_t BDK_GIC_RDB_ITS_IF_ERR_STATUSR_FUNC(void)
1387 {
1388 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
1389 return 0x801000010070ll;
1390 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
1391 return 0x801000010070ll;
1392 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1393 return 0x801000010070ll;
1394 __bdk_csr_fatal("GIC_RDB_ITS_IF_ERR_STATUSR", 0, 0, 0, 0, 0);
1395 }
1396
1397 #define typedef_BDK_GIC_RDB_ITS_IF_ERR_STATUSR bdk_gic_rdb_its_if_err_statusr_t
1398 #define bustype_BDK_GIC_RDB_ITS_IF_ERR_STATUSR BDK_CSR_TYPE_NCB
1399 #define basename_BDK_GIC_RDB_ITS_IF_ERR_STATUSR "GIC_RDB_ITS_IF_ERR_STATUSR"
1400 #define device_bar_BDK_GIC_RDB_ITS_IF_ERR_STATUSR 0x0 /* PF_BAR0 */
1401 #define busnum_BDK_GIC_RDB_ITS_IF_ERR_STATUSR 0
1402 #define arguments_BDK_GIC_RDB_ITS_IF_ERR_STATUSR -1,-1,-1,-1
1403
1404 /**
1405 * Register (NCB) gic_rib_err_adrr
1406 *
1407 * GIC Implementation RIB Error Address Register
1408 * This register holds the address of the first RIB error message.
1409 */
1410 union bdk_gic_rib_err_adrr
1411 {
1412 uint64_t u;
1413 struct bdk_gic_rib_err_adrr_s
1414 {
1415 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1416 uint64_t reserved_36_63 : 28;
1417 uint64_t addr : 34; /**< [ 35: 2](RO/H) Address of the target CSR. It is meaningful only when GIC_RIB_ERR_STATUSR[V] is set. */
1418 uint64_t node : 2; /**< [ 1: 0](RO/H) ID of the target node. It is meaningful only when GIC_RIB_ERR_STATUSR[V] is set. */
1419 #else /* Word 0 - Little Endian */
1420 uint64_t node : 2; /**< [ 1: 0](RO/H) ID of the target node. It is meaningful only when GIC_RIB_ERR_STATUSR[V] is set. */
1421 uint64_t addr : 34; /**< [ 35: 2](RO/H) Address of the target CSR. It is meaningful only when GIC_RIB_ERR_STATUSR[V] is set. */
1422 uint64_t reserved_36_63 : 28;
1423 #endif /* Word 0 - End */
1424 } s;
1425 /* struct bdk_gic_rib_err_adrr_s cn; */
1426 };
1427 typedef union bdk_gic_rib_err_adrr bdk_gic_rib_err_adrr_t;
1428
1429 #define BDK_GIC_RIB_ERR_ADRR BDK_GIC_RIB_ERR_ADRR_FUNC()
1430 static inline uint64_t BDK_GIC_RIB_ERR_ADRR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_RIB_ERR_ADRR_FUNC(void)1431 static inline uint64_t BDK_GIC_RIB_ERR_ADRR_FUNC(void)
1432 {
1433 return 0x801000010048ll;
1434 }
1435
1436 #define typedef_BDK_GIC_RIB_ERR_ADRR bdk_gic_rib_err_adrr_t
1437 #define bustype_BDK_GIC_RIB_ERR_ADRR BDK_CSR_TYPE_NCB
1438 #define basename_BDK_GIC_RIB_ERR_ADRR "GIC_RIB_ERR_ADRR"
1439 #define device_bar_BDK_GIC_RIB_ERR_ADRR 0x0 /* PF_BAR0 */
1440 #define busnum_BDK_GIC_RIB_ERR_ADRR 0
1441 #define arguments_BDK_GIC_RIB_ERR_ADRR -1,-1,-1,-1
1442
1443 /**
1444 * Register (NCB) gic_rib_err_statusr
1445 *
1446 * GIC Implementation RIB Error Status Register
1447 * This register holds the status of the first RIB error message.
1448 */
1449 union bdk_gic_rib_err_statusr
1450 {
1451 uint64_t u;
1452 struct bdk_gic_rib_err_statusr_s
1453 {
1454 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1455 uint64_t reserved_62_63 : 2;
1456 uint64_t v : 1; /**< [ 61: 61](R/W1C/H) When set, the command error is valid. */
1457 uint64_t m : 1; /**< [ 60: 60](RO/H) When set, it means multiple errors have happened. It is meaningful only when [V]=1. */
1458 uint64_t reserved_56_59 : 4;
1459 uint64_t dev_id : 24; /**< [ 55: 32](RO/H) Device ID inside the RIB message. */
1460 uint64_t reserved_29_31 : 3;
1461 uint64_t secure : 1; /**< [ 28: 28](RO/H) Secure bit inside the RIB message. It is meaningful only when V=1. */
1462 uint64_t reserved_20_27 : 8;
1463 uint64_t int_id : 20; /**< [ 19: 0](RO/H) Interrrupt ID inside the RIB message. It is meaningful only when V=1. */
1464 #else /* Word 0 - Little Endian */
1465 uint64_t int_id : 20; /**< [ 19: 0](RO/H) Interrrupt ID inside the RIB message. It is meaningful only when V=1. */
1466 uint64_t reserved_20_27 : 8;
1467 uint64_t secure : 1; /**< [ 28: 28](RO/H) Secure bit inside the RIB message. It is meaningful only when V=1. */
1468 uint64_t reserved_29_31 : 3;
1469 uint64_t dev_id : 24; /**< [ 55: 32](RO/H) Device ID inside the RIB message. */
1470 uint64_t reserved_56_59 : 4;
1471 uint64_t m : 1; /**< [ 60: 60](RO/H) When set, it means multiple errors have happened. It is meaningful only when [V]=1. */
1472 uint64_t v : 1; /**< [ 61: 61](R/W1C/H) When set, the command error is valid. */
1473 uint64_t reserved_62_63 : 2;
1474 #endif /* Word 0 - End */
1475 } s;
1476 struct bdk_gic_rib_err_statusr_cn8
1477 {
1478 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1479 uint64_t reserved_62_63 : 2;
1480 uint64_t v : 1; /**< [ 61: 61](R/W1C/H) When set, the command error is valid. */
1481 uint64_t m : 1; /**< [ 60: 60](RO/H) When set, it means multiple errors have happened. It is meaningful only when [V]=1. */
1482 uint64_t reserved_53_59 : 7;
1483 uint64_t dev_id : 21; /**< [ 52: 32](RO/H) Device ID inside the RIB message. */
1484 uint64_t reserved_29_31 : 3;
1485 uint64_t secure : 1; /**< [ 28: 28](RO/H) Secure bit inside the RIB message. It is meaningful only when V=1. */
1486 uint64_t reserved_20_27 : 8;
1487 uint64_t int_id : 20; /**< [ 19: 0](RO/H) Interrrupt ID inside the RIB message. It is meaningful only when V=1. */
1488 #else /* Word 0 - Little Endian */
1489 uint64_t int_id : 20; /**< [ 19: 0](RO/H) Interrrupt ID inside the RIB message. It is meaningful only when V=1. */
1490 uint64_t reserved_20_27 : 8;
1491 uint64_t secure : 1; /**< [ 28: 28](RO/H) Secure bit inside the RIB message. It is meaningful only when V=1. */
1492 uint64_t reserved_29_31 : 3;
1493 uint64_t dev_id : 21; /**< [ 52: 32](RO/H) Device ID inside the RIB message. */
1494 uint64_t reserved_53_59 : 7;
1495 uint64_t m : 1; /**< [ 60: 60](RO/H) When set, it means multiple errors have happened. It is meaningful only when [V]=1. */
1496 uint64_t v : 1; /**< [ 61: 61](R/W1C/H) When set, the command error is valid. */
1497 uint64_t reserved_62_63 : 2;
1498 #endif /* Word 0 - End */
1499 } cn8;
1500 /* struct bdk_gic_rib_err_statusr_s cn9; */
1501 };
1502 typedef union bdk_gic_rib_err_statusr bdk_gic_rib_err_statusr_t;
1503
1504 #define BDK_GIC_RIB_ERR_STATUSR BDK_GIC_RIB_ERR_STATUSR_FUNC()
1505 static inline uint64_t BDK_GIC_RIB_ERR_STATUSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_RIB_ERR_STATUSR_FUNC(void)1506 static inline uint64_t BDK_GIC_RIB_ERR_STATUSR_FUNC(void)
1507 {
1508 return 0x801000010040ll;
1509 }
1510
1511 #define typedef_BDK_GIC_RIB_ERR_STATUSR bdk_gic_rib_err_statusr_t
1512 #define bustype_BDK_GIC_RIB_ERR_STATUSR BDK_CSR_TYPE_NCB
1513 #define basename_BDK_GIC_RIB_ERR_STATUSR "GIC_RIB_ERR_STATUSR"
1514 #define device_bar_BDK_GIC_RIB_ERR_STATUSR 0x0 /* PF_BAR0 */
1515 #define busnum_BDK_GIC_RIB_ERR_STATUSR 0
1516 #define arguments_BDK_GIC_RIB_ERR_STATUSR -1,-1,-1,-1
1517
1518 /**
1519 * Register (NCB) gic_scratch
1520 *
1521 * GIC Scratch Register
1522 * This is a scratch register.
1523 */
1524 union bdk_gic_scratch
1525 {
1526 uint64_t u;
1527 struct bdk_gic_scratch_s
1528 {
1529 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1530 uint64_t data : 64; /**< [ 63: 0](R/W) This is a scratch register. Reads and writes of this register have no side effects. */
1531 #else /* Word 0 - Little Endian */
1532 uint64_t data : 64; /**< [ 63: 0](R/W) This is a scratch register. Reads and writes of this register have no side effects. */
1533 #endif /* Word 0 - End */
1534 } s;
1535 /* struct bdk_gic_scratch_s cn; */
1536 };
1537 typedef union bdk_gic_scratch bdk_gic_scratch_t;
1538
1539 #define BDK_GIC_SCRATCH BDK_GIC_SCRATCH_FUNC()
1540 static inline uint64_t BDK_GIC_SCRATCH_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_SCRATCH_FUNC(void)1541 static inline uint64_t BDK_GIC_SCRATCH_FUNC(void)
1542 {
1543 return 0x801000010080ll;
1544 }
1545
1546 #define typedef_BDK_GIC_SCRATCH bdk_gic_scratch_t
1547 #define bustype_BDK_GIC_SCRATCH BDK_CSR_TYPE_NCB
1548 #define basename_BDK_GIC_SCRATCH "GIC_SCRATCH"
1549 #define device_bar_BDK_GIC_SCRATCH 0x0 /* PF_BAR0 */
1550 #define busnum_BDK_GIC_SCRATCH 0
1551 #define arguments_BDK_GIC_SCRATCH -1,-1,-1,-1
1552
1553 /**
1554 * Register (NCB) gic_sync_cfg
1555 *
1556 * GIC SYNC Configuration Register
1557 * This register configures the behavior of ITS SYNC command.
1558 */
1559 union bdk_gic_sync_cfg
1560 {
1561 uint64_t u;
1562 struct bdk_gic_sync_cfg_s
1563 {
1564 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1565 uint64_t te : 1; /**< [ 63: 63](R/W) Translation enable. If set, there is interrupt translation is enabled during
1566 sync command execution. If clear, interrupt translation is disabled during sync
1567 command execution. */
1568 uint64_t reserved_32_62 : 31;
1569 uint64_t tol : 32; /**< [ 31: 0](R/W) Time out limit. Timeout wait period for the ITS SYNC command. SYNC command will
1570 wait for ACK from a GICR for at most [TOL] system-clock cycles. If ACK is not
1571 received within [TOL] system-clock cycles, SYNC is timed out and considered
1572 done. [TOL] = 0x0 means SYNC timeout scheme is not used and SYNC command always
1573 waits for ACK. */
1574 #else /* Word 0 - Little Endian */
1575 uint64_t tol : 32; /**< [ 31: 0](R/W) Time out limit. Timeout wait period for the ITS SYNC command. SYNC command will
1576 wait for ACK from a GICR for at most [TOL] system-clock cycles. If ACK is not
1577 received within [TOL] system-clock cycles, SYNC is timed out and considered
1578 done. [TOL] = 0x0 means SYNC timeout scheme is not used and SYNC command always
1579 waits for ACK. */
1580 uint64_t reserved_32_62 : 31;
1581 uint64_t te : 1; /**< [ 63: 63](R/W) Translation enable. If set, there is interrupt translation is enabled during
1582 sync command execution. If clear, interrupt translation is disabled during sync
1583 command execution. */
1584 #endif /* Word 0 - End */
1585 } s;
1586 /* struct bdk_gic_sync_cfg_s cn; */
1587 };
1588 typedef union bdk_gic_sync_cfg bdk_gic_sync_cfg_t;
1589
1590 #define BDK_GIC_SYNC_CFG BDK_GIC_SYNC_CFG_FUNC()
1591 static inline uint64_t BDK_GIC_SYNC_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GIC_SYNC_CFG_FUNC(void)1592 static inline uint64_t BDK_GIC_SYNC_CFG_FUNC(void)
1593 {
1594 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
1595 return 0x801000010050ll;
1596 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
1597 return 0x801000010050ll;
1598 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
1599 return 0x801000010050ll;
1600 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1601 return 0x801000010050ll;
1602 __bdk_csr_fatal("GIC_SYNC_CFG", 0, 0, 0, 0, 0);
1603 }
1604
1605 #define typedef_BDK_GIC_SYNC_CFG bdk_gic_sync_cfg_t
1606 #define bustype_BDK_GIC_SYNC_CFG BDK_CSR_TYPE_NCB
1607 #define basename_BDK_GIC_SYNC_CFG "GIC_SYNC_CFG"
1608 #define device_bar_BDK_GIC_SYNC_CFG 0x0 /* PF_BAR0 */
1609 #define busnum_BDK_GIC_SYNC_CFG 0
1610 #define arguments_BDK_GIC_SYNC_CFG -1,-1,-1,-1
1611
1612 /**
1613 * Register (NCB32b) gicd_cidr0
1614 *
1615 * GIC Distributor Component Identification Register 0
1616 */
1617 union bdk_gicd_cidr0
1618 {
1619 uint32_t u;
1620 struct bdk_gicd_cidr0_s
1621 {
1622 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1623 uint32_t reserved_8_31 : 24;
1624 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1625 #else /* Word 0 - Little Endian */
1626 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1627 uint32_t reserved_8_31 : 24;
1628 #endif /* Word 0 - End */
1629 } s;
1630 /* struct bdk_gicd_cidr0_s cn; */
1631 };
1632 typedef union bdk_gicd_cidr0 bdk_gicd_cidr0_t;
1633
1634 #define BDK_GICD_CIDR0 BDK_GICD_CIDR0_FUNC()
1635 static inline uint64_t BDK_GICD_CIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_CIDR0_FUNC(void)1636 static inline uint64_t BDK_GICD_CIDR0_FUNC(void)
1637 {
1638 return 0x80100000fff0ll;
1639 }
1640
1641 #define typedef_BDK_GICD_CIDR0 bdk_gicd_cidr0_t
1642 #define bustype_BDK_GICD_CIDR0 BDK_CSR_TYPE_NCB32b
1643 #define basename_BDK_GICD_CIDR0 "GICD_CIDR0"
1644 #define device_bar_BDK_GICD_CIDR0 0x0 /* PF_BAR0 */
1645 #define busnum_BDK_GICD_CIDR0 0
1646 #define arguments_BDK_GICD_CIDR0 -1,-1,-1,-1
1647
1648 /**
1649 * Register (NCB32b) gicd_cidr1
1650 *
1651 * GIC Distributor Component Identification Register 1
1652 */
1653 union bdk_gicd_cidr1
1654 {
1655 uint32_t u;
1656 struct bdk_gicd_cidr1_s
1657 {
1658 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1659 uint32_t reserved_8_31 : 24;
1660 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1661 #else /* Word 0 - Little Endian */
1662 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1663 uint32_t reserved_8_31 : 24;
1664 #endif /* Word 0 - End */
1665 } s;
1666 /* struct bdk_gicd_cidr1_s cn; */
1667 };
1668 typedef union bdk_gicd_cidr1 bdk_gicd_cidr1_t;
1669
1670 #define BDK_GICD_CIDR1 BDK_GICD_CIDR1_FUNC()
1671 static inline uint64_t BDK_GICD_CIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_CIDR1_FUNC(void)1672 static inline uint64_t BDK_GICD_CIDR1_FUNC(void)
1673 {
1674 return 0x80100000fff4ll;
1675 }
1676
1677 #define typedef_BDK_GICD_CIDR1 bdk_gicd_cidr1_t
1678 #define bustype_BDK_GICD_CIDR1 BDK_CSR_TYPE_NCB32b
1679 #define basename_BDK_GICD_CIDR1 "GICD_CIDR1"
1680 #define device_bar_BDK_GICD_CIDR1 0x0 /* PF_BAR0 */
1681 #define busnum_BDK_GICD_CIDR1 0
1682 #define arguments_BDK_GICD_CIDR1 -1,-1,-1,-1
1683
1684 /**
1685 * Register (NCB32b) gicd_cidr2
1686 *
1687 * GIC Distributor Component Identification Register 2
1688 */
1689 union bdk_gicd_cidr2
1690 {
1691 uint32_t u;
1692 struct bdk_gicd_cidr2_s
1693 {
1694 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1695 uint32_t reserved_8_31 : 24;
1696 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1697 #else /* Word 0 - Little Endian */
1698 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1699 uint32_t reserved_8_31 : 24;
1700 #endif /* Word 0 - End */
1701 } s;
1702 /* struct bdk_gicd_cidr2_s cn; */
1703 };
1704 typedef union bdk_gicd_cidr2 bdk_gicd_cidr2_t;
1705
1706 #define BDK_GICD_CIDR2 BDK_GICD_CIDR2_FUNC()
1707 static inline uint64_t BDK_GICD_CIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_CIDR2_FUNC(void)1708 static inline uint64_t BDK_GICD_CIDR2_FUNC(void)
1709 {
1710 return 0x80100000fff8ll;
1711 }
1712
1713 #define typedef_BDK_GICD_CIDR2 bdk_gicd_cidr2_t
1714 #define bustype_BDK_GICD_CIDR2 BDK_CSR_TYPE_NCB32b
1715 #define basename_BDK_GICD_CIDR2 "GICD_CIDR2"
1716 #define device_bar_BDK_GICD_CIDR2 0x0 /* PF_BAR0 */
1717 #define busnum_BDK_GICD_CIDR2 0
1718 #define arguments_BDK_GICD_CIDR2 -1,-1,-1,-1
1719
1720 /**
1721 * Register (NCB32b) gicd_cidr3
1722 *
1723 * GIC Distributor Component Identification Register 3
1724 */
1725 union bdk_gicd_cidr3
1726 {
1727 uint32_t u;
1728 struct bdk_gicd_cidr3_s
1729 {
1730 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1731 uint32_t reserved_8_31 : 24;
1732 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1733 #else /* Word 0 - Little Endian */
1734 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1735 uint32_t reserved_8_31 : 24;
1736 #endif /* Word 0 - End */
1737 } s;
1738 /* struct bdk_gicd_cidr3_s cn; */
1739 };
1740 typedef union bdk_gicd_cidr3 bdk_gicd_cidr3_t;
1741
1742 #define BDK_GICD_CIDR3 BDK_GICD_CIDR3_FUNC()
1743 static inline uint64_t BDK_GICD_CIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_CIDR3_FUNC(void)1744 static inline uint64_t BDK_GICD_CIDR3_FUNC(void)
1745 {
1746 return 0x80100000fffcll;
1747 }
1748
1749 #define typedef_BDK_GICD_CIDR3 bdk_gicd_cidr3_t
1750 #define bustype_BDK_GICD_CIDR3 BDK_CSR_TYPE_NCB32b
1751 #define basename_BDK_GICD_CIDR3 "GICD_CIDR3"
1752 #define device_bar_BDK_GICD_CIDR3 0x0 /* PF_BAR0 */
1753 #define busnum_BDK_GICD_CIDR3 0
1754 #define arguments_BDK_GICD_CIDR3 -1,-1,-1,-1
1755
1756 /**
1757 * Register (NCB32b) gicd_clrspi_nsr
1758 *
1759 * GIC Distributor Clear SPI Pending Register
1760 */
1761 union bdk_gicd_clrspi_nsr
1762 {
1763 uint32_t u;
1764 struct bdk_gicd_clrspi_nsr_s
1765 {
1766 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1767 uint32_t reserved_10_31 : 22;
1768 uint32_t spi_id : 10; /**< [ 9: 0](WO) Clear an SPI pending state (write-only). If the SPI is not pending, then the write has no
1769 effect.
1770
1771 If the SPI ID is invalid, then the write has no effect.
1772
1773 If the register is written using a nonsecure access and the value specifies a secure SPI
1774 and the value of the corresponding GICD_NSACR() register is less than 0x2 (i.e. does not
1775 permit nonsecure accesses to clear the interrupt pending state), the write has no effect. */
1776 #else /* Word 0 - Little Endian */
1777 uint32_t spi_id : 10; /**< [ 9: 0](WO) Clear an SPI pending state (write-only). If the SPI is not pending, then the write has no
1778 effect.
1779
1780 If the SPI ID is invalid, then the write has no effect.
1781
1782 If the register is written using a nonsecure access and the value specifies a secure SPI
1783 and the value of the corresponding GICD_NSACR() register is less than 0x2 (i.e. does not
1784 permit nonsecure accesses to clear the interrupt pending state), the write has no effect. */
1785 uint32_t reserved_10_31 : 22;
1786 #endif /* Word 0 - End */
1787 } s;
1788 /* struct bdk_gicd_clrspi_nsr_s cn; */
1789 };
1790 typedef union bdk_gicd_clrspi_nsr bdk_gicd_clrspi_nsr_t;
1791
1792 #define BDK_GICD_CLRSPI_NSR BDK_GICD_CLRSPI_NSR_FUNC()
1793 static inline uint64_t BDK_GICD_CLRSPI_NSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_CLRSPI_NSR_FUNC(void)1794 static inline uint64_t BDK_GICD_CLRSPI_NSR_FUNC(void)
1795 {
1796 return 0x801000000048ll;
1797 }
1798
1799 #define typedef_BDK_GICD_CLRSPI_NSR bdk_gicd_clrspi_nsr_t
1800 #define bustype_BDK_GICD_CLRSPI_NSR BDK_CSR_TYPE_NCB32b
1801 #define basename_BDK_GICD_CLRSPI_NSR "GICD_CLRSPI_NSR"
1802 #define device_bar_BDK_GICD_CLRSPI_NSR 0x0 /* PF_BAR0 */
1803 #define busnum_BDK_GICD_CLRSPI_NSR 0
1804 #define arguments_BDK_GICD_CLRSPI_NSR -1,-1,-1,-1
1805
1806 /**
1807 * Register (NCB32b) gicd_clrspi_sr
1808 *
1809 * GIC Distributor Clear Secure SPI Pending Register
1810 */
1811 union bdk_gicd_clrspi_sr
1812 {
1813 uint32_t u;
1814 struct bdk_gicd_clrspi_sr_s
1815 {
1816 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1817 uint32_t reserved_10_31 : 22;
1818 uint32_t spi_id : 10; /**< [ 9: 0](SWO) Clear an SPI pending state (write-only). If the SPI is not pending, then the write has no
1819 effect.
1820
1821 If the SPI ID is invalid, then the write has no effect.
1822
1823 If the register is written using a nonsecure access, the write has no effect. */
1824 #else /* Word 0 - Little Endian */
1825 uint32_t spi_id : 10; /**< [ 9: 0](SWO) Clear an SPI pending state (write-only). If the SPI is not pending, then the write has no
1826 effect.
1827
1828 If the SPI ID is invalid, then the write has no effect.
1829
1830 If the register is written using a nonsecure access, the write has no effect. */
1831 uint32_t reserved_10_31 : 22;
1832 #endif /* Word 0 - End */
1833 } s;
1834 /* struct bdk_gicd_clrspi_sr_s cn; */
1835 };
1836 typedef union bdk_gicd_clrspi_sr bdk_gicd_clrspi_sr_t;
1837
1838 #define BDK_GICD_CLRSPI_SR BDK_GICD_CLRSPI_SR_FUNC()
1839 static inline uint64_t BDK_GICD_CLRSPI_SR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_CLRSPI_SR_FUNC(void)1840 static inline uint64_t BDK_GICD_CLRSPI_SR_FUNC(void)
1841 {
1842 return 0x801000000058ll;
1843 }
1844
1845 #define typedef_BDK_GICD_CLRSPI_SR bdk_gicd_clrspi_sr_t
1846 #define bustype_BDK_GICD_CLRSPI_SR BDK_CSR_TYPE_NCB32b
1847 #define basename_BDK_GICD_CLRSPI_SR "GICD_CLRSPI_SR"
1848 #define device_bar_BDK_GICD_CLRSPI_SR 0x0 /* PF_BAR0 */
1849 #define busnum_BDK_GICD_CLRSPI_SR 0
1850 #define arguments_BDK_GICD_CLRSPI_SR -1,-1,-1,-1
1851
1852 /**
1853 * Register (NCB32b) gicd_icactiver#
1854 *
1855 * GIC Distributor Interrupt Clear-Active Registers
1856 * Each bit in this register provides a clear-active bit for each SPI supported by the GIC.
1857 * Writing one to a clear-active bit clears the active status of the corresponding SPI.
1858 */
1859 union bdk_gicd_icactiverx
1860 {
1861 uint32_t u;
1862 struct bdk_gicd_icactiverx_s
1863 {
1864 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1865 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
1866 SPI
1867 is not active. If read as one, the SPI is in active state.
1868
1869 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
1870 may only be set by secure accesses.
1871
1872 A clear-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
1873 #else /* Word 0 - Little Endian */
1874 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
1875 SPI
1876 is not active. If read as one, the SPI is in active state.
1877
1878 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
1879 may only be set by secure accesses.
1880
1881 A clear-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
1882 #endif /* Word 0 - End */
1883 } s;
1884 struct bdk_gicd_icactiverx_cn9
1885 {
1886 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1887 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
1888 SPI
1889 is not active. If read as one, the SPI is in active state.
1890
1891 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
1892 may only be set by secure accesses.
1893
1894 A clear-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
1895 #else /* Word 0 - Little Endian */
1896 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
1897 SPI
1898 is not active. If read as one, the SPI is in active state.
1899
1900 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
1901 may only be set by secure accesses.
1902
1903 A clear-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
1904 #endif /* Word 0 - End */
1905 } cn9;
1906 /* struct bdk_gicd_icactiverx_cn9 cn81xx; */
1907 /* struct bdk_gicd_icactiverx_s cn88xx; */
1908 /* struct bdk_gicd_icactiverx_cn9 cn83xx; */
1909 };
1910 typedef union bdk_gicd_icactiverx bdk_gicd_icactiverx_t;
1911
1912 static inline uint64_t BDK_GICD_ICACTIVERX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ICACTIVERX(unsigned long a)1913 static inline uint64_t BDK_GICD_ICACTIVERX(unsigned long a)
1914 {
1915 if ((a>=1)&&(a<=4))
1916 return 0x801000000380ll + 4ll * ((a) & 0x7);
1917 __bdk_csr_fatal("GICD_ICACTIVERX", 1, a, 0, 0, 0);
1918 }
1919
1920 #define typedef_BDK_GICD_ICACTIVERX(a) bdk_gicd_icactiverx_t
1921 #define bustype_BDK_GICD_ICACTIVERX(a) BDK_CSR_TYPE_NCB32b
1922 #define basename_BDK_GICD_ICACTIVERX(a) "GICD_ICACTIVERX"
1923 #define device_bar_BDK_GICD_ICACTIVERX(a) 0x0 /* PF_BAR0 */
1924 #define busnum_BDK_GICD_ICACTIVERX(a) (a)
1925 #define arguments_BDK_GICD_ICACTIVERX(a) (a),-1,-1,-1
1926
1927 /**
1928 * Register (NCB32b) gicd_icenabler#
1929 *
1930 * GIC Distributor Interrupt Clear-Enable Registers
1931 * Each bit in GICD_ICENABLER() provides a clear-enable bit for each SPI supported by the GIC.
1932 * Writing one to a clear-enable bit disables forwarding of the corresponding SPI from the
1933 * distributor to the CPU interfaces. Reading a bit identifies whether the SPI is enabled.
1934 */
1935 union bdk_gicd_icenablerx
1936 {
1937 uint32_t u;
1938 struct bdk_gicd_icenablerx_s
1939 {
1940 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1941 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SPI for SPI IDs in the range 159..32. Upon reading, if a bit is
1942 zero, then the SPI is not enabled to be forwarded to the CPU interface. Upon reading, if a
1943 bit is one, the SPI is enabled to be forwarded to the CPU interface. Clear-enable bits
1944 corresponding to secure interrupts (either group 0 or group 1) may only be set by secure
1945 accesses.
1946
1947 Writes to the register cannot be considered complete until the effects of the write are
1948 visible throughout the affinity hierarchy. To ensure that an enable has been cleared,
1949 software must write to this register with bits set to clear the required enables. Software
1950 must then poll GICD_(S)CTLR[RWP] (register writes pending) until it has the value zero. */
1951 #else /* Word 0 - Little Endian */
1952 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SPI for SPI IDs in the range 159..32. Upon reading, if a bit is
1953 zero, then the SPI is not enabled to be forwarded to the CPU interface. Upon reading, if a
1954 bit is one, the SPI is enabled to be forwarded to the CPU interface. Clear-enable bits
1955 corresponding to secure interrupts (either group 0 or group 1) may only be set by secure
1956 accesses.
1957
1958 Writes to the register cannot be considered complete until the effects of the write are
1959 visible throughout the affinity hierarchy. To ensure that an enable has been cleared,
1960 software must write to this register with bits set to clear the required enables. Software
1961 must then poll GICD_(S)CTLR[RWP] (register writes pending) until it has the value zero. */
1962 #endif /* Word 0 - End */
1963 } s;
1964 /* struct bdk_gicd_icenablerx_s cn; */
1965 };
1966 typedef union bdk_gicd_icenablerx bdk_gicd_icenablerx_t;
1967
1968 static inline uint64_t BDK_GICD_ICENABLERX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ICENABLERX(unsigned long a)1969 static inline uint64_t BDK_GICD_ICENABLERX(unsigned long a)
1970 {
1971 if ((a>=1)&&(a<=4))
1972 return 0x801000000180ll + 4ll * ((a) & 0x7);
1973 __bdk_csr_fatal("GICD_ICENABLERX", 1, a, 0, 0, 0);
1974 }
1975
1976 #define typedef_BDK_GICD_ICENABLERX(a) bdk_gicd_icenablerx_t
1977 #define bustype_BDK_GICD_ICENABLERX(a) BDK_CSR_TYPE_NCB32b
1978 #define basename_BDK_GICD_ICENABLERX(a) "GICD_ICENABLERX"
1979 #define device_bar_BDK_GICD_ICENABLERX(a) 0x0 /* PF_BAR0 */
1980 #define busnum_BDK_GICD_ICENABLERX(a) (a)
1981 #define arguments_BDK_GICD_ICENABLERX(a) (a),-1,-1,-1
1982
1983 /**
1984 * Register (NCB32b) gicd_icfgr#
1985 *
1986 * GIC Distributor SPI Configuration Registers
1987 */
1988 union bdk_gicd_icfgrx
1989 {
1990 uint32_t u;
1991 struct bdk_gicd_icfgrx_s
1992 {
1993 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1994 uint32_t vec : 32; /**< [ 31: 0](R/W) Two bits per SPI. Defines whether an SPI is level-sensitive or edge-triggered.
1995 Bit[1] is zero, the SPI is level-sensitive.
1996 Bit[1] is one, the SPI is edge-triggered.
1997 Bit[0] Reserved.
1998
1999 If SPI is a secure interrupt, then its corresponding field is RAZ/WI to nonsecure
2000 accesses. */
2001 #else /* Word 0 - Little Endian */
2002 uint32_t vec : 32; /**< [ 31: 0](R/W) Two bits per SPI. Defines whether an SPI is level-sensitive or edge-triggered.
2003 Bit[1] is zero, the SPI is level-sensitive.
2004 Bit[1] is one, the SPI is edge-triggered.
2005 Bit[0] Reserved.
2006
2007 If SPI is a secure interrupt, then its corresponding field is RAZ/WI to nonsecure
2008 accesses. */
2009 #endif /* Word 0 - End */
2010 } s;
2011 /* struct bdk_gicd_icfgrx_s cn; */
2012 };
2013 typedef union bdk_gicd_icfgrx bdk_gicd_icfgrx_t;
2014
2015 static inline uint64_t BDK_GICD_ICFGRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ICFGRX(unsigned long a)2016 static inline uint64_t BDK_GICD_ICFGRX(unsigned long a)
2017 {
2018 if ((a>=2)&&(a<=9))
2019 return 0x801000000c00ll + 4ll * ((a) & 0xf);
2020 __bdk_csr_fatal("GICD_ICFGRX", 1, a, 0, 0, 0);
2021 }
2022
2023 #define typedef_BDK_GICD_ICFGRX(a) bdk_gicd_icfgrx_t
2024 #define bustype_BDK_GICD_ICFGRX(a) BDK_CSR_TYPE_NCB32b
2025 #define basename_BDK_GICD_ICFGRX(a) "GICD_ICFGRX"
2026 #define device_bar_BDK_GICD_ICFGRX(a) 0x0 /* PF_BAR0 */
2027 #define busnum_BDK_GICD_ICFGRX(a) (a)
2028 #define arguments_BDK_GICD_ICFGRX(a) (a),-1,-1,-1
2029
2030 /**
2031 * Register (NCB32b) gicd_icpendr#
2032 *
2033 * GIC Distributor Interrupt Clear-Pending Registers
2034 * Each bit in GICD_ICPENDR() provides a clear-pending bit for each SPI supported by the GIC.
2035 * Writing one to a clear-pending bit clears the pending status of the corresponding SPI.
2036 */
2037 union bdk_gicd_icpendrx
2038 {
2039 uint32_t u;
2040 struct bdk_gicd_icpendrx_s
2041 {
2042 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2043 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2044 SPI
2045 is not pending. If read as one, the SPI is in pending state.
2046
2047 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
2048 be set by secure accesses.
2049
2050 A clear-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2051 #else /* Word 0 - Little Endian */
2052 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2053 SPI
2054 is not pending. If read as one, the SPI is in pending state.
2055
2056 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
2057 be set by secure accesses.
2058
2059 A clear-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2060 #endif /* Word 0 - End */
2061 } s;
2062 struct bdk_gicd_icpendrx_cn9
2063 {
2064 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2065 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2066 SPI
2067 is not pending. If read as one, the SPI is in pending state.
2068
2069 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
2070 be set by secure accesses.
2071
2072 A clear-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2073 #else /* Word 0 - Little Endian */
2074 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2075 SPI
2076 is not pending. If read as one, the SPI is in pending state.
2077
2078 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
2079 be set by secure accesses.
2080
2081 A clear-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2082 #endif /* Word 0 - End */
2083 } cn9;
2084 /* struct bdk_gicd_icpendrx_cn9 cn81xx; */
2085 /* struct bdk_gicd_icpendrx_s cn88xx; */
2086 /* struct bdk_gicd_icpendrx_cn9 cn83xx; */
2087 };
2088 typedef union bdk_gicd_icpendrx bdk_gicd_icpendrx_t;
2089
2090 static inline uint64_t BDK_GICD_ICPENDRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ICPENDRX(unsigned long a)2091 static inline uint64_t BDK_GICD_ICPENDRX(unsigned long a)
2092 {
2093 if ((a>=1)&&(a<=4))
2094 return 0x801000000280ll + 4ll * ((a) & 0x7);
2095 __bdk_csr_fatal("GICD_ICPENDRX", 1, a, 0, 0, 0);
2096 }
2097
2098 #define typedef_BDK_GICD_ICPENDRX(a) bdk_gicd_icpendrx_t
2099 #define bustype_BDK_GICD_ICPENDRX(a) BDK_CSR_TYPE_NCB32b
2100 #define basename_BDK_GICD_ICPENDRX(a) "GICD_ICPENDRX"
2101 #define device_bar_BDK_GICD_ICPENDRX(a) 0x0 /* PF_BAR0 */
2102 #define busnum_BDK_GICD_ICPENDRX(a) (a)
2103 #define arguments_BDK_GICD_ICPENDRX(a) (a),-1,-1,-1
2104
2105 /**
2106 * Register (NCB32b) gicd_igroupr#
2107 *
2108 * GIC Distributor Secure Interrupt Group Registers
2109 * The bit in this register for a particular SPI is concatenated with the corresponding
2110 * bit for that SPI in GICD_IGRPMODR() to form a two-bit field that defines the
2111 * interrupt group (G0S, G1S, G1NS) for that SPI.
2112 */
2113 union bdk_gicd_igrouprx
2114 {
2115 uint32_t u;
2116 struct bdk_gicd_igrouprx_s
2117 {
2118 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2119 uint32_t vec : 32; /**< [ 31: 0](SR/W) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If zero, then the SPI is
2120 secure. If one, the SPI is nonsecure. */
2121 #else /* Word 0 - Little Endian */
2122 uint32_t vec : 32; /**< [ 31: 0](SR/W) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If zero, then the SPI is
2123 secure. If one, the SPI is nonsecure. */
2124 #endif /* Word 0 - End */
2125 } s;
2126 /* struct bdk_gicd_igrouprx_s cn; */
2127 };
2128 typedef union bdk_gicd_igrouprx bdk_gicd_igrouprx_t;
2129
2130 static inline uint64_t BDK_GICD_IGROUPRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_IGROUPRX(unsigned long a)2131 static inline uint64_t BDK_GICD_IGROUPRX(unsigned long a)
2132 {
2133 if ((a>=1)&&(a<=4))
2134 return 0x801000000080ll + 4ll * ((a) & 0x7);
2135 __bdk_csr_fatal("GICD_IGROUPRX", 1, a, 0, 0, 0);
2136 }
2137
2138 #define typedef_BDK_GICD_IGROUPRX(a) bdk_gicd_igrouprx_t
2139 #define bustype_BDK_GICD_IGROUPRX(a) BDK_CSR_TYPE_NCB32b
2140 #define basename_BDK_GICD_IGROUPRX(a) "GICD_IGROUPRX"
2141 #define device_bar_BDK_GICD_IGROUPRX(a) 0x0 /* PF_BAR0 */
2142 #define busnum_BDK_GICD_IGROUPRX(a) (a)
2143 #define arguments_BDK_GICD_IGROUPRX(a) (a),-1,-1,-1
2144
2145 /**
2146 * Register (NCB32b) gicd_igrpmodr#
2147 *
2148 * GIC Distributor Interrupt Group Modifier Secure Registers
2149 * The bit in this register for a particular SPI is concatenated with the
2150 * corresponding bit for that SPI in GICD_IGROUPR() to form a two-bit field that defines
2151 * the interrupt group (G0S, G1S, G1NS) for that SPI.
2152 */
2153 union bdk_gicd_igrpmodrx
2154 {
2155 uint32_t u;
2156 struct bdk_gicd_igrpmodrx_s
2157 {
2158 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2159 uint32_t vec : 32; /**< [ 31: 0](SR/W) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If zero, then
2160 the SPI group is not modified. If one, then the SPI group is modified from group
2161 0 to secure group 1. */
2162 #else /* Word 0 - Little Endian */
2163 uint32_t vec : 32; /**< [ 31: 0](SR/W) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If zero, then
2164 the SPI group is not modified. If one, then the SPI group is modified from group
2165 0 to secure group 1. */
2166 #endif /* Word 0 - End */
2167 } s;
2168 /* struct bdk_gicd_igrpmodrx_s cn; */
2169 };
2170 typedef union bdk_gicd_igrpmodrx bdk_gicd_igrpmodrx_t;
2171
2172 static inline uint64_t BDK_GICD_IGRPMODRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_IGRPMODRX(unsigned long a)2173 static inline uint64_t BDK_GICD_IGRPMODRX(unsigned long a)
2174 {
2175 if ((a>=1)&&(a<=4))
2176 return 0x801000000d00ll + 4ll * ((a) & 0x7);
2177 __bdk_csr_fatal("GICD_IGRPMODRX", 1, a, 0, 0, 0);
2178 }
2179
2180 #define typedef_BDK_GICD_IGRPMODRX(a) bdk_gicd_igrpmodrx_t
2181 #define bustype_BDK_GICD_IGRPMODRX(a) BDK_CSR_TYPE_NCB32b
2182 #define basename_BDK_GICD_IGRPMODRX(a) "GICD_IGRPMODRX"
2183 #define device_bar_BDK_GICD_IGRPMODRX(a) 0x0 /* PF_BAR0 */
2184 #define busnum_BDK_GICD_IGRPMODRX(a) (a)
2185 #define arguments_BDK_GICD_IGRPMODRX(a) (a),-1,-1,-1
2186
2187 /**
2188 * Register (NCB32b) gicd_iidr
2189 *
2190 * GIC Distributor Implementation Identification Register
2191 * This 32-bit register is read-only and specifies the version and features supported by the
2192 * distributor.
2193 */
2194 union bdk_gicd_iidr
2195 {
2196 uint32_t u;
2197 struct bdk_gicd_iidr_s
2198 {
2199 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2200 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
2201 In CNXXXX, enumerated by PCC_PROD_E. */
2202 uint32_t reserved_20_23 : 4;
2203 uint32_t variant : 4; /**< [ 19: 16](RO) Indicates the major revision or variant of the product.
2204 On CNXXXX, this is the major revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
2205 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
2206 On CNXXXX, this is the minor revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
2207 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer:
2208 0x34C = Cavium. */
2209 #else /* Word 0 - Little Endian */
2210 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer:
2211 0x34C = Cavium. */
2212 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
2213 On CNXXXX, this is the minor revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
2214 uint32_t variant : 4; /**< [ 19: 16](RO) Indicates the major revision or variant of the product.
2215 On CNXXXX, this is the major revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
2216 uint32_t reserved_20_23 : 4;
2217 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
2218 In CNXXXX, enumerated by PCC_PROD_E. */
2219 #endif /* Word 0 - End */
2220 } s;
2221 /* struct bdk_gicd_iidr_s cn; */
2222 };
2223 typedef union bdk_gicd_iidr bdk_gicd_iidr_t;
2224
2225 #define BDK_GICD_IIDR BDK_GICD_IIDR_FUNC()
2226 static inline uint64_t BDK_GICD_IIDR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_IIDR_FUNC(void)2227 static inline uint64_t BDK_GICD_IIDR_FUNC(void)
2228 {
2229 return 0x801000000008ll;
2230 }
2231
2232 #define typedef_BDK_GICD_IIDR bdk_gicd_iidr_t
2233 #define bustype_BDK_GICD_IIDR BDK_CSR_TYPE_NCB32b
2234 #define basename_BDK_GICD_IIDR "GICD_IIDR"
2235 #define device_bar_BDK_GICD_IIDR 0x0 /* PF_BAR0 */
2236 #define busnum_BDK_GICD_IIDR 0
2237 #define arguments_BDK_GICD_IIDR -1,-1,-1,-1
2238
2239 /**
2240 * Register (NCB32b) gicd_ipriorityr#
2241 *
2242 * GIC Distributor Interrupt Priority Registers
2243 * Each byte in this register provides a priority field for each SPI supported by the GIC.
2244 */
2245 union bdk_gicd_ipriorityrx
2246 {
2247 uint32_t u;
2248 struct bdk_gicd_ipriorityrx_s
2249 {
2250 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2251 uint32_t vec : 32; /**< [ 31: 0](R/W) Each byte corresponds to an SPI for SPI IDs in the range 159..32.
2252
2253 Priority fields corresponding to secure interrupts (either group 0 or group 1)
2254 may only be set by secure accesses, or when GICD_(S)CTLR[DS] is one.
2255
2256 Byte accesses are permitted to these registers.
2257
2258 A priority field for a secure SPI is RAZ/WI to nonsecure accesses. */
2259 #else /* Word 0 - Little Endian */
2260 uint32_t vec : 32; /**< [ 31: 0](R/W) Each byte corresponds to an SPI for SPI IDs in the range 159..32.
2261
2262 Priority fields corresponding to secure interrupts (either group 0 or group 1)
2263 may only be set by secure accesses, or when GICD_(S)CTLR[DS] is one.
2264
2265 Byte accesses are permitted to these registers.
2266
2267 A priority field for a secure SPI is RAZ/WI to nonsecure accesses. */
2268 #endif /* Word 0 - End */
2269 } s;
2270 /* struct bdk_gicd_ipriorityrx_s cn; */
2271 };
2272 typedef union bdk_gicd_ipriorityrx bdk_gicd_ipriorityrx_t;
2273
2274 static inline uint64_t BDK_GICD_IPRIORITYRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_IPRIORITYRX(unsigned long a)2275 static inline uint64_t BDK_GICD_IPRIORITYRX(unsigned long a)
2276 {
2277 if ((a>=8)&&(a<=39))
2278 return 0x801000000400ll + 4ll * ((a) & 0x3f);
2279 __bdk_csr_fatal("GICD_IPRIORITYRX", 1, a, 0, 0, 0);
2280 }
2281
2282 #define typedef_BDK_GICD_IPRIORITYRX(a) bdk_gicd_ipriorityrx_t
2283 #define bustype_BDK_GICD_IPRIORITYRX(a) BDK_CSR_TYPE_NCB32b
2284 #define basename_BDK_GICD_IPRIORITYRX(a) "GICD_IPRIORITYRX"
2285 #define device_bar_BDK_GICD_IPRIORITYRX(a) 0x0 /* PF_BAR0 */
2286 #define busnum_BDK_GICD_IPRIORITYRX(a) (a)
2287 #define arguments_BDK_GICD_IPRIORITYRX(a) (a),-1,-1,-1
2288
2289 /**
2290 * Register (NCB) gicd_irouter#
2291 *
2292 * GIC Distributor SPI Routing Registers
2293 * These registers provide the routing information for the security state of the associated SPIs.
2294 * Up to 64 bits of state to control the routing.
2295 */
2296 union bdk_gicd_irouterx
2297 {
2298 uint64_t u;
2299 struct bdk_gicd_irouterx_s
2300 {
2301 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2302 uint64_t reserved_40_63 : 24;
2303 uint64_t a3 : 8; /**< [ 39: 32](RO) Specifies the affinity 3 level for the SPI. In CNXXXX implementation, 0x0. */
2304 uint64_t irm : 1; /**< [ 31: 31](R/W) Specifies the interrupt routing mode for the SPI.
2305 0 = Route to the processor specified by the affinity levels A3.A2.A1.A0.
2306 1 = Route to any one processor in the system (one-of-N). */
2307 uint64_t reserved_24_30 : 7;
2308 uint64_t a2 : 8; /**< [ 23: 16](R/W) Specifies the affinity 2 level for the SPI. */
2309 uint64_t a1 : 8; /**< [ 15: 8](R/W) Specifies the affinity 1 level for the SPI. */
2310 uint64_t a0 : 8; /**< [ 7: 0](R/W) Specifies the affinity 0 level for the SPI. */
2311 #else /* Word 0 - Little Endian */
2312 uint64_t a0 : 8; /**< [ 7: 0](R/W) Specifies the affinity 0 level for the SPI. */
2313 uint64_t a1 : 8; /**< [ 15: 8](R/W) Specifies the affinity 1 level for the SPI. */
2314 uint64_t a2 : 8; /**< [ 23: 16](R/W) Specifies the affinity 2 level for the SPI. */
2315 uint64_t reserved_24_30 : 7;
2316 uint64_t irm : 1; /**< [ 31: 31](R/W) Specifies the interrupt routing mode for the SPI.
2317 0 = Route to the processor specified by the affinity levels A3.A2.A1.A0.
2318 1 = Route to any one processor in the system (one-of-N). */
2319 uint64_t a3 : 8; /**< [ 39: 32](RO) Specifies the affinity 3 level for the SPI. In CNXXXX implementation, 0x0. */
2320 uint64_t reserved_40_63 : 24;
2321 #endif /* Word 0 - End */
2322 } s;
2323 /* struct bdk_gicd_irouterx_s cn; */
2324 };
2325 typedef union bdk_gicd_irouterx bdk_gicd_irouterx_t;
2326
2327 static inline uint64_t BDK_GICD_IROUTERX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_IROUTERX(unsigned long a)2328 static inline uint64_t BDK_GICD_IROUTERX(unsigned long a)
2329 {
2330 if ((a>=32)&&(a<=159))
2331 return 0x801000006000ll + 8ll * ((a) & 0xff);
2332 __bdk_csr_fatal("GICD_IROUTERX", 1, a, 0, 0, 0);
2333 }
2334
2335 #define typedef_BDK_GICD_IROUTERX(a) bdk_gicd_irouterx_t
2336 #define bustype_BDK_GICD_IROUTERX(a) BDK_CSR_TYPE_NCB
2337 #define basename_BDK_GICD_IROUTERX(a) "GICD_IROUTERX"
2338 #define device_bar_BDK_GICD_IROUTERX(a) 0x0 /* PF_BAR0 */
2339 #define busnum_BDK_GICD_IROUTERX(a) (a)
2340 #define arguments_BDK_GICD_IROUTERX(a) (a),-1,-1,-1
2341
2342 /**
2343 * Register (NCB32b) gicd_isactiver#
2344 *
2345 * GIC Distributor Interrupt Set-Active Registers
2346 * Each bit in this register provides a set-active bit for each SPI supported by the GIC.
2347 * Writing one to a set-active bit sets the status of the corresponding SPI to active.
2348 */
2349 union bdk_gicd_isactiverx
2350 {
2351 uint32_t u;
2352 struct bdk_gicd_isactiverx_s
2353 {
2354 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2355 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2356 SPI
2357 is not active. If read as one, the SPI is in active state.
2358
2359 Set-active bits corresponding to secure interrupts (either group 0 or group 1)
2360 may only be set by secure accesses.
2361
2362 A set-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2363 #else /* Word 0 - Little Endian */
2364 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2365 SPI
2366 is not active. If read as one, the SPI is in active state.
2367
2368 Set-active bits corresponding to secure interrupts (either group 0 or group 1)
2369 may only be set by secure accesses.
2370
2371 A set-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2372 #endif /* Word 0 - End */
2373 } s;
2374 struct bdk_gicd_isactiverx_cn9
2375 {
2376 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2377 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2378 SPI
2379 is not active. If read as one, the SPI is in active state.
2380
2381 Set-active bits corresponding to secure interrupts (either group 0 or group 1)
2382 may only be set by secure accesses.
2383
2384 A set-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2385 #else /* Word 0 - Little Endian */
2386 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2387 SPI
2388 is not active. If read as one, the SPI is in active state.
2389
2390 Set-active bits corresponding to secure interrupts (either group 0 or group 1)
2391 may only be set by secure accesses.
2392
2393 A set-active bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2394 #endif /* Word 0 - End */
2395 } cn9;
2396 /* struct bdk_gicd_isactiverx_cn9 cn81xx; */
2397 /* struct bdk_gicd_isactiverx_s cn88xx; */
2398 /* struct bdk_gicd_isactiverx_cn9 cn83xx; */
2399 };
2400 typedef union bdk_gicd_isactiverx bdk_gicd_isactiverx_t;
2401
2402 static inline uint64_t BDK_GICD_ISACTIVERX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ISACTIVERX(unsigned long a)2403 static inline uint64_t BDK_GICD_ISACTIVERX(unsigned long a)
2404 {
2405 if ((a>=1)&&(a<=4))
2406 return 0x801000000300ll + 4ll * ((a) & 0x7);
2407 __bdk_csr_fatal("GICD_ISACTIVERX", 1, a, 0, 0, 0);
2408 }
2409
2410 #define typedef_BDK_GICD_ISACTIVERX(a) bdk_gicd_isactiverx_t
2411 #define bustype_BDK_GICD_ISACTIVERX(a) BDK_CSR_TYPE_NCB32b
2412 #define basename_BDK_GICD_ISACTIVERX(a) "GICD_ISACTIVERX"
2413 #define device_bar_BDK_GICD_ISACTIVERX(a) 0x0 /* PF_BAR0 */
2414 #define busnum_BDK_GICD_ISACTIVERX(a) (a)
2415 #define arguments_BDK_GICD_ISACTIVERX(a) (a),-1,-1,-1
2416
2417 /**
2418 * Register (NCB32b) gicd_isenabler#
2419 *
2420 * GIC Distributor Interrupt Set-Enable Registers
2421 * Each bit in GICD_ISENABLER() provides a set-enable bit for each SPI supported by the GIC.
2422 * Writing one to a set-enable bit enables forwarding of the corresponding SPI from the
2423 * distributor to the CPU interfaces.
2424 */
2425 union bdk_gicd_isenablerx
2426 {
2427 uint32_t u;
2428 struct bdk_gicd_isenablerx_s
2429 {
2430 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2431 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If zero, then
2432 the SPI is not enabled to be forwarded to the CPU interface. If one, the SPI is
2433 enabled to be forwarded to the CPU interface. Set-enable bits corresponding to
2434 secure interrupts (either group 0 or group 1) may only be set by secure
2435 accesses. */
2436 #else /* Word 0 - Little Endian */
2437 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If zero, then
2438 the SPI is not enabled to be forwarded to the CPU interface. If one, the SPI is
2439 enabled to be forwarded to the CPU interface. Set-enable bits corresponding to
2440 secure interrupts (either group 0 or group 1) may only be set by secure
2441 accesses. */
2442 #endif /* Word 0 - End */
2443 } s;
2444 /* struct bdk_gicd_isenablerx_s cn; */
2445 };
2446 typedef union bdk_gicd_isenablerx bdk_gicd_isenablerx_t;
2447
2448 static inline uint64_t BDK_GICD_ISENABLERX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ISENABLERX(unsigned long a)2449 static inline uint64_t BDK_GICD_ISENABLERX(unsigned long a)
2450 {
2451 if ((a>=1)&&(a<=4))
2452 return 0x801000000100ll + 4ll * ((a) & 0x7);
2453 __bdk_csr_fatal("GICD_ISENABLERX", 1, a, 0, 0, 0);
2454 }
2455
2456 #define typedef_BDK_GICD_ISENABLERX(a) bdk_gicd_isenablerx_t
2457 #define bustype_BDK_GICD_ISENABLERX(a) BDK_CSR_TYPE_NCB32b
2458 #define basename_BDK_GICD_ISENABLERX(a) "GICD_ISENABLERX"
2459 #define device_bar_BDK_GICD_ISENABLERX(a) 0x0 /* PF_BAR0 */
2460 #define busnum_BDK_GICD_ISENABLERX(a) (a)
2461 #define arguments_BDK_GICD_ISENABLERX(a) (a),-1,-1,-1
2462
2463 /**
2464 * Register (NCB32b) gicd_ispendr#
2465 *
2466 * GIC Distributor Interrupt Set-Pending Registers
2467 * Each bit in GICD_ISPENDR() provides a set-pending bit for each SPI supported by the GIC.
2468 * Writing one to a set-pending bit sets the status of the corresponding SPI to pending.
2469 */
2470 union bdk_gicd_ispendrx
2471 {
2472 uint32_t u;
2473 struct bdk_gicd_ispendrx_s
2474 {
2475 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2476 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2477 SPI
2478 is not pending. If read as one, the SPI is in pending state.
2479
2480 Set-pending bits corresponding to secure interrupts (either group 0 or group 1)
2481 may only be set by secure accesses.
2482
2483 A set-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2484 #else /* Word 0 - Little Endian */
2485 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2486 SPI
2487 is not pending. If read as one, the SPI is in pending state.
2488
2489 Set-pending bits corresponding to secure interrupts (either group 0 or group 1)
2490 may only be set by secure accesses.
2491
2492 A set-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2493 #endif /* Word 0 - End */
2494 } s;
2495 struct bdk_gicd_ispendrx_cn9
2496 {
2497 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2498 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2499 SPI
2500 is not pending. If read as one, the SPI is in pending state.
2501
2502 Set-pending bits corresponding to secure interrupts (either group 0 or group 1)
2503 may only be set by secure accesses.
2504
2505 A set-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2506 #else /* Word 0 - Little Endian */
2507 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SPI for SPI IDs in the range 159..32. If read as zero, then the
2508 SPI
2509 is not pending. If read as one, the SPI is in pending state.
2510
2511 Set-pending bits corresponding to secure interrupts (either group 0 or group 1)
2512 may only be set by secure accesses.
2513
2514 A set-pending bit for a secure SPI is RAZ/WI to nonsecure accesses. */
2515 #endif /* Word 0 - End */
2516 } cn9;
2517 /* struct bdk_gicd_ispendrx_cn9 cn81xx; */
2518 /* struct bdk_gicd_ispendrx_s cn88xx; */
2519 /* struct bdk_gicd_ispendrx_cn9 cn83xx; */
2520 };
2521 typedef union bdk_gicd_ispendrx bdk_gicd_ispendrx_t;
2522
2523 static inline uint64_t BDK_GICD_ISPENDRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_ISPENDRX(unsigned long a)2524 static inline uint64_t BDK_GICD_ISPENDRX(unsigned long a)
2525 {
2526 if ((a>=1)&&(a<=4))
2527 return 0x801000000200ll + 4ll * ((a) & 0x7);
2528 __bdk_csr_fatal("GICD_ISPENDRX", 1, a, 0, 0, 0);
2529 }
2530
2531 #define typedef_BDK_GICD_ISPENDRX(a) bdk_gicd_ispendrx_t
2532 #define bustype_BDK_GICD_ISPENDRX(a) BDK_CSR_TYPE_NCB32b
2533 #define basename_BDK_GICD_ISPENDRX(a) "GICD_ISPENDRX"
2534 #define device_bar_BDK_GICD_ISPENDRX(a) 0x0 /* PF_BAR0 */
2535 #define busnum_BDK_GICD_ISPENDRX(a) (a)
2536 #define arguments_BDK_GICD_ISPENDRX(a) (a),-1,-1,-1
2537
2538 /**
2539 * Register (NCB32b) gicd_nsacr#
2540 *
2541 * GIC Distributor Nonsecure Access Control Secure Registers
2542 */
2543 union bdk_gicd_nsacrx
2544 {
2545 uint32_t u;
2546 struct bdk_gicd_nsacrx_s
2547 {
2548 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2549 uint32_t vec : 32; /**< [ 31: 0](SR/W) Two bits per SPI. Defines whether nonsecure access is permitted to secure SPI resources.
2550 0x0 = No nonsecure access is permitted to fields associated with the corresponding SPI.
2551 0x1 = Nonsecure read and write access is permitted to fields associated with the SPI in
2552 GICD_ISPENDR(). A nonsecure write access to GICD_SETSPI_NSR is permitted to
2553 set the pending state of the corresponding SPI.
2554 0x2 = Adds nonsecure read and write access permissions to fields associated with the
2555 corresponding SPI in GICD_ICPENDR(). A nonsecure write access to
2556 GICD_CLRSPI_NSR is permitted to clear the pending state of the corresponding SPI. Also
2557 adds nonsecure read access permission to fields associated with the corresponding SPI in
2558 the GICD_ISACTIVER() and GICD_ICACTIVER().
2559 0x3 = Adds nonsecure read and write access permission to fields associated with the
2560 corresponding SPI in GICD_IROUTER().
2561
2562 This register is RAZ/WI for nonsecure accesses.
2563
2564 When GICD_(S)CTLR[DS] is one, this register is RAZ/WI. */
2565 #else /* Word 0 - Little Endian */
2566 uint32_t vec : 32; /**< [ 31: 0](SR/W) Two bits per SPI. Defines whether nonsecure access is permitted to secure SPI resources.
2567 0x0 = No nonsecure access is permitted to fields associated with the corresponding SPI.
2568 0x1 = Nonsecure read and write access is permitted to fields associated with the SPI in
2569 GICD_ISPENDR(). A nonsecure write access to GICD_SETSPI_NSR is permitted to
2570 set the pending state of the corresponding SPI.
2571 0x2 = Adds nonsecure read and write access permissions to fields associated with the
2572 corresponding SPI in GICD_ICPENDR(). A nonsecure write access to
2573 GICD_CLRSPI_NSR is permitted to clear the pending state of the corresponding SPI. Also
2574 adds nonsecure read access permission to fields associated with the corresponding SPI in
2575 the GICD_ISACTIVER() and GICD_ICACTIVER().
2576 0x3 = Adds nonsecure read and write access permission to fields associated with the
2577 corresponding SPI in GICD_IROUTER().
2578
2579 This register is RAZ/WI for nonsecure accesses.
2580
2581 When GICD_(S)CTLR[DS] is one, this register is RAZ/WI. */
2582 #endif /* Word 0 - End */
2583 } s;
2584 /* struct bdk_gicd_nsacrx_s cn; */
2585 };
2586 typedef union bdk_gicd_nsacrx bdk_gicd_nsacrx_t;
2587
2588 static inline uint64_t BDK_GICD_NSACRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICD_NSACRX(unsigned long a)2589 static inline uint64_t BDK_GICD_NSACRX(unsigned long a)
2590 {
2591 if ((a>=2)&&(a<=9))
2592 return 0x801000000e00ll + 4ll * ((a) & 0xf);
2593 __bdk_csr_fatal("GICD_NSACRX", 1, a, 0, 0, 0);
2594 }
2595
2596 #define typedef_BDK_GICD_NSACRX(a) bdk_gicd_nsacrx_t
2597 #define bustype_BDK_GICD_NSACRX(a) BDK_CSR_TYPE_NCB32b
2598 #define basename_BDK_GICD_NSACRX(a) "GICD_NSACRX"
2599 #define device_bar_BDK_GICD_NSACRX(a) 0x0 /* PF_BAR0 */
2600 #define busnum_BDK_GICD_NSACRX(a) (a)
2601 #define arguments_BDK_GICD_NSACRX(a) (a),-1,-1,-1
2602
2603 /**
2604 * Register (NCB32b) gicd_pidr0
2605 *
2606 * GIC Distributor Peripheral Identification Register 0
2607 */
2608 union bdk_gicd_pidr0
2609 {
2610 uint32_t u;
2611 struct bdk_gicd_pidr0_s
2612 {
2613 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2614 uint32_t reserved_8_31 : 24;
2615 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GICD. */
2616 #else /* Word 0 - Little Endian */
2617 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GICD. */
2618 uint32_t reserved_8_31 : 24;
2619 #endif /* Word 0 - End */
2620 } s;
2621 /* struct bdk_gicd_pidr0_s cn; */
2622 };
2623 typedef union bdk_gicd_pidr0 bdk_gicd_pidr0_t;
2624
2625 #define BDK_GICD_PIDR0 BDK_GICD_PIDR0_FUNC()
2626 static inline uint64_t BDK_GICD_PIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR0_FUNC(void)2627 static inline uint64_t BDK_GICD_PIDR0_FUNC(void)
2628 {
2629 return 0x80100000ffe0ll;
2630 }
2631
2632 #define typedef_BDK_GICD_PIDR0 bdk_gicd_pidr0_t
2633 #define bustype_BDK_GICD_PIDR0 BDK_CSR_TYPE_NCB32b
2634 #define basename_BDK_GICD_PIDR0 "GICD_PIDR0"
2635 #define device_bar_BDK_GICD_PIDR0 0x0 /* PF_BAR0 */
2636 #define busnum_BDK_GICD_PIDR0 0
2637 #define arguments_BDK_GICD_PIDR0 -1,-1,-1,-1
2638
2639 /**
2640 * Register (NCB32b) gicd_pidr1
2641 *
2642 * GIC Distributor Peripheral Identification Register 1
2643 */
2644 union bdk_gicd_pidr1
2645 {
2646 uint32_t u;
2647 struct bdk_gicd_pidr1_s
2648 {
2649 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2650 uint32_t reserved_8_31 : 24;
2651 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
2652 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
2653 #else /* Word 0 - Little Endian */
2654 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
2655 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
2656 uint32_t reserved_8_31 : 24;
2657 #endif /* Word 0 - End */
2658 } s;
2659 /* struct bdk_gicd_pidr1_s cn; */
2660 };
2661 typedef union bdk_gicd_pidr1 bdk_gicd_pidr1_t;
2662
2663 #define BDK_GICD_PIDR1 BDK_GICD_PIDR1_FUNC()
2664 static inline uint64_t BDK_GICD_PIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR1_FUNC(void)2665 static inline uint64_t BDK_GICD_PIDR1_FUNC(void)
2666 {
2667 return 0x80100000ffe4ll;
2668 }
2669
2670 #define typedef_BDK_GICD_PIDR1 bdk_gicd_pidr1_t
2671 #define bustype_BDK_GICD_PIDR1 BDK_CSR_TYPE_NCB32b
2672 #define basename_BDK_GICD_PIDR1 "GICD_PIDR1"
2673 #define device_bar_BDK_GICD_PIDR1 0x0 /* PF_BAR0 */
2674 #define busnum_BDK_GICD_PIDR1 0
2675 #define arguments_BDK_GICD_PIDR1 -1,-1,-1,-1
2676
2677 /**
2678 * Register (NCB32b) gicd_pidr2
2679 *
2680 * GIC Distributor Peripheral Identification Register 2
2681 */
2682 union bdk_gicd_pidr2
2683 {
2684 uint32_t u;
2685 struct bdk_gicd_pidr2_s
2686 {
2687 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2688 uint32_t reserved_8_31 : 24;
2689 uint32_t archrev : 4; /**< [ 7: 4](RO) Architectural revision:
2690 0x1 = GICv1.
2691 0x2 = GICV2.
2692 0x3 = GICv3.
2693 0x4 = GICv4.
2694 0x5-0xF = Reserved. */
2695 uint32_t usesjepcode : 1; /**< [ 3: 3](RO) JEDEC assigned. */
2696 uint32_t jepid : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
2697 #else /* Word 0 - Little Endian */
2698 uint32_t jepid : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
2699 uint32_t usesjepcode : 1; /**< [ 3: 3](RO) JEDEC assigned. */
2700 uint32_t archrev : 4; /**< [ 7: 4](RO) Architectural revision:
2701 0x1 = GICv1.
2702 0x2 = GICV2.
2703 0x3 = GICv3.
2704 0x4 = GICv4.
2705 0x5-0xF = Reserved. */
2706 uint32_t reserved_8_31 : 24;
2707 #endif /* Word 0 - End */
2708 } s;
2709 /* struct bdk_gicd_pidr2_s cn; */
2710 };
2711 typedef union bdk_gicd_pidr2 bdk_gicd_pidr2_t;
2712
2713 #define BDK_GICD_PIDR2 BDK_GICD_PIDR2_FUNC()
2714 static inline uint64_t BDK_GICD_PIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR2_FUNC(void)2715 static inline uint64_t BDK_GICD_PIDR2_FUNC(void)
2716 {
2717 return 0x80100000ffe8ll;
2718 }
2719
2720 #define typedef_BDK_GICD_PIDR2 bdk_gicd_pidr2_t
2721 #define bustype_BDK_GICD_PIDR2 BDK_CSR_TYPE_NCB32b
2722 #define basename_BDK_GICD_PIDR2 "GICD_PIDR2"
2723 #define device_bar_BDK_GICD_PIDR2 0x0 /* PF_BAR0 */
2724 #define busnum_BDK_GICD_PIDR2 0
2725 #define arguments_BDK_GICD_PIDR2 -1,-1,-1,-1
2726
2727 /**
2728 * Register (NCB32b) gicd_pidr3
2729 *
2730 * GIC Distributor Peripheral Identification Register 3
2731 */
2732 union bdk_gicd_pidr3
2733 {
2734 uint32_t u;
2735 struct bdk_gicd_pidr3_s
2736 {
2737 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2738 uint32_t reserved_8_31 : 24;
2739 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
2740 uint32_t cmod : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
2741 product, major and minor pass numbers. */
2742 #else /* Word 0 - Little Endian */
2743 uint32_t cmod : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
2744 product, major and minor pass numbers. */
2745 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
2746 uint32_t reserved_8_31 : 24;
2747 #endif /* Word 0 - End */
2748 } s;
2749 /* struct bdk_gicd_pidr3_s cn; */
2750 };
2751 typedef union bdk_gicd_pidr3 bdk_gicd_pidr3_t;
2752
2753 #define BDK_GICD_PIDR3 BDK_GICD_PIDR3_FUNC()
2754 static inline uint64_t BDK_GICD_PIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR3_FUNC(void)2755 static inline uint64_t BDK_GICD_PIDR3_FUNC(void)
2756 {
2757 return 0x80100000ffecll;
2758 }
2759
2760 #define typedef_BDK_GICD_PIDR3 bdk_gicd_pidr3_t
2761 #define bustype_BDK_GICD_PIDR3 BDK_CSR_TYPE_NCB32b
2762 #define basename_BDK_GICD_PIDR3 "GICD_PIDR3"
2763 #define device_bar_BDK_GICD_PIDR3 0x0 /* PF_BAR0 */
2764 #define busnum_BDK_GICD_PIDR3 0
2765 #define arguments_BDK_GICD_PIDR3 -1,-1,-1,-1
2766
2767 /**
2768 * Register (NCB32b) gicd_pidr4
2769 *
2770 * GIC Distributor Peripheral Identification Register 4
2771 */
2772 union bdk_gicd_pidr4
2773 {
2774 uint32_t u;
2775 struct bdk_gicd_pidr4_s
2776 {
2777 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2778 uint32_t reserved_8_31 : 24;
2779 uint32_t cnt_4k : 4; /**< [ 7: 4](RO) This field is 0x4, indicating a 64 KB software-visible page. */
2780 uint32_t continuation_code : 4; /**< [ 3: 0](RO) JEP106 continuation code, least significant nibble. Indicates Cavium. */
2781 #else /* Word 0 - Little Endian */
2782 uint32_t continuation_code : 4; /**< [ 3: 0](RO) JEP106 continuation code, least significant nibble. Indicates Cavium. */
2783 uint32_t cnt_4k : 4; /**< [ 7: 4](RO) This field is 0x4, indicating a 64 KB software-visible page. */
2784 uint32_t reserved_8_31 : 24;
2785 #endif /* Word 0 - End */
2786 } s;
2787 /* struct bdk_gicd_pidr4_s cn; */
2788 };
2789 typedef union bdk_gicd_pidr4 bdk_gicd_pidr4_t;
2790
2791 #define BDK_GICD_PIDR4 BDK_GICD_PIDR4_FUNC()
2792 static inline uint64_t BDK_GICD_PIDR4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR4_FUNC(void)2793 static inline uint64_t BDK_GICD_PIDR4_FUNC(void)
2794 {
2795 return 0x80100000ffd0ll;
2796 }
2797
2798 #define typedef_BDK_GICD_PIDR4 bdk_gicd_pidr4_t
2799 #define bustype_BDK_GICD_PIDR4 BDK_CSR_TYPE_NCB32b
2800 #define basename_BDK_GICD_PIDR4 "GICD_PIDR4"
2801 #define device_bar_BDK_GICD_PIDR4 0x0 /* PF_BAR0 */
2802 #define busnum_BDK_GICD_PIDR4 0
2803 #define arguments_BDK_GICD_PIDR4 -1,-1,-1,-1
2804
2805 /**
2806 * Register (NCB32b) gicd_pidr5
2807 *
2808 * GIC Distributor Peripheral Identification Register 5
2809 */
2810 union bdk_gicd_pidr5
2811 {
2812 uint32_t u;
2813 struct bdk_gicd_pidr5_s
2814 {
2815 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2816 uint32_t reserved_0_31 : 32;
2817 #else /* Word 0 - Little Endian */
2818 uint32_t reserved_0_31 : 32;
2819 #endif /* Word 0 - End */
2820 } s;
2821 /* struct bdk_gicd_pidr5_s cn; */
2822 };
2823 typedef union bdk_gicd_pidr5 bdk_gicd_pidr5_t;
2824
2825 #define BDK_GICD_PIDR5 BDK_GICD_PIDR5_FUNC()
2826 static inline uint64_t BDK_GICD_PIDR5_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR5_FUNC(void)2827 static inline uint64_t BDK_GICD_PIDR5_FUNC(void)
2828 {
2829 return 0x80100000ffd4ll;
2830 }
2831
2832 #define typedef_BDK_GICD_PIDR5 bdk_gicd_pidr5_t
2833 #define bustype_BDK_GICD_PIDR5 BDK_CSR_TYPE_NCB32b
2834 #define basename_BDK_GICD_PIDR5 "GICD_PIDR5"
2835 #define device_bar_BDK_GICD_PIDR5 0x0 /* PF_BAR0 */
2836 #define busnum_BDK_GICD_PIDR5 0
2837 #define arguments_BDK_GICD_PIDR5 -1,-1,-1,-1
2838
2839 /**
2840 * Register (NCB32b) gicd_pidr6
2841 *
2842 * GIC Distributor Peripheral Identification Register 6
2843 */
2844 union bdk_gicd_pidr6
2845 {
2846 uint32_t u;
2847 struct bdk_gicd_pidr6_s
2848 {
2849 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2850 uint32_t reserved_0_31 : 32;
2851 #else /* Word 0 - Little Endian */
2852 uint32_t reserved_0_31 : 32;
2853 #endif /* Word 0 - End */
2854 } s;
2855 /* struct bdk_gicd_pidr6_s cn; */
2856 };
2857 typedef union bdk_gicd_pidr6 bdk_gicd_pidr6_t;
2858
2859 #define BDK_GICD_PIDR6 BDK_GICD_PIDR6_FUNC()
2860 static inline uint64_t BDK_GICD_PIDR6_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR6_FUNC(void)2861 static inline uint64_t BDK_GICD_PIDR6_FUNC(void)
2862 {
2863 return 0x80100000ffd8ll;
2864 }
2865
2866 #define typedef_BDK_GICD_PIDR6 bdk_gicd_pidr6_t
2867 #define bustype_BDK_GICD_PIDR6 BDK_CSR_TYPE_NCB32b
2868 #define basename_BDK_GICD_PIDR6 "GICD_PIDR6"
2869 #define device_bar_BDK_GICD_PIDR6 0x0 /* PF_BAR0 */
2870 #define busnum_BDK_GICD_PIDR6 0
2871 #define arguments_BDK_GICD_PIDR6 -1,-1,-1,-1
2872
2873 /**
2874 * Register (NCB32b) gicd_pidr7
2875 *
2876 * GIC Distributor Peripheral Identification Register 7
2877 */
2878 union bdk_gicd_pidr7
2879 {
2880 uint32_t u;
2881 struct bdk_gicd_pidr7_s
2882 {
2883 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2884 uint32_t reserved_0_31 : 32;
2885 #else /* Word 0 - Little Endian */
2886 uint32_t reserved_0_31 : 32;
2887 #endif /* Word 0 - End */
2888 } s;
2889 /* struct bdk_gicd_pidr7_s cn; */
2890 };
2891 typedef union bdk_gicd_pidr7 bdk_gicd_pidr7_t;
2892
2893 #define BDK_GICD_PIDR7 BDK_GICD_PIDR7_FUNC()
2894 static inline uint64_t BDK_GICD_PIDR7_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_PIDR7_FUNC(void)2895 static inline uint64_t BDK_GICD_PIDR7_FUNC(void)
2896 {
2897 return 0x80100000ffdcll;
2898 }
2899
2900 #define typedef_BDK_GICD_PIDR7 bdk_gicd_pidr7_t
2901 #define bustype_BDK_GICD_PIDR7 BDK_CSR_TYPE_NCB32b
2902 #define basename_BDK_GICD_PIDR7 "GICD_PIDR7"
2903 #define device_bar_BDK_GICD_PIDR7 0x0 /* PF_BAR0 */
2904 #define busnum_BDK_GICD_PIDR7 0
2905 #define arguments_BDK_GICD_PIDR7 -1,-1,-1,-1
2906
2907 /**
2908 * Register (NCB32b) gicd_sctlr
2909 *
2910 * GIC Distributor (Secure) Control Register
2911 * Controls the behavior of the distributor.
2912 */
2913 union bdk_gicd_sctlr
2914 {
2915 uint32_t u;
2916 struct bdk_gicd_sctlr_s
2917 {
2918 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2919 uint32_t rwp : 1; /**< [ 31: 31](RO/H) Register write pending.
2920 Indicates whether a register write is in progress.
2921 0 = The effects of all register writes are visible to all descendants of the top-level
2922 redistributor, including processors.
2923 1 = The effects of all register writes are not visible to all descendants of the top-level
2924 redistributor.
2925
2926 Note: this field tracks completion of writes to GICD_(S)CTLR that change the state of an
2927 interrupt group enable or an affinity routing setting and writes to GICD_ICENABLER() that
2928 clear the enable of one or more SPIs. */
2929 uint32_t reserved_7_30 : 24;
2930 uint32_t ds : 1; /**< [ 6: 6](SR/W) Disable security.
2931 When set, nonsecure accesses are permitted to access and modify registers that control
2932 group 0 interrupts.
2933 If [DS] becomes one when [ARE_SNS] is one, then ARE for the single security state is
2934 RAO/WI.
2935
2936 When [DS] is set, all accesses to GICD_(S)CTLR access the single security state view
2937 (below) and all bits are accessible.
2938
2939 This bit is RAO/WI if the distributor only supports a single security state (see
2940 below).
2941
2942 Once set, [DS] may only be clear by a hardware reset. */
2943 uint32_t are_ns : 1; /**< [ 5: 5](SRO) Enable affinity routing for the nonsecure state when set.
2944 In CNXXXX this bit is always one as only affinity routing is supported.
2945
2946 Note: this bit is RAO/WI when ARE is one for the secure state. */
2947 uint32_t are_sns : 1; /**< [ 4: 4](RO) Enables affinity routing for the nonsecure state.
2948 This field is fixed as RAO/WI for CNXXXX for both secure and non secure state. */
2949 uint32_t reserved_3 : 1;
2950 uint32_t enable_g1s : 1; /**< [ 2: 2](SR/W) Enables secure group 1 interrupts.
2951 0 = Disable G1S interrupts.
2952 1 = Enable G1S interrupts. */
2953 uint32_t enable_g1ns : 1; /**< [ 1: 1](R/W) S - Enables nonsecure group 1 interrupts. Behaves as defined for GICv2. This
2954 enable also controls whether LPIs are forwarded to processors. When written
2955 to zero, [RWP] indicates whether the effects of this enable on LPIs
2956 have been made visible.
2957
2958 NS - This field is called ENABLE_G1A. It enables nonsecure group 1 interrupts. */
2959 uint32_t enable_g0 : 1; /**< [ 0: 0](SR/W) Secure view or [DS] is set -- Enable/disable group 0 interrupts.
2960 0 = Disable G0 interrupts.
2961 1 = Enable G0 interrupts.
2962
2963 Nonsecure view -- RES0 for CNXXXX since [ARE_NS] is RAO. */
2964 #else /* Word 0 - Little Endian */
2965 uint32_t enable_g0 : 1; /**< [ 0: 0](SR/W) Secure view or [DS] is set -- Enable/disable group 0 interrupts.
2966 0 = Disable G0 interrupts.
2967 1 = Enable G0 interrupts.
2968
2969 Nonsecure view -- RES0 for CNXXXX since [ARE_NS] is RAO. */
2970 uint32_t enable_g1ns : 1; /**< [ 1: 1](R/W) S - Enables nonsecure group 1 interrupts. Behaves as defined for GICv2. This
2971 enable also controls whether LPIs are forwarded to processors. When written
2972 to zero, [RWP] indicates whether the effects of this enable on LPIs
2973 have been made visible.
2974
2975 NS - This field is called ENABLE_G1A. It enables nonsecure group 1 interrupts. */
2976 uint32_t enable_g1s : 1; /**< [ 2: 2](SR/W) Enables secure group 1 interrupts.
2977 0 = Disable G1S interrupts.
2978 1 = Enable G1S interrupts. */
2979 uint32_t reserved_3 : 1;
2980 uint32_t are_sns : 1; /**< [ 4: 4](RO) Enables affinity routing for the nonsecure state.
2981 This field is fixed as RAO/WI for CNXXXX for both secure and non secure state. */
2982 uint32_t are_ns : 1; /**< [ 5: 5](SRO) Enable affinity routing for the nonsecure state when set.
2983 In CNXXXX this bit is always one as only affinity routing is supported.
2984
2985 Note: this bit is RAO/WI when ARE is one for the secure state. */
2986 uint32_t ds : 1; /**< [ 6: 6](SR/W) Disable security.
2987 When set, nonsecure accesses are permitted to access and modify registers that control
2988 group 0 interrupts.
2989 If [DS] becomes one when [ARE_SNS] is one, then ARE for the single security state is
2990 RAO/WI.
2991
2992 When [DS] is set, all accesses to GICD_(S)CTLR access the single security state view
2993 (below) and all bits are accessible.
2994
2995 This bit is RAO/WI if the distributor only supports a single security state (see
2996 below).
2997
2998 Once set, [DS] may only be clear by a hardware reset. */
2999 uint32_t reserved_7_30 : 24;
3000 uint32_t rwp : 1; /**< [ 31: 31](RO/H) Register write pending.
3001 Indicates whether a register write is in progress.
3002 0 = The effects of all register writes are visible to all descendants of the top-level
3003 redistributor, including processors.
3004 1 = The effects of all register writes are not visible to all descendants of the top-level
3005 redistributor.
3006
3007 Note: this field tracks completion of writes to GICD_(S)CTLR that change the state of an
3008 interrupt group enable or an affinity routing setting and writes to GICD_ICENABLER() that
3009 clear the enable of one or more SPIs. */
3010 #endif /* Word 0 - End */
3011 } s;
3012 /* struct bdk_gicd_sctlr_s cn; */
3013 };
3014 typedef union bdk_gicd_sctlr bdk_gicd_sctlr_t;
3015
3016 #define BDK_GICD_SCTLR BDK_GICD_SCTLR_FUNC()
3017 static inline uint64_t BDK_GICD_SCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_SCTLR_FUNC(void)3018 static inline uint64_t BDK_GICD_SCTLR_FUNC(void)
3019 {
3020 return 0x801000000000ll;
3021 }
3022
3023 #define typedef_BDK_GICD_SCTLR bdk_gicd_sctlr_t
3024 #define bustype_BDK_GICD_SCTLR BDK_CSR_TYPE_NCB32b
3025 #define basename_BDK_GICD_SCTLR "GICD_SCTLR"
3026 #define device_bar_BDK_GICD_SCTLR 0x0 /* PF_BAR0 */
3027 #define busnum_BDK_GICD_SCTLR 0
3028 #define arguments_BDK_GICD_SCTLR -1,-1,-1,-1
3029
3030 /**
3031 * Register (NCB32b) gicd_setspi_nsr
3032 *
3033 * GIC Distributor Set SPI Pending Register
3034 */
3035 union bdk_gicd_setspi_nsr
3036 {
3037 uint32_t u;
3038 struct bdk_gicd_setspi_nsr_s
3039 {
3040 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3041 uint32_t reserved_10_31 : 22;
3042 uint32_t spi_id : 10; /**< [ 9: 0](WO) Set an SPI to pending (write-only). If the SPI is already pending, then the write has no
3043 effect.
3044
3045 If the SPI ID is invalid, then the write has no effect.
3046
3047 If the register is written using a nonsecure access and the value specifies a secure SPI
3048 and the value of the corresponding GICD_NSACR() register is zero (i.e. does not permit
3049 nonsecure accesses to set the interrupt as pending), the write has no effect. */
3050 #else /* Word 0 - Little Endian */
3051 uint32_t spi_id : 10; /**< [ 9: 0](WO) Set an SPI to pending (write-only). If the SPI is already pending, then the write has no
3052 effect.
3053
3054 If the SPI ID is invalid, then the write has no effect.
3055
3056 If the register is written using a nonsecure access and the value specifies a secure SPI
3057 and the value of the corresponding GICD_NSACR() register is zero (i.e. does not permit
3058 nonsecure accesses to set the interrupt as pending), the write has no effect. */
3059 uint32_t reserved_10_31 : 22;
3060 #endif /* Word 0 - End */
3061 } s;
3062 /* struct bdk_gicd_setspi_nsr_s cn; */
3063 };
3064 typedef union bdk_gicd_setspi_nsr bdk_gicd_setspi_nsr_t;
3065
3066 #define BDK_GICD_SETSPI_NSR BDK_GICD_SETSPI_NSR_FUNC()
3067 static inline uint64_t BDK_GICD_SETSPI_NSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_SETSPI_NSR_FUNC(void)3068 static inline uint64_t BDK_GICD_SETSPI_NSR_FUNC(void)
3069 {
3070 return 0x801000000040ll;
3071 }
3072
3073 #define typedef_BDK_GICD_SETSPI_NSR bdk_gicd_setspi_nsr_t
3074 #define bustype_BDK_GICD_SETSPI_NSR BDK_CSR_TYPE_NCB32b
3075 #define basename_BDK_GICD_SETSPI_NSR "GICD_SETSPI_NSR"
3076 #define device_bar_BDK_GICD_SETSPI_NSR 0x0 /* PF_BAR0 */
3077 #define busnum_BDK_GICD_SETSPI_NSR 0
3078 #define arguments_BDK_GICD_SETSPI_NSR -1,-1,-1,-1
3079
3080 /**
3081 * Register (NCB32b) gicd_setspi_sr
3082 *
3083 * GIC Distributor Set Secure SPI Pending Register
3084 */
3085 union bdk_gicd_setspi_sr
3086 {
3087 uint32_t u;
3088 struct bdk_gicd_setspi_sr_s
3089 {
3090 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3091 uint32_t reserved_10_31 : 22;
3092 uint32_t spi_id : 10; /**< [ 9: 0](SWO) Set an SPI to pending (write-only). If the SPI is already pending, then the write has no
3093 effect.
3094
3095 If the SPI ID is invalid, then the write has no effect.
3096
3097 If the register is written using a nonsecure access, the write has no effect. */
3098 #else /* Word 0 - Little Endian */
3099 uint32_t spi_id : 10; /**< [ 9: 0](SWO) Set an SPI to pending (write-only). If the SPI is already pending, then the write has no
3100 effect.
3101
3102 If the SPI ID is invalid, then the write has no effect.
3103
3104 If the register is written using a nonsecure access, the write has no effect. */
3105 uint32_t reserved_10_31 : 22;
3106 #endif /* Word 0 - End */
3107 } s;
3108 /* struct bdk_gicd_setspi_sr_s cn; */
3109 };
3110 typedef union bdk_gicd_setspi_sr bdk_gicd_setspi_sr_t;
3111
3112 #define BDK_GICD_SETSPI_SR BDK_GICD_SETSPI_SR_FUNC()
3113 static inline uint64_t BDK_GICD_SETSPI_SR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_SETSPI_SR_FUNC(void)3114 static inline uint64_t BDK_GICD_SETSPI_SR_FUNC(void)
3115 {
3116 return 0x801000000050ll;
3117 }
3118
3119 #define typedef_BDK_GICD_SETSPI_SR bdk_gicd_setspi_sr_t
3120 #define bustype_BDK_GICD_SETSPI_SR BDK_CSR_TYPE_NCB32b
3121 #define basename_BDK_GICD_SETSPI_SR "GICD_SETSPI_SR"
3122 #define device_bar_BDK_GICD_SETSPI_SR 0x0 /* PF_BAR0 */
3123 #define busnum_BDK_GICD_SETSPI_SR 0
3124 #define arguments_BDK_GICD_SETSPI_SR -1,-1,-1,-1
3125
3126 /**
3127 * Register (NCB32b) gicd_sstatusr
3128 *
3129 * GIC Distributor (Secure) Status Register
3130 */
3131 union bdk_gicd_sstatusr
3132 {
3133 uint32_t u;
3134 struct bdk_gicd_sstatusr_s
3135 {
3136 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3137 uint32_t reserved_4_31 : 28;
3138 uint32_t wrod : 1; /**< [ 3: 3](R/W) This bit is set if a write to a read-only location is detected. Software must write a one
3139 to this bit to clear it. */
3140 uint32_t rwod : 1; /**< [ 2: 2](R/W) This bit is set if a read to a write-only location is detected. Software must write a one
3141 to this bit to clear it. */
3142 uint32_t wrd : 1; /**< [ 1: 1](R/W) This bit is set if a write to a reserved location is detected. Software must write a one
3143 to this bit to clear it. */
3144 uint32_t rrd : 1; /**< [ 0: 0](R/W) This bit is set if a read to a reserved location is detected. Software must write a one to
3145 this bit to clear it. */
3146 #else /* Word 0 - Little Endian */
3147 uint32_t rrd : 1; /**< [ 0: 0](R/W) This bit is set if a read to a reserved location is detected. Software must write a one to
3148 this bit to clear it. */
3149 uint32_t wrd : 1; /**< [ 1: 1](R/W) This bit is set if a write to a reserved location is detected. Software must write a one
3150 to this bit to clear it. */
3151 uint32_t rwod : 1; /**< [ 2: 2](R/W) This bit is set if a read to a write-only location is detected. Software must write a one
3152 to this bit to clear it. */
3153 uint32_t wrod : 1; /**< [ 3: 3](R/W) This bit is set if a write to a read-only location is detected. Software must write a one
3154 to this bit to clear it. */
3155 uint32_t reserved_4_31 : 28;
3156 #endif /* Word 0 - End */
3157 } s;
3158 struct bdk_gicd_sstatusr_cn9
3159 {
3160 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3161 uint32_t reserved_4_31 : 28;
3162 uint32_t wrod : 1; /**< [ 3: 3](R/W/H) This bit is set if a write to a read-only location is detected. Software must write a one
3163 to this bit to clear it. */
3164 uint32_t rwod : 1; /**< [ 2: 2](R/W/H) This bit is set if a read to a write-only location is detected. Software must write a one
3165 to this bit to clear it. */
3166 uint32_t wrd : 1; /**< [ 1: 1](R/W/H) This bit is set if a write to a reserved location is detected. Software must write a one
3167 to this bit to clear it. */
3168 uint32_t rrd : 1; /**< [ 0: 0](R/W/H) This bit is set if a read to a reserved location is detected. Software must write a one to
3169 this bit to clear it. */
3170 #else /* Word 0 - Little Endian */
3171 uint32_t rrd : 1; /**< [ 0: 0](R/W/H) This bit is set if a read to a reserved location is detected. Software must write a one to
3172 this bit to clear it. */
3173 uint32_t wrd : 1; /**< [ 1: 1](R/W/H) This bit is set if a write to a reserved location is detected. Software must write a one
3174 to this bit to clear it. */
3175 uint32_t rwod : 1; /**< [ 2: 2](R/W/H) This bit is set if a read to a write-only location is detected. Software must write a one
3176 to this bit to clear it. */
3177 uint32_t wrod : 1; /**< [ 3: 3](R/W/H) This bit is set if a write to a read-only location is detected. Software must write a one
3178 to this bit to clear it. */
3179 uint32_t reserved_4_31 : 28;
3180 #endif /* Word 0 - End */
3181 } cn9;
3182 /* struct bdk_gicd_sstatusr_cn9 cn81xx; */
3183 /* struct bdk_gicd_sstatusr_s cn88xx; */
3184 /* struct bdk_gicd_sstatusr_cn9 cn83xx; */
3185 };
3186 typedef union bdk_gicd_sstatusr bdk_gicd_sstatusr_t;
3187
3188 #define BDK_GICD_SSTATUSR BDK_GICD_SSTATUSR_FUNC()
3189 static inline uint64_t BDK_GICD_SSTATUSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_SSTATUSR_FUNC(void)3190 static inline uint64_t BDK_GICD_SSTATUSR_FUNC(void)
3191 {
3192 return 0x801000000010ll;
3193 }
3194
3195 #define typedef_BDK_GICD_SSTATUSR bdk_gicd_sstatusr_t
3196 #define bustype_BDK_GICD_SSTATUSR BDK_CSR_TYPE_NCB32b
3197 #define basename_BDK_GICD_SSTATUSR "GICD_SSTATUSR"
3198 #define device_bar_BDK_GICD_SSTATUSR 0x0 /* PF_BAR0 */
3199 #define busnum_BDK_GICD_SSTATUSR 0
3200 #define arguments_BDK_GICD_SSTATUSR -1,-1,-1,-1
3201
3202 /**
3203 * Register (NCB32b) gicd_typer
3204 *
3205 * GIC Distributor Type Register
3206 * Describes features supported by the distributor.
3207 */
3208 union bdk_gicd_typer
3209 {
3210 uint32_t u;
3211 struct bdk_gicd_typer_s
3212 {
3213 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3214 uint32_t reserved_25_31 : 7;
3215 uint32_t a3v : 1; /**< [ 24: 24](RO) Indicates whether the distributor supports nonzero values of affinity 3. */
3216 uint32_t idbits : 5; /**< [ 23: 19](RO) The number of interrupt identifier bits supported by the GIC stream protocol interface minus one. */
3217 uint32_t dvis : 1; /**< [ 18: 18](RO) Direct virtual LPI injection supported. */
3218 uint32_t lpis : 1; /**< [ 17: 17](RO) Locality-specific peripheral interrupt supported. */
3219 uint32_t mbis : 1; /**< [ 16: 16](RO) Message based interrupt supported. */
3220 uint32_t lspi : 5; /**< [ 15: 11](RO) The number of lockable SPI interrupts. This is not supported in GICv3 and is RES0. */
3221 uint32_t securityextn : 1; /**< [ 10: 10](RO) Security extension supported. When GICD_(S)CTLR[DS] is
3222 set, this field is clear. */
3223 uint32_t reserved_8_9 : 2;
3224 uint32_t cpunumber : 3; /**< [ 7: 5](RO) Reserved. In CNXXXX implementation, not used. */
3225 uint32_t itlinesnumber : 5; /**< [ 4: 0](RO) The value derived from this specifies the maximum number of SPIs. */
3226 #else /* Word 0 - Little Endian */
3227 uint32_t itlinesnumber : 5; /**< [ 4: 0](RO) The value derived from this specifies the maximum number of SPIs. */
3228 uint32_t cpunumber : 3; /**< [ 7: 5](RO) Reserved. In CNXXXX implementation, not used. */
3229 uint32_t reserved_8_9 : 2;
3230 uint32_t securityextn : 1; /**< [ 10: 10](RO) Security extension supported. When GICD_(S)CTLR[DS] is
3231 set, this field is clear. */
3232 uint32_t lspi : 5; /**< [ 15: 11](RO) The number of lockable SPI interrupts. This is not supported in GICv3 and is RES0. */
3233 uint32_t mbis : 1; /**< [ 16: 16](RO) Message based interrupt supported. */
3234 uint32_t lpis : 1; /**< [ 17: 17](RO) Locality-specific peripheral interrupt supported. */
3235 uint32_t dvis : 1; /**< [ 18: 18](RO) Direct virtual LPI injection supported. */
3236 uint32_t idbits : 5; /**< [ 23: 19](RO) The number of interrupt identifier bits supported by the GIC stream protocol interface minus one. */
3237 uint32_t a3v : 1; /**< [ 24: 24](RO) Indicates whether the distributor supports nonzero values of affinity 3. */
3238 uint32_t reserved_25_31 : 7;
3239 #endif /* Word 0 - End */
3240 } s;
3241 /* struct bdk_gicd_typer_s cn; */
3242 };
3243 typedef union bdk_gicd_typer bdk_gicd_typer_t;
3244
3245 #define BDK_GICD_TYPER BDK_GICD_TYPER_FUNC()
3246 static inline uint64_t BDK_GICD_TYPER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GICD_TYPER_FUNC(void)3247 static inline uint64_t BDK_GICD_TYPER_FUNC(void)
3248 {
3249 return 0x801000000004ll;
3250 }
3251
3252 #define typedef_BDK_GICD_TYPER bdk_gicd_typer_t
3253 #define bustype_BDK_GICD_TYPER BDK_CSR_TYPE_NCB32b
3254 #define basename_BDK_GICD_TYPER "GICD_TYPER"
3255 #define device_bar_BDK_GICD_TYPER 0x0 /* PF_BAR0 */
3256 #define busnum_BDK_GICD_TYPER 0
3257 #define arguments_BDK_GICD_TYPER -1,-1,-1,-1
3258
3259 /**
3260 * Register (NCB32b) gicr#_cidr0
3261 *
3262 * GIC Redistributor Component Identification Register 0
3263 */
3264 union bdk_gicrx_cidr0
3265 {
3266 uint32_t u;
3267 struct bdk_gicrx_cidr0_s
3268 {
3269 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3270 uint32_t reserved_8_31 : 24;
3271 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3272 #else /* Word 0 - Little Endian */
3273 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3274 uint32_t reserved_8_31 : 24;
3275 #endif /* Word 0 - End */
3276 } s;
3277 /* struct bdk_gicrx_cidr0_s cn; */
3278 };
3279 typedef union bdk_gicrx_cidr0 bdk_gicrx_cidr0_t;
3280
3281 static inline uint64_t BDK_GICRX_CIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_CIDR0(unsigned long a)3282 static inline uint64_t BDK_GICRX_CIDR0(unsigned long a)
3283 {
3284 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3285 return 0x80108000fff0ll + 0x20000ll * ((a) & 0x3);
3286 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3287 return 0x80108000fff0ll + 0x20000ll * ((a) & 0x1f);
3288 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3289 return 0x80108000fff0ll + 0x20000ll * ((a) & 0x3f);
3290 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3291 return 0x80108000fff0ll + 0x20000ll * ((a) & 0x1f);
3292 __bdk_csr_fatal("GICRX_CIDR0", 1, a, 0, 0, 0);
3293 }
3294
3295 #define typedef_BDK_GICRX_CIDR0(a) bdk_gicrx_cidr0_t
3296 #define bustype_BDK_GICRX_CIDR0(a) BDK_CSR_TYPE_NCB32b
3297 #define basename_BDK_GICRX_CIDR0(a) "GICRX_CIDR0"
3298 #define device_bar_BDK_GICRX_CIDR0(a) 0x4 /* PF_BAR4 */
3299 #define busnum_BDK_GICRX_CIDR0(a) (a)
3300 #define arguments_BDK_GICRX_CIDR0(a) (a),-1,-1,-1
3301
3302 /**
3303 * Register (NCB32b) gicr#_cidr1
3304 *
3305 * GIC Redistributor Component Identification Register 1
3306 */
3307 union bdk_gicrx_cidr1
3308 {
3309 uint32_t u;
3310 struct bdk_gicrx_cidr1_s
3311 {
3312 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3313 uint32_t reserved_8_31 : 24;
3314 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3315 #else /* Word 0 - Little Endian */
3316 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3317 uint32_t reserved_8_31 : 24;
3318 #endif /* Word 0 - End */
3319 } s;
3320 /* struct bdk_gicrx_cidr1_s cn; */
3321 };
3322 typedef union bdk_gicrx_cidr1 bdk_gicrx_cidr1_t;
3323
3324 static inline uint64_t BDK_GICRX_CIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_CIDR1(unsigned long a)3325 static inline uint64_t BDK_GICRX_CIDR1(unsigned long a)
3326 {
3327 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3328 return 0x80108000fff4ll + 0x20000ll * ((a) & 0x3);
3329 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3330 return 0x80108000fff4ll + 0x20000ll * ((a) & 0x1f);
3331 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3332 return 0x80108000fff4ll + 0x20000ll * ((a) & 0x3f);
3333 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3334 return 0x80108000fff4ll + 0x20000ll * ((a) & 0x1f);
3335 __bdk_csr_fatal("GICRX_CIDR1", 1, a, 0, 0, 0);
3336 }
3337
3338 #define typedef_BDK_GICRX_CIDR1(a) bdk_gicrx_cidr1_t
3339 #define bustype_BDK_GICRX_CIDR1(a) BDK_CSR_TYPE_NCB32b
3340 #define basename_BDK_GICRX_CIDR1(a) "GICRX_CIDR1"
3341 #define device_bar_BDK_GICRX_CIDR1(a) 0x4 /* PF_BAR4 */
3342 #define busnum_BDK_GICRX_CIDR1(a) (a)
3343 #define arguments_BDK_GICRX_CIDR1(a) (a),-1,-1,-1
3344
3345 /**
3346 * Register (NCB32b) gicr#_cidr2
3347 *
3348 * GIC Redistributor Component Identification Register 2
3349 */
3350 union bdk_gicrx_cidr2
3351 {
3352 uint32_t u;
3353 struct bdk_gicrx_cidr2_s
3354 {
3355 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3356 uint32_t reserved_8_31 : 24;
3357 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3358 #else /* Word 0 - Little Endian */
3359 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3360 uint32_t reserved_8_31 : 24;
3361 #endif /* Word 0 - End */
3362 } s;
3363 /* struct bdk_gicrx_cidr2_s cn; */
3364 };
3365 typedef union bdk_gicrx_cidr2 bdk_gicrx_cidr2_t;
3366
3367 static inline uint64_t BDK_GICRX_CIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_CIDR2(unsigned long a)3368 static inline uint64_t BDK_GICRX_CIDR2(unsigned long a)
3369 {
3370 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3371 return 0x80108000fff8ll + 0x20000ll * ((a) & 0x3);
3372 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3373 return 0x80108000fff8ll + 0x20000ll * ((a) & 0x1f);
3374 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3375 return 0x80108000fff8ll + 0x20000ll * ((a) & 0x3f);
3376 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3377 return 0x80108000fff8ll + 0x20000ll * ((a) & 0x1f);
3378 __bdk_csr_fatal("GICRX_CIDR2", 1, a, 0, 0, 0);
3379 }
3380
3381 #define typedef_BDK_GICRX_CIDR2(a) bdk_gicrx_cidr2_t
3382 #define bustype_BDK_GICRX_CIDR2(a) BDK_CSR_TYPE_NCB32b
3383 #define basename_BDK_GICRX_CIDR2(a) "GICRX_CIDR2"
3384 #define device_bar_BDK_GICRX_CIDR2(a) 0x4 /* PF_BAR4 */
3385 #define busnum_BDK_GICRX_CIDR2(a) (a)
3386 #define arguments_BDK_GICRX_CIDR2(a) (a),-1,-1,-1
3387
3388 /**
3389 * Register (NCB32b) gicr#_cidr3
3390 *
3391 * GIC Redistributor Component Identification Register 3
3392 */
3393 union bdk_gicrx_cidr3
3394 {
3395 uint32_t u;
3396 struct bdk_gicrx_cidr3_s
3397 {
3398 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3399 uint32_t reserved_8_31 : 24;
3400 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3401 #else /* Word 0 - Little Endian */
3402 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3403 uint32_t reserved_8_31 : 24;
3404 #endif /* Word 0 - End */
3405 } s;
3406 /* struct bdk_gicrx_cidr3_s cn; */
3407 };
3408 typedef union bdk_gicrx_cidr3 bdk_gicrx_cidr3_t;
3409
3410 static inline uint64_t BDK_GICRX_CIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_CIDR3(unsigned long a)3411 static inline uint64_t BDK_GICRX_CIDR3(unsigned long a)
3412 {
3413 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3414 return 0x80108000fffcll + 0x20000ll * ((a) & 0x3);
3415 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3416 return 0x80108000fffcll + 0x20000ll * ((a) & 0x1f);
3417 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3418 return 0x80108000fffcll + 0x20000ll * ((a) & 0x3f);
3419 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3420 return 0x80108000fffcll + 0x20000ll * ((a) & 0x1f);
3421 __bdk_csr_fatal("GICRX_CIDR3", 1, a, 0, 0, 0);
3422 }
3423
3424 #define typedef_BDK_GICRX_CIDR3(a) bdk_gicrx_cidr3_t
3425 #define bustype_BDK_GICRX_CIDR3(a) BDK_CSR_TYPE_NCB32b
3426 #define basename_BDK_GICRX_CIDR3(a) "GICRX_CIDR3"
3427 #define device_bar_BDK_GICRX_CIDR3(a) 0x4 /* PF_BAR4 */
3428 #define busnum_BDK_GICRX_CIDR3(a) (a)
3429 #define arguments_BDK_GICRX_CIDR3(a) (a),-1,-1,-1
3430
3431 /**
3432 * Register (NCB) gicr#_clrlpir
3433 *
3434 * GIC Redistributor Clear LPI Register
3435 */
3436 union bdk_gicrx_clrlpir
3437 {
3438 uint64_t u;
3439 struct bdk_gicrx_clrlpir_s
3440 {
3441 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3442 uint64_t reserved_32_63 : 32;
3443 uint64_t pid : 32; /**< [ 31: 0](WO) Physical ID of the LPI to be set as not pending. If the LPI is already not pending, the
3444 write has no effect.
3445 If the LPI with the physical ID is not implemented, the write has no effect.
3446 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
3447 #else /* Word 0 - Little Endian */
3448 uint64_t pid : 32; /**< [ 31: 0](WO) Physical ID of the LPI to be set as not pending. If the LPI is already not pending, the
3449 write has no effect.
3450 If the LPI with the physical ID is not implemented, the write has no effect.
3451 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
3452 uint64_t reserved_32_63 : 32;
3453 #endif /* Word 0 - End */
3454 } s;
3455 /* struct bdk_gicrx_clrlpir_s cn; */
3456 };
3457 typedef union bdk_gicrx_clrlpir bdk_gicrx_clrlpir_t;
3458
3459 static inline uint64_t BDK_GICRX_CLRLPIR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_CLRLPIR(unsigned long a)3460 static inline uint64_t BDK_GICRX_CLRLPIR(unsigned long a)
3461 {
3462 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3463 return 0x801080000048ll + 0x20000ll * ((a) & 0x3);
3464 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3465 return 0x801080000048ll + 0x20000ll * ((a) & 0x1f);
3466 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3467 return 0x801080000048ll + 0x20000ll * ((a) & 0x3f);
3468 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3469 return 0x801080000048ll + 0x20000ll * ((a) & 0x1f);
3470 __bdk_csr_fatal("GICRX_CLRLPIR", 1, a, 0, 0, 0);
3471 }
3472
3473 #define typedef_BDK_GICRX_CLRLPIR(a) bdk_gicrx_clrlpir_t
3474 #define bustype_BDK_GICRX_CLRLPIR(a) BDK_CSR_TYPE_NCB
3475 #define basename_BDK_GICRX_CLRLPIR(a) "GICRX_CLRLPIR"
3476 #define device_bar_BDK_GICRX_CLRLPIR(a) 0x4 /* PF_BAR4 */
3477 #define busnum_BDK_GICRX_CLRLPIR(a) (a)
3478 #define arguments_BDK_GICRX_CLRLPIR(a) (a),-1,-1,-1
3479
3480 /**
3481 * Register (NCB32b) gicr#_icactiver0
3482 *
3483 * GIC Redistributor Interrupt Clear-Active Register 0
3484 * Each bit in GICR()_ICACTIVER0 provides a clear-active bit for an SGI or a
3485 * PPI. Writing one to a clear-active bit clears the active status of the corresponding
3486 * interrupt.
3487 */
3488 union bdk_gicrx_icactiver0
3489 {
3490 uint32_t u;
3491 struct bdk_gicrx_icactiver0_s
3492 {
3493 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3494 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3495 zero, then the interrupt is not active. If read as one, the interrupt is in active state.
3496
3497 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
3498 may only be set by secure accesses.
3499
3500 A clear-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3501 #else /* Word 0 - Little Endian */
3502 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3503 zero, then the interrupt is not active. If read as one, the interrupt is in active state.
3504
3505 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
3506 may only be set by secure accesses.
3507
3508 A clear-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3509 #endif /* Word 0 - End */
3510 } s;
3511 struct bdk_gicrx_icactiver0_cn9
3512 {
3513 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3514 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3515 zero, then the interrupt is not active. If read as one, the interrupt is in active state.
3516
3517 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
3518 may only be set by secure accesses.
3519
3520 A clear-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3521 #else /* Word 0 - Little Endian */
3522 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3523 zero, then the interrupt is not active. If read as one, the interrupt is in active state.
3524
3525 Clear-active bits corresponding to secure interrupts (either group 0 or group 1)
3526 may only be set by secure accesses.
3527
3528 A clear-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3529 #endif /* Word 0 - End */
3530 } cn9;
3531 /* struct bdk_gicrx_icactiver0_cn9 cn81xx; */
3532 /* struct bdk_gicrx_icactiver0_s cn88xx; */
3533 /* struct bdk_gicrx_icactiver0_cn9 cn83xx; */
3534 };
3535 typedef union bdk_gicrx_icactiver0 bdk_gicrx_icactiver0_t;
3536
3537 static inline uint64_t BDK_GICRX_ICACTIVER0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ICACTIVER0(unsigned long a)3538 static inline uint64_t BDK_GICRX_ICACTIVER0(unsigned long a)
3539 {
3540 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3541 return 0x801080010380ll + 0x20000ll * ((a) & 0x3);
3542 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3543 return 0x801080010380ll + 0x20000ll * ((a) & 0x1f);
3544 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3545 return 0x801080010380ll + 0x20000ll * ((a) & 0x3f);
3546 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3547 return 0x801080010380ll + 0x20000ll * ((a) & 0x1f);
3548 __bdk_csr_fatal("GICRX_ICACTIVER0", 1, a, 0, 0, 0);
3549 }
3550
3551 #define typedef_BDK_GICRX_ICACTIVER0(a) bdk_gicrx_icactiver0_t
3552 #define bustype_BDK_GICRX_ICACTIVER0(a) BDK_CSR_TYPE_NCB32b
3553 #define basename_BDK_GICRX_ICACTIVER0(a) "GICRX_ICACTIVER0"
3554 #define device_bar_BDK_GICRX_ICACTIVER0(a) 0x4 /* PF_BAR4 */
3555 #define busnum_BDK_GICRX_ICACTIVER0(a) (a)
3556 #define arguments_BDK_GICRX_ICACTIVER0(a) (a),-1,-1,-1
3557
3558 /**
3559 * Register (NCB32b) gicr#_icenabler0
3560 *
3561 * GIC Redistributor Interrupt Clear-Enable Register 0
3562 * Each bit in GICR()_ICENABLER0 provides a clear-enable bit for an SGI or a PPI. Writing one to
3563 * a
3564 * clear-enable bit disables forwarding of the corresponding SGI or PPI from the redistributor
3565 * to the CPU interfaces. Reading a bit identifies whether the interrupt is enabled.
3566 */
3567 union bdk_gicrx_icenabler0
3568 {
3569 uint32_t u;
3570 struct bdk_gicrx_icenabler0_s
3571 {
3572 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3573 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. Upon reading,
3574 if a bit is zero, then the interrupt is not enabled to be forwarded to the CPU interface.
3575 Upon reading, if a bit is one, the SPI is enabled to be forwarded to the CPU interface.
3576
3577 Clear-enable bits corresponding to secure interrupts (either group 0 or group 1)
3578 may only be set by secure accesses.
3579
3580 Writes to the register cannot be considered complete until the effects of the write are
3581 visible throughout the affinity hierarchy. To ensure that an enable has been cleared,
3582 software must write to this register with bits set to clear the required enables. Software
3583 must then poll GICR()_(S)CTLR[RWP] (register writes pending) until it has the value zero. */
3584 #else /* Word 0 - Little Endian */
3585 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. Upon reading,
3586 if a bit is zero, then the interrupt is not enabled to be forwarded to the CPU interface.
3587 Upon reading, if a bit is one, the SPI is enabled to be forwarded to the CPU interface.
3588
3589 Clear-enable bits corresponding to secure interrupts (either group 0 or group 1)
3590 may only be set by secure accesses.
3591
3592 Writes to the register cannot be considered complete until the effects of the write are
3593 visible throughout the affinity hierarchy. To ensure that an enable has been cleared,
3594 software must write to this register with bits set to clear the required enables. Software
3595 must then poll GICR()_(S)CTLR[RWP] (register writes pending) until it has the value zero. */
3596 #endif /* Word 0 - End */
3597 } s;
3598 /* struct bdk_gicrx_icenabler0_s cn; */
3599 };
3600 typedef union bdk_gicrx_icenabler0 bdk_gicrx_icenabler0_t;
3601
3602 static inline uint64_t BDK_GICRX_ICENABLER0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ICENABLER0(unsigned long a)3603 static inline uint64_t BDK_GICRX_ICENABLER0(unsigned long a)
3604 {
3605 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3606 return 0x801080010180ll + 0x20000ll * ((a) & 0x3);
3607 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3608 return 0x801080010180ll + 0x20000ll * ((a) & 0x1f);
3609 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3610 return 0x801080010180ll + 0x20000ll * ((a) & 0x3f);
3611 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3612 return 0x801080010180ll + 0x20000ll * ((a) & 0x1f);
3613 __bdk_csr_fatal("GICRX_ICENABLER0", 1, a, 0, 0, 0);
3614 }
3615
3616 #define typedef_BDK_GICRX_ICENABLER0(a) bdk_gicrx_icenabler0_t
3617 #define bustype_BDK_GICRX_ICENABLER0(a) BDK_CSR_TYPE_NCB32b
3618 #define basename_BDK_GICRX_ICENABLER0(a) "GICRX_ICENABLER0"
3619 #define device_bar_BDK_GICRX_ICENABLER0(a) 0x4 /* PF_BAR4 */
3620 #define busnum_BDK_GICRX_ICENABLER0(a) (a)
3621 #define arguments_BDK_GICRX_ICENABLER0(a) (a),-1,-1,-1
3622
3623 /**
3624 * Register (NCB32b) gicr#_icfgr0
3625 *
3626 * GIC Redistributor Interrupt Configuration Register 0
3627 */
3628 union bdk_gicrx_icfgr0
3629 {
3630 uint32_t u;
3631 struct bdk_gicrx_icfgr0_s
3632 {
3633 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3634 uint32_t vec : 32; /**< [ 31: 0](RO) Two bits per SGI. Defines whether an SGI is level-sensitive or edge-triggered.
3635 Note SGIs are always edge-triggered, so Bit[1] for an SGI is RAO and read-only.
3636
3637 Bit[1] is zero, the interrupt is level-sensitive.
3638
3639 Bit[1] is one, the interrupt is edge-triggered.
3640
3641 Bit[0] Reserved.
3642
3643 If a secure interrupt, then its corresponding field is RAZ/WI to nonsecure accesses. */
3644 #else /* Word 0 - Little Endian */
3645 uint32_t vec : 32; /**< [ 31: 0](RO) Two bits per SGI. Defines whether an SGI is level-sensitive or edge-triggered.
3646 Note SGIs are always edge-triggered, so Bit[1] for an SGI is RAO and read-only.
3647
3648 Bit[1] is zero, the interrupt is level-sensitive.
3649
3650 Bit[1] is one, the interrupt is edge-triggered.
3651
3652 Bit[0] Reserved.
3653
3654 If a secure interrupt, then its corresponding field is RAZ/WI to nonsecure accesses. */
3655 #endif /* Word 0 - End */
3656 } s;
3657 /* struct bdk_gicrx_icfgr0_s cn; */
3658 };
3659 typedef union bdk_gicrx_icfgr0 bdk_gicrx_icfgr0_t;
3660
3661 static inline uint64_t BDK_GICRX_ICFGR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ICFGR0(unsigned long a)3662 static inline uint64_t BDK_GICRX_ICFGR0(unsigned long a)
3663 {
3664 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3665 return 0x801080010c00ll + 0x20000ll * ((a) & 0x3);
3666 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3667 return 0x801080010c00ll + 0x20000ll * ((a) & 0x1f);
3668 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3669 return 0x801080010c00ll + 0x20000ll * ((a) & 0x3f);
3670 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3671 return 0x801080010c00ll + 0x20000ll * ((a) & 0x1f);
3672 __bdk_csr_fatal("GICRX_ICFGR0", 1, a, 0, 0, 0);
3673 }
3674
3675 #define typedef_BDK_GICRX_ICFGR0(a) bdk_gicrx_icfgr0_t
3676 #define bustype_BDK_GICRX_ICFGR0(a) BDK_CSR_TYPE_NCB32b
3677 #define basename_BDK_GICRX_ICFGR0(a) "GICRX_ICFGR0"
3678 #define device_bar_BDK_GICRX_ICFGR0(a) 0x4 /* PF_BAR4 */
3679 #define busnum_BDK_GICRX_ICFGR0(a) (a)
3680 #define arguments_BDK_GICRX_ICFGR0(a) (a),-1,-1,-1
3681
3682 /**
3683 * Register (NCB32b) gicr#_icfgr1
3684 *
3685 * GIC Redistributor Interrupt Configuration Register 1
3686 * Redistributor interrupt configuration register 1.
3687 */
3688 union bdk_gicrx_icfgr1
3689 {
3690 uint32_t u;
3691 struct bdk_gicrx_icfgr1_s
3692 {
3693 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3694 uint32_t vec : 32; /**< [ 31: 0](RO) Two bits per PPI. Defines whether an PPI is level-sensitive or edge-triggered.
3695
3696 Bit[1] is zero, the interrupt is level-sensitive.
3697
3698 Bit[1] is one, the interrupt is edge-triggered.
3699
3700 Bit[0] Reserved.
3701
3702 If a secure interrupt, then its corresponding field is RAZ/WI to nonsecure accesses. */
3703 #else /* Word 0 - Little Endian */
3704 uint32_t vec : 32; /**< [ 31: 0](RO) Two bits per PPI. Defines whether an PPI is level-sensitive or edge-triggered.
3705
3706 Bit[1] is zero, the interrupt is level-sensitive.
3707
3708 Bit[1] is one, the interrupt is edge-triggered.
3709
3710 Bit[0] Reserved.
3711
3712 If a secure interrupt, then its corresponding field is RAZ/WI to nonsecure accesses. */
3713 #endif /* Word 0 - End */
3714 } s;
3715 /* struct bdk_gicrx_icfgr1_s cn; */
3716 };
3717 typedef union bdk_gicrx_icfgr1 bdk_gicrx_icfgr1_t;
3718
3719 static inline uint64_t BDK_GICRX_ICFGR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ICFGR1(unsigned long a)3720 static inline uint64_t BDK_GICRX_ICFGR1(unsigned long a)
3721 {
3722 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3723 return 0x801080010c04ll + 0x20000ll * ((a) & 0x3);
3724 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3725 return 0x801080010c04ll + 0x20000ll * ((a) & 0x1f);
3726 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3727 return 0x801080010c04ll + 0x20000ll * ((a) & 0x3f);
3728 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3729 return 0x801080010c04ll + 0x20000ll * ((a) & 0x1f);
3730 __bdk_csr_fatal("GICRX_ICFGR1", 1, a, 0, 0, 0);
3731 }
3732
3733 #define typedef_BDK_GICRX_ICFGR1(a) bdk_gicrx_icfgr1_t
3734 #define bustype_BDK_GICRX_ICFGR1(a) BDK_CSR_TYPE_NCB32b
3735 #define basename_BDK_GICRX_ICFGR1(a) "GICRX_ICFGR1"
3736 #define device_bar_BDK_GICRX_ICFGR1(a) 0x4 /* PF_BAR4 */
3737 #define busnum_BDK_GICRX_ICFGR1(a) (a)
3738 #define arguments_BDK_GICRX_ICFGR1(a) (a),-1,-1,-1
3739
3740 /**
3741 * Register (NCB32b) gicr#_icpendr0
3742 *
3743 * GIC Redistributor Interrupt Clear-Pending Register 0
3744 * Each bit in GICR()_ICPENDR0 provides a clear-pending bit for an SGI or a PPI. Writing one to a
3745 * clear-pending bit clears the pending status of the corresponding interrupt.
3746 */
3747 union bdk_gicrx_icpendr0
3748 {
3749 uint32_t u;
3750 struct bdk_gicrx_icpendr0_s
3751 {
3752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3753 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3754 zero, then the interrupt is not pending. If read as one, the interrupt is in pending
3755 state.
3756
3757 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
3758 be set by secure accesses.
3759
3760 A clear-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3761 #else /* Word 0 - Little Endian */
3762 uint32_t vec : 32; /**< [ 31: 0](R/W1C) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3763 zero, then the interrupt is not pending. If read as one, the interrupt is in pending
3764 state.
3765
3766 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
3767 be set by secure accesses.
3768
3769 A clear-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3770 #endif /* Word 0 - End */
3771 } s;
3772 struct bdk_gicrx_icpendr0_cn9
3773 {
3774 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3775 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3776 zero, then the interrupt is not pending. If read as one, the interrupt is in pending
3777 state.
3778
3779 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
3780 be set by secure accesses.
3781
3782 A clear-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3783 #else /* Word 0 - Little Endian */
3784 uint32_t vec : 32; /**< [ 31: 0](R/W1C/H) Each bit corresponds to an SGI or a PPI for interrupt IDs in the range 31..0. If read as
3785 zero, then the interrupt is not pending. If read as one, the interrupt is in pending
3786 state.
3787
3788 Clear-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
3789 be set by secure accesses.
3790
3791 A clear-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
3792 #endif /* Word 0 - End */
3793 } cn9;
3794 /* struct bdk_gicrx_icpendr0_cn9 cn81xx; */
3795 /* struct bdk_gicrx_icpendr0_s cn88xx; */
3796 /* struct bdk_gicrx_icpendr0_cn9 cn83xx; */
3797 };
3798 typedef union bdk_gicrx_icpendr0 bdk_gicrx_icpendr0_t;
3799
3800 static inline uint64_t BDK_GICRX_ICPENDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ICPENDR0(unsigned long a)3801 static inline uint64_t BDK_GICRX_ICPENDR0(unsigned long a)
3802 {
3803 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3804 return 0x801080010280ll + 0x20000ll * ((a) & 0x3);
3805 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3806 return 0x801080010280ll + 0x20000ll * ((a) & 0x1f);
3807 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3808 return 0x801080010280ll + 0x20000ll * ((a) & 0x3f);
3809 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3810 return 0x801080010280ll + 0x20000ll * ((a) & 0x1f);
3811 __bdk_csr_fatal("GICRX_ICPENDR0", 1, a, 0, 0, 0);
3812 }
3813
3814 #define typedef_BDK_GICRX_ICPENDR0(a) bdk_gicrx_icpendr0_t
3815 #define bustype_BDK_GICRX_ICPENDR0(a) BDK_CSR_TYPE_NCB32b
3816 #define basename_BDK_GICRX_ICPENDR0(a) "GICRX_ICPENDR0"
3817 #define device_bar_BDK_GICRX_ICPENDR0(a) 0x4 /* PF_BAR4 */
3818 #define busnum_BDK_GICRX_ICPENDR0(a) (a)
3819 #define arguments_BDK_GICRX_ICPENDR0(a) (a),-1,-1,-1
3820
3821 /**
3822 * Register (NCB32b) gicr#_igroupr0
3823 *
3824 * GIC Redistributor Interrupt Group Secure Register
3825 */
3826 union bdk_gicrx_igroupr0
3827 {
3828 uint32_t u;
3829 struct bdk_gicrx_igroupr0_s
3830 {
3831 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3832 uint32_t ppi : 16; /**< [ 31: 16](SR/W) Groups for PPIs.
3833 0 = Group 0.
3834 1 = Group 1. */
3835 uint32_t sgi : 16; /**< [ 15: 0](SR/W) Groups for SGIs.
3836 0 = Group 0.
3837 1 = Group 1. */
3838 #else /* Word 0 - Little Endian */
3839 uint32_t sgi : 16; /**< [ 15: 0](SR/W) Groups for SGIs.
3840 0 = Group 0.
3841 1 = Group 1. */
3842 uint32_t ppi : 16; /**< [ 31: 16](SR/W) Groups for PPIs.
3843 0 = Group 0.
3844 1 = Group 1. */
3845 #endif /* Word 0 - End */
3846 } s;
3847 /* struct bdk_gicrx_igroupr0_s cn; */
3848 };
3849 typedef union bdk_gicrx_igroupr0 bdk_gicrx_igroupr0_t;
3850
3851 static inline uint64_t BDK_GICRX_IGROUPR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_IGROUPR0(unsigned long a)3852 static inline uint64_t BDK_GICRX_IGROUPR0(unsigned long a)
3853 {
3854 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3855 return 0x801080010080ll + 0x20000ll * ((a) & 0x3);
3856 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3857 return 0x801080010080ll + 0x20000ll * ((a) & 0x1f);
3858 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3859 return 0x801080010080ll + 0x20000ll * ((a) & 0x3f);
3860 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3861 return 0x801080010080ll + 0x20000ll * ((a) & 0x1f);
3862 __bdk_csr_fatal("GICRX_IGROUPR0", 1, a, 0, 0, 0);
3863 }
3864
3865 #define typedef_BDK_GICRX_IGROUPR0(a) bdk_gicrx_igroupr0_t
3866 #define bustype_BDK_GICRX_IGROUPR0(a) BDK_CSR_TYPE_NCB32b
3867 #define basename_BDK_GICRX_IGROUPR0(a) "GICRX_IGROUPR0"
3868 #define device_bar_BDK_GICRX_IGROUPR0(a) 0x4 /* PF_BAR4 */
3869 #define busnum_BDK_GICRX_IGROUPR0(a) (a)
3870 #define arguments_BDK_GICRX_IGROUPR0(a) (a),-1,-1,-1
3871
3872 /**
3873 * Register (NCB32b) gicr#_igrpmodr0
3874 *
3875 * GIC Redistributor Interrupt Group Secure Register
3876 * Control the group modifier for PPIs and SGIs, similar to GICD_IGRPMODR() for SPIs.
3877 */
3878 union bdk_gicrx_igrpmodr0
3879 {
3880 uint32_t u;
3881 struct bdk_gicrx_igrpmodr0_s
3882 {
3883 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3884 uint32_t ppi : 16; /**< [ 31: 16](SR/W) Group modifiers for PPIs.
3885 0 = No group modification.
3886 1 = Modify to group 1. */
3887 uint32_t sgi : 16; /**< [ 15: 0](SR/W) Group modifiers for SGIs.
3888 0 = No group modification.
3889 1 = Modify to group 1. */
3890 #else /* Word 0 - Little Endian */
3891 uint32_t sgi : 16; /**< [ 15: 0](SR/W) Group modifiers for SGIs.
3892 0 = No group modification.
3893 1 = Modify to group 1. */
3894 uint32_t ppi : 16; /**< [ 31: 16](SR/W) Group modifiers for PPIs.
3895 0 = No group modification.
3896 1 = Modify to group 1. */
3897 #endif /* Word 0 - End */
3898 } s;
3899 /* struct bdk_gicrx_igrpmodr0_s cn; */
3900 };
3901 typedef union bdk_gicrx_igrpmodr0 bdk_gicrx_igrpmodr0_t;
3902
3903 static inline uint64_t BDK_GICRX_IGRPMODR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_IGRPMODR0(unsigned long a)3904 static inline uint64_t BDK_GICRX_IGRPMODR0(unsigned long a)
3905 {
3906 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3907 return 0x801080010d00ll + 0x20000ll * ((a) & 0x3);
3908 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3909 return 0x801080010d00ll + 0x20000ll * ((a) & 0x1f);
3910 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3911 return 0x801080010d00ll + 0x20000ll * ((a) & 0x3f);
3912 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3913 return 0x801080010d00ll + 0x20000ll * ((a) & 0x1f);
3914 __bdk_csr_fatal("GICRX_IGRPMODR0", 1, a, 0, 0, 0);
3915 }
3916
3917 #define typedef_BDK_GICRX_IGRPMODR0(a) bdk_gicrx_igrpmodr0_t
3918 #define bustype_BDK_GICRX_IGRPMODR0(a) BDK_CSR_TYPE_NCB32b
3919 #define basename_BDK_GICRX_IGRPMODR0(a) "GICRX_IGRPMODR0"
3920 #define device_bar_BDK_GICRX_IGRPMODR0(a) 0x4 /* PF_BAR4 */
3921 #define busnum_BDK_GICRX_IGRPMODR0(a) (a)
3922 #define arguments_BDK_GICRX_IGRPMODR0(a) (a),-1,-1,-1
3923
3924 /**
3925 * Register (NCB32b) gicr#_iidr
3926 *
3927 * GIC Redistributor Implementation Identification Register
3928 * This 32-bit register is read-only and specifies the version and features supported by the
3929 * redistributor.
3930 */
3931 union bdk_gicrx_iidr
3932 {
3933 uint32_t u;
3934 struct bdk_gicrx_iidr_s
3935 {
3936 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3937 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
3938 In CNXXXX, enumerated by PCC_PROD_E. */
3939 uint32_t reserved_20_23 : 4;
3940 uint32_t variant : 4; /**< [ 19: 16](RO) Indicates the major revision or variant of the product.
3941 On CNXXXX, this is the major revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
3942 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
3943 On CNXXXX, this is the minor revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
3944 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer:
3945 0x34C = Cavium. */
3946 #else /* Word 0 - Little Endian */
3947 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer:
3948 0x34C = Cavium. */
3949 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
3950 On CNXXXX, this is the minor revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
3951 uint32_t variant : 4; /**< [ 19: 16](RO) Indicates the major revision or variant of the product.
3952 On CNXXXX, this is the major revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
3953 uint32_t reserved_20_23 : 4;
3954 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
3955 In CNXXXX, enumerated by PCC_PROD_E. */
3956 #endif /* Word 0 - End */
3957 } s;
3958 /* struct bdk_gicrx_iidr_s cn; */
3959 };
3960 typedef union bdk_gicrx_iidr bdk_gicrx_iidr_t;
3961
3962 static inline uint64_t BDK_GICRX_IIDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_IIDR(unsigned long a)3963 static inline uint64_t BDK_GICRX_IIDR(unsigned long a)
3964 {
3965 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
3966 return 0x801080000004ll + 0x20000ll * ((a) & 0x3);
3967 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
3968 return 0x801080000004ll + 0x20000ll * ((a) & 0x1f);
3969 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
3970 return 0x801080000004ll + 0x20000ll * ((a) & 0x3f);
3971 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
3972 return 0x801080000004ll + 0x20000ll * ((a) & 0x1f);
3973 __bdk_csr_fatal("GICRX_IIDR", 1, a, 0, 0, 0);
3974 }
3975
3976 #define typedef_BDK_GICRX_IIDR(a) bdk_gicrx_iidr_t
3977 #define bustype_BDK_GICRX_IIDR(a) BDK_CSR_TYPE_NCB32b
3978 #define basename_BDK_GICRX_IIDR(a) "GICRX_IIDR"
3979 #define device_bar_BDK_GICRX_IIDR(a) 0x4 /* PF_BAR4 */
3980 #define busnum_BDK_GICRX_IIDR(a) (a)
3981 #define arguments_BDK_GICRX_IIDR(a) (a),-1,-1,-1
3982
3983 /**
3984 * Register (NCB) gicr#_invallr
3985 *
3986 * GIC Redistributor LPI Invalidate All Register
3987 * This register is write-only and causes the LPI configuration to be reloaded from the table in
3988 * memory.
3989 */
3990 union bdk_gicrx_invallr
3991 {
3992 uint64_t u;
3993 struct bdk_gicrx_invallr_s
3994 {
3995 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3996 uint64_t reserved_0_63 : 64;
3997 #else /* Word 0 - Little Endian */
3998 uint64_t reserved_0_63 : 64;
3999 #endif /* Word 0 - End */
4000 } s;
4001 /* struct bdk_gicrx_invallr_s cn; */
4002 };
4003 typedef union bdk_gicrx_invallr bdk_gicrx_invallr_t;
4004
4005 static inline uint64_t BDK_GICRX_INVALLR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_INVALLR(unsigned long a)4006 static inline uint64_t BDK_GICRX_INVALLR(unsigned long a)
4007 {
4008 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4009 return 0x8010800000b0ll + 0x20000ll * ((a) & 0x3);
4010 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4011 return 0x8010800000b0ll + 0x20000ll * ((a) & 0x1f);
4012 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4013 return 0x8010800000b0ll + 0x20000ll * ((a) & 0x3f);
4014 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4015 return 0x8010800000b0ll + 0x20000ll * ((a) & 0x1f);
4016 __bdk_csr_fatal("GICRX_INVALLR", 1, a, 0, 0, 0);
4017 }
4018
4019 #define typedef_BDK_GICRX_INVALLR(a) bdk_gicrx_invallr_t
4020 #define bustype_BDK_GICRX_INVALLR(a) BDK_CSR_TYPE_NCB
4021 #define basename_BDK_GICRX_INVALLR(a) "GICRX_INVALLR"
4022 #define device_bar_BDK_GICRX_INVALLR(a) 0x4 /* PF_BAR4 */
4023 #define busnum_BDK_GICRX_INVALLR(a) (a)
4024 #define arguments_BDK_GICRX_INVALLR(a) (a),-1,-1,-1
4025
4026 /**
4027 * Register (NCB) gicr#_invlpir
4028 *
4029 * GIC Redistributor Invalidate LPI Register
4030 */
4031 union bdk_gicrx_invlpir
4032 {
4033 uint64_t u;
4034 struct bdk_gicrx_invlpir_s
4035 {
4036 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4037 uint64_t reserved_32_63 : 32;
4038 uint64_t pid : 32; /**< [ 31: 0](WO) Physical LPI ID to be cleaned. The invalidate in the register name and the ITS command is
4039 a misnomer. This actually results in a clean operation wherein the cached (in the
4040 redistributor) pending state of the LPI is updated to the pending table held in memory and
4041 its cached configuration is invalidated in the cache. */
4042 #else /* Word 0 - Little Endian */
4043 uint64_t pid : 32; /**< [ 31: 0](WO) Physical LPI ID to be cleaned. The invalidate in the register name and the ITS command is
4044 a misnomer. This actually results in a clean operation wherein the cached (in the
4045 redistributor) pending state of the LPI is updated to the pending table held in memory and
4046 its cached configuration is invalidated in the cache. */
4047 uint64_t reserved_32_63 : 32;
4048 #endif /* Word 0 - End */
4049 } s;
4050 /* struct bdk_gicrx_invlpir_s cn; */
4051 };
4052 typedef union bdk_gicrx_invlpir bdk_gicrx_invlpir_t;
4053
4054 static inline uint64_t BDK_GICRX_INVLPIR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_INVLPIR(unsigned long a)4055 static inline uint64_t BDK_GICRX_INVLPIR(unsigned long a)
4056 {
4057 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4058 return 0x8010800000a0ll + 0x20000ll * ((a) & 0x3);
4059 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4060 return 0x8010800000a0ll + 0x20000ll * ((a) & 0x1f);
4061 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4062 return 0x8010800000a0ll + 0x20000ll * ((a) & 0x3f);
4063 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4064 return 0x8010800000a0ll + 0x20000ll * ((a) & 0x1f);
4065 __bdk_csr_fatal("GICRX_INVLPIR", 1, a, 0, 0, 0);
4066 }
4067
4068 #define typedef_BDK_GICRX_INVLPIR(a) bdk_gicrx_invlpir_t
4069 #define bustype_BDK_GICRX_INVLPIR(a) BDK_CSR_TYPE_NCB
4070 #define basename_BDK_GICRX_INVLPIR(a) "GICRX_INVLPIR"
4071 #define device_bar_BDK_GICRX_INVLPIR(a) 0x4 /* PF_BAR4 */
4072 #define busnum_BDK_GICRX_INVLPIR(a) (a)
4073 #define arguments_BDK_GICRX_INVLPIR(a) (a),-1,-1,-1
4074
4075 /**
4076 * Register (NCB32b) gicr#_ipriorityr#
4077 *
4078 * GIC Redistributor Interrupt Priority Registers
4079 * Each byte in this register provides a priority field for each SGI or PPI supported by the
4080 * GIC.
4081 */
4082 union bdk_gicrx_ipriorityrx
4083 {
4084 uint32_t u;
4085 struct bdk_gicrx_ipriorityrx_s
4086 {
4087 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4088 uint32_t vec : 32; /**< [ 31: 0](R/W) Each byte corresponds to an SGI or PPI for interrupt IDs in the range 31..0.
4089
4090 Priority fields corresponding to secure interrupts (either group 0 or group 1)
4091 may only be set by secure accesses, or when GICD_(S)CTLR[DS] is one.
4092
4093 Byte accesses are permitted to these registers.
4094
4095 A priority field for a secure interrupt is RAZ/WI to nonsecure accesses. */
4096 #else /* Word 0 - Little Endian */
4097 uint32_t vec : 32; /**< [ 31: 0](R/W) Each byte corresponds to an SGI or PPI for interrupt IDs in the range 31..0.
4098
4099 Priority fields corresponding to secure interrupts (either group 0 or group 1)
4100 may only be set by secure accesses, or when GICD_(S)CTLR[DS] is one.
4101
4102 Byte accesses are permitted to these registers.
4103
4104 A priority field for a secure interrupt is RAZ/WI to nonsecure accesses. */
4105 #endif /* Word 0 - End */
4106 } s;
4107 /* struct bdk_gicrx_ipriorityrx_s cn; */
4108 };
4109 typedef union bdk_gicrx_ipriorityrx bdk_gicrx_ipriorityrx_t;
4110
4111 static inline uint64_t BDK_GICRX_IPRIORITYRX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GICRX_IPRIORITYRX(unsigned long a,unsigned long b)4112 static inline uint64_t BDK_GICRX_IPRIORITYRX(unsigned long a, unsigned long b)
4113 {
4114 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=7)))
4115 return 0x801080010400ll + 0x20000ll * ((a) & 0x3) + 4ll * ((b) & 0x7);
4116 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=23) && (b<=7)))
4117 return 0x801080010400ll + 0x20000ll * ((a) & 0x1f) + 4ll * ((b) & 0x7);
4118 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=47) && (b<=7)))
4119 return 0x801080010400ll + 0x20000ll * ((a) & 0x3f) + 4ll * ((b) & 0x7);
4120 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=23) && (b<=7)))
4121 return 0x801080010400ll + 0x20000ll * ((a) & 0x1f) + 4ll * ((b) & 0x7);
4122 __bdk_csr_fatal("GICRX_IPRIORITYRX", 2, a, b, 0, 0);
4123 }
4124
4125 #define typedef_BDK_GICRX_IPRIORITYRX(a,b) bdk_gicrx_ipriorityrx_t
4126 #define bustype_BDK_GICRX_IPRIORITYRX(a,b) BDK_CSR_TYPE_NCB32b
4127 #define basename_BDK_GICRX_IPRIORITYRX(a,b) "GICRX_IPRIORITYRX"
4128 #define device_bar_BDK_GICRX_IPRIORITYRX(a,b) 0x4 /* PF_BAR4 */
4129 #define busnum_BDK_GICRX_IPRIORITYRX(a,b) (a)
4130 #define arguments_BDK_GICRX_IPRIORITYRX(a,b) (a),(b),-1,-1
4131
4132 /**
4133 * Register (NCB32b) gicr#_isactiver0
4134 *
4135 * GIC Redistributor Interrupt Set-Active Register 0
4136 * Each bit in GICR()_ISACTIVER0 provides a set-active bit for an SGI or a PPI. Writing one to a
4137 * set-active bit sets the status of the corresponding interrupt to active.
4138 */
4139 union bdk_gicrx_isactiver0
4140 {
4141 uint32_t u;
4142 struct bdk_gicrx_isactiver0_s
4143 {
4144 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4145 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4146 read as zero, then the interrupt is not active. If read as one, the interrupt is
4147 in active state.
4148
4149 Set-active bits corresponding to secure interrupts (either group 0 or group 1) may only be
4150 set by secure accesses.
4151
4152 A set-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4153 #else /* Word 0 - Little Endian */
4154 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4155 read as zero, then the interrupt is not active. If read as one, the interrupt is
4156 in active state.
4157
4158 Set-active bits corresponding to secure interrupts (either group 0 or group 1) may only be
4159 set by secure accesses.
4160
4161 A set-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4162 #endif /* Word 0 - End */
4163 } s;
4164 struct bdk_gicrx_isactiver0_cn9
4165 {
4166 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4167 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4168 read as zero, then the interrupt is not active. If read as one, the interrupt is
4169 in active state.
4170
4171 Set-active bits corresponding to secure interrupts (either group 0 or group 1) may only be
4172 set by secure accesses.
4173
4174 A set-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4175 #else /* Word 0 - Little Endian */
4176 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4177 read as zero, then the interrupt is not active. If read as one, the interrupt is
4178 in active state.
4179
4180 Set-active bits corresponding to secure interrupts (either group 0 or group 1) may only be
4181 set by secure accesses.
4182
4183 A set-active bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4184 #endif /* Word 0 - End */
4185 } cn9;
4186 /* struct bdk_gicrx_isactiver0_cn9 cn81xx; */
4187 /* struct bdk_gicrx_isactiver0_s cn88xx; */
4188 /* struct bdk_gicrx_isactiver0_cn9 cn83xx; */
4189 };
4190 typedef union bdk_gicrx_isactiver0 bdk_gicrx_isactiver0_t;
4191
4192 static inline uint64_t BDK_GICRX_ISACTIVER0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ISACTIVER0(unsigned long a)4193 static inline uint64_t BDK_GICRX_ISACTIVER0(unsigned long a)
4194 {
4195 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4196 return 0x801080010300ll + 0x20000ll * ((a) & 0x3);
4197 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4198 return 0x801080010300ll + 0x20000ll * ((a) & 0x1f);
4199 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4200 return 0x801080010300ll + 0x20000ll * ((a) & 0x3f);
4201 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4202 return 0x801080010300ll + 0x20000ll * ((a) & 0x1f);
4203 __bdk_csr_fatal("GICRX_ISACTIVER0", 1, a, 0, 0, 0);
4204 }
4205
4206 #define typedef_BDK_GICRX_ISACTIVER0(a) bdk_gicrx_isactiver0_t
4207 #define bustype_BDK_GICRX_ISACTIVER0(a) BDK_CSR_TYPE_NCB32b
4208 #define basename_BDK_GICRX_ISACTIVER0(a) "GICRX_ISACTIVER0"
4209 #define device_bar_BDK_GICRX_ISACTIVER0(a) 0x4 /* PF_BAR4 */
4210 #define busnum_BDK_GICRX_ISACTIVER0(a) (a)
4211 #define arguments_BDK_GICRX_ISACTIVER0(a) (a),-1,-1,-1
4212
4213 /**
4214 * Register (NCB32b) gicr#_isenabler0
4215 *
4216 * GIC Redistributor Interrupt Set-Enable Register 0
4217 * Each bit in GICR()_ISENABLER0 provides a set-enable bit for an SGI or a PPI. Writing one
4218 * to a set-enable bit enables forwarding of the corresponding SGI or PPI from the
4219 * redistributor to the CPU interfaces.
4220 */
4221 union bdk_gicrx_isenabler0
4222 {
4223 uint32_t u;
4224 struct bdk_gicrx_isenabler0_s
4225 {
4226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4227 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4228 zero, then the interrupt is not enabled to be forwarded to the CPU interface. If
4229 one, the interrupt is enabled to be forwarded to the CPU interface. Set-enable
4230 bits corresponding to secure interrupts (either group0 or group1) may only be
4231 set by secure accesses. */
4232 #else /* Word 0 - Little Endian */
4233 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4234 zero, then the interrupt is not enabled to be forwarded to the CPU interface. If
4235 one, the interrupt is enabled to be forwarded to the CPU interface. Set-enable
4236 bits corresponding to secure interrupts (either group0 or group1) may only be
4237 set by secure accesses. */
4238 #endif /* Word 0 - End */
4239 } s;
4240 /* struct bdk_gicrx_isenabler0_s cn; */
4241 };
4242 typedef union bdk_gicrx_isenabler0 bdk_gicrx_isenabler0_t;
4243
4244 static inline uint64_t BDK_GICRX_ISENABLER0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ISENABLER0(unsigned long a)4245 static inline uint64_t BDK_GICRX_ISENABLER0(unsigned long a)
4246 {
4247 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4248 return 0x801080010100ll + 0x20000ll * ((a) & 0x3);
4249 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4250 return 0x801080010100ll + 0x20000ll * ((a) & 0x1f);
4251 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4252 return 0x801080010100ll + 0x20000ll * ((a) & 0x3f);
4253 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4254 return 0x801080010100ll + 0x20000ll * ((a) & 0x1f);
4255 __bdk_csr_fatal("GICRX_ISENABLER0", 1, a, 0, 0, 0);
4256 }
4257
4258 #define typedef_BDK_GICRX_ISENABLER0(a) bdk_gicrx_isenabler0_t
4259 #define bustype_BDK_GICRX_ISENABLER0(a) BDK_CSR_TYPE_NCB32b
4260 #define basename_BDK_GICRX_ISENABLER0(a) "GICRX_ISENABLER0"
4261 #define device_bar_BDK_GICRX_ISENABLER0(a) 0x4 /* PF_BAR4 */
4262 #define busnum_BDK_GICRX_ISENABLER0(a) (a)
4263 #define arguments_BDK_GICRX_ISENABLER0(a) (a),-1,-1,-1
4264
4265 /**
4266 * Register (NCB32b) gicr#_ispendr0
4267 *
4268 * GIC Redistributor Interrupt Set-Pending Register 0
4269 * Each bit in GICR()_ISPENDR0 provides a set-pending bit for an SGI or a PPI. Writing one
4270 * to a set-pending bit sets the status of the corresponding interrupt to pending.
4271 */
4272 union bdk_gicrx_ispendr0
4273 {
4274 uint32_t u;
4275 struct bdk_gicrx_ispendr0_s
4276 {
4277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4278 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4279 read as zero, then the interrupt is not pending. If read as one, the interrupt
4280 is in pending state.
4281
4282 Set-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
4283 be set by secure accesses.
4284
4285 A set-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4286 #else /* Word 0 - Little Endian */
4287 uint32_t vec : 32; /**< [ 31: 0](R/W1S) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4288 read as zero, then the interrupt is not pending. If read as one, the interrupt
4289 is in pending state.
4290
4291 Set-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
4292 be set by secure accesses.
4293
4294 A set-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4295 #endif /* Word 0 - End */
4296 } s;
4297 struct bdk_gicrx_ispendr0_cn9
4298 {
4299 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4300 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4301 read as zero, then the interrupt is not pending. If read as one, the interrupt
4302 is in pending state.
4303
4304 Set-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
4305 be set by secure accesses.
4306
4307 A set-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4308 #else /* Word 0 - Little Endian */
4309 uint32_t vec : 32; /**< [ 31: 0](R/W1S/H) Each bit corresponds to an SGI or PPI for interrupt IDs in the range 31..0. If
4310 read as zero, then the interrupt is not pending. If read as one, the interrupt
4311 is in pending state.
4312
4313 Set-pending bits corresponding to secure interrupts (either group 0 or group 1) may only
4314 be set by secure accesses.
4315
4316 A set-pending bit for a secure interrupt is RAZ/WI to nonsecure accesses. */
4317 #endif /* Word 0 - End */
4318 } cn9;
4319 /* struct bdk_gicrx_ispendr0_cn9 cn81xx; */
4320 /* struct bdk_gicrx_ispendr0_s cn88xx; */
4321 /* struct bdk_gicrx_ispendr0_cn9 cn83xx; */
4322 };
4323 typedef union bdk_gicrx_ispendr0 bdk_gicrx_ispendr0_t;
4324
4325 static inline uint64_t BDK_GICRX_ISPENDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_ISPENDR0(unsigned long a)4326 static inline uint64_t BDK_GICRX_ISPENDR0(unsigned long a)
4327 {
4328 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4329 return 0x801080010200ll + 0x20000ll * ((a) & 0x3);
4330 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4331 return 0x801080010200ll + 0x20000ll * ((a) & 0x1f);
4332 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4333 return 0x801080010200ll + 0x20000ll * ((a) & 0x3f);
4334 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4335 return 0x801080010200ll + 0x20000ll * ((a) & 0x1f);
4336 __bdk_csr_fatal("GICRX_ISPENDR0", 1, a, 0, 0, 0);
4337 }
4338
4339 #define typedef_BDK_GICRX_ISPENDR0(a) bdk_gicrx_ispendr0_t
4340 #define bustype_BDK_GICRX_ISPENDR0(a) BDK_CSR_TYPE_NCB32b
4341 #define basename_BDK_GICRX_ISPENDR0(a) "GICRX_ISPENDR0"
4342 #define device_bar_BDK_GICRX_ISPENDR0(a) 0x4 /* PF_BAR4 */
4343 #define busnum_BDK_GICRX_ISPENDR0(a) (a)
4344 #define arguments_BDK_GICRX_ISPENDR0(a) (a),-1,-1,-1
4345
4346 /**
4347 * Register (NCB) gicr#_movallr
4348 *
4349 * GIC Redistributor LPI Move All Register
4350 * This register is write-only and causes the LPI configuration to be reloaded from the table in
4351 * memory.
4352 */
4353 union bdk_gicrx_movallr
4354 {
4355 uint64_t u;
4356 struct bdk_gicrx_movallr_s
4357 {
4358 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4359 uint64_t pa : 32; /**< [ 63: 32](WO) Target address \<47:16\>. Base address of the redistributor to which pending LPIs are to be
4360 moved.
4361 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
4362 uint64_t reserved_0_31 : 32;
4363 #else /* Word 0 - Little Endian */
4364 uint64_t reserved_0_31 : 32;
4365 uint64_t pa : 32; /**< [ 63: 32](WO) Target address \<47:16\>. Base address of the redistributor to which pending LPIs are to be
4366 moved.
4367 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
4368 #endif /* Word 0 - End */
4369 } s;
4370 /* struct bdk_gicrx_movallr_s cn; */
4371 };
4372 typedef union bdk_gicrx_movallr bdk_gicrx_movallr_t;
4373
4374 static inline uint64_t BDK_GICRX_MOVALLR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_MOVALLR(unsigned long a)4375 static inline uint64_t BDK_GICRX_MOVALLR(unsigned long a)
4376 {
4377 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4378 return 0x801080000110ll + 0x20000ll * ((a) & 0x3);
4379 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4380 return 0x801080000110ll + 0x20000ll * ((a) & 0x1f);
4381 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4382 return 0x801080000110ll + 0x20000ll * ((a) & 0x3f);
4383 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4384 return 0x801080000110ll + 0x20000ll * ((a) & 0x1f);
4385 __bdk_csr_fatal("GICRX_MOVALLR", 1, a, 0, 0, 0);
4386 }
4387
4388 #define typedef_BDK_GICRX_MOVALLR(a) bdk_gicrx_movallr_t
4389 #define bustype_BDK_GICRX_MOVALLR(a) BDK_CSR_TYPE_NCB
4390 #define basename_BDK_GICRX_MOVALLR(a) "GICRX_MOVALLR"
4391 #define device_bar_BDK_GICRX_MOVALLR(a) 0x4 /* PF_BAR4 */
4392 #define busnum_BDK_GICRX_MOVALLR(a) (a)
4393 #define arguments_BDK_GICRX_MOVALLR(a) (a),-1,-1,-1
4394
4395 /**
4396 * Register (NCB) gicr#_movlpir
4397 *
4398 * GIC Redistributor Move LPI Register
4399 */
4400 union bdk_gicrx_movlpir
4401 {
4402 uint64_t u;
4403 struct bdk_gicrx_movlpir_s
4404 {
4405 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4406 uint64_t pa : 32; /**< [ 63: 32](WO) Target address \<47:16\>. Base address of the redistributor to which the physical LPI is to
4407 be moved. */
4408 uint64_t pid : 32; /**< [ 31: 0](WO) Physical LPI ID to be moved to the redistributor at [PA]. If the LPI with this
4409 PID is unimplemented, the write has no effect.
4410 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
4411 #else /* Word 0 - Little Endian */
4412 uint64_t pid : 32; /**< [ 31: 0](WO) Physical LPI ID to be moved to the redistributor at [PA]. If the LPI with this
4413 PID is unimplemented, the write has no effect.
4414 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
4415 uint64_t pa : 32; /**< [ 63: 32](WO) Target address \<47:16\>. Base address of the redistributor to which the physical LPI is to
4416 be moved. */
4417 #endif /* Word 0 - End */
4418 } s;
4419 /* struct bdk_gicrx_movlpir_s cn; */
4420 };
4421 typedef union bdk_gicrx_movlpir bdk_gicrx_movlpir_t;
4422
4423 static inline uint64_t BDK_GICRX_MOVLPIR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_MOVLPIR(unsigned long a)4424 static inline uint64_t BDK_GICRX_MOVLPIR(unsigned long a)
4425 {
4426 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4427 return 0x801080000100ll + 0x20000ll * ((a) & 0x3);
4428 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4429 return 0x801080000100ll + 0x20000ll * ((a) & 0x1f);
4430 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4431 return 0x801080000100ll + 0x20000ll * ((a) & 0x3f);
4432 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4433 return 0x801080000100ll + 0x20000ll * ((a) & 0x1f);
4434 __bdk_csr_fatal("GICRX_MOVLPIR", 1, a, 0, 0, 0);
4435 }
4436
4437 #define typedef_BDK_GICRX_MOVLPIR(a) bdk_gicrx_movlpir_t
4438 #define bustype_BDK_GICRX_MOVLPIR(a) BDK_CSR_TYPE_NCB
4439 #define basename_BDK_GICRX_MOVLPIR(a) "GICRX_MOVLPIR"
4440 #define device_bar_BDK_GICRX_MOVLPIR(a) 0x4 /* PF_BAR4 */
4441 #define busnum_BDK_GICRX_MOVLPIR(a) (a)
4442 #define arguments_BDK_GICRX_MOVLPIR(a) (a),-1,-1,-1
4443
4444 /**
4445 * Register (NCB32b) gicr#_nsacr
4446 *
4447 * GIC Redistributor Non-Secure Access Control Secure Registers
4448 */
4449 union bdk_gicrx_nsacr
4450 {
4451 uint32_t u;
4452 struct bdk_gicrx_nsacr_s
4453 {
4454 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4455 uint32_t vec : 32; /**< [ 31: 0](SR/W) Two bits per SGI or PPI. Defines whether nonsecure access is permitted to secure
4456 interrupt resources.
4457 0x0 = No nonsecure access is permitted to fields associated with the corresponding
4458 interrupt.
4459 0x1 = Nonsecure write access is permitted to generate secure group0 interrupts.
4460 0x2 = Adds nonsecure write access permissions to generate secure group1 interrupts.
4461 0x3 = Reserved. Treated as 0x1.
4462
4463 This register is RAZ/WI for nonsecure accesses.
4464
4465 When GICD_(S)CTLR[DS] is one, this register is RAZ/WI. */
4466 #else /* Word 0 - Little Endian */
4467 uint32_t vec : 32; /**< [ 31: 0](SR/W) Two bits per SGI or PPI. Defines whether nonsecure access is permitted to secure
4468 interrupt resources.
4469 0x0 = No nonsecure access is permitted to fields associated with the corresponding
4470 interrupt.
4471 0x1 = Nonsecure write access is permitted to generate secure group0 interrupts.
4472 0x2 = Adds nonsecure write access permissions to generate secure group1 interrupts.
4473 0x3 = Reserved. Treated as 0x1.
4474
4475 This register is RAZ/WI for nonsecure accesses.
4476
4477 When GICD_(S)CTLR[DS] is one, this register is RAZ/WI. */
4478 #endif /* Word 0 - End */
4479 } s;
4480 /* struct bdk_gicrx_nsacr_s cn; */
4481 };
4482 typedef union bdk_gicrx_nsacr bdk_gicrx_nsacr_t;
4483
4484 static inline uint64_t BDK_GICRX_NSACR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_NSACR(unsigned long a)4485 static inline uint64_t BDK_GICRX_NSACR(unsigned long a)
4486 {
4487 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4488 return 0x801080010e00ll + 0x20000ll * ((a) & 0x3);
4489 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4490 return 0x801080010e00ll + 0x20000ll * ((a) & 0x1f);
4491 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4492 return 0x801080010e00ll + 0x20000ll * ((a) & 0x3f);
4493 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4494 return 0x801080010e00ll + 0x20000ll * ((a) & 0x1f);
4495 __bdk_csr_fatal("GICRX_NSACR", 1, a, 0, 0, 0);
4496 }
4497
4498 #define typedef_BDK_GICRX_NSACR(a) bdk_gicrx_nsacr_t
4499 #define bustype_BDK_GICRX_NSACR(a) BDK_CSR_TYPE_NCB32b
4500 #define basename_BDK_GICRX_NSACR(a) "GICRX_NSACR"
4501 #define device_bar_BDK_GICRX_NSACR(a) 0x4 /* PF_BAR4 */
4502 #define busnum_BDK_GICRX_NSACR(a) (a)
4503 #define arguments_BDK_GICRX_NSACR(a) (a),-1,-1,-1
4504
4505 /**
4506 * Register (NCB) gicr#_pendbaser
4507 *
4508 * GIC Redistributor LPI Pending Table Address Register
4509 */
4510 union bdk_gicrx_pendbaser
4511 {
4512 uint64_t u;
4513 struct bdk_gicrx_pendbaser_s
4514 {
4515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4516 uint64_t reserved_63 : 1;
4517 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4518 0 = The coarse-grained map for the LPI pending table is valid.
4519 1 = The pending table has been zeroed out. */
4520 uint64_t reserved_59_61 : 3;
4521 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
4522 uint64_t reserved_52_55 : 4;
4523 uint64_t pa : 36; /**< [ 51: 16](R/W) Physical address bits \<46:16\> for the LPI pending table. */
4524 uint64_t reserved_12_15 : 4;
4525 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
4526 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
4527 uint64_t reserved_0_6 : 7;
4528 #else /* Word 0 - Little Endian */
4529 uint64_t reserved_0_6 : 7;
4530 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
4531 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
4532 uint64_t reserved_12_15 : 4;
4533 uint64_t pa : 36; /**< [ 51: 16](R/W) Physical address bits \<46:16\> for the LPI pending table. */
4534 uint64_t reserved_52_55 : 4;
4535 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
4536 uint64_t reserved_59_61 : 3;
4537 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4538 0 = The coarse-grained map for the LPI pending table is valid.
4539 1 = The pending table has been zeroed out. */
4540 uint64_t reserved_63 : 1;
4541 #endif /* Word 0 - End */
4542 } s;
4543 struct bdk_gicrx_pendbaser_cn88xxp1
4544 {
4545 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4546 uint64_t reserved_63 : 1;
4547 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4548 0 = The coarse-grained map for the LPI pending table is valid.
4549 1 = The pending table has been zeroed out. */
4550 uint64_t reserved_48_61 : 14;
4551 uint64_t pa : 32; /**< [ 47: 16](R/W) Physical address bits \<46:16\> for the LPI pending table. */
4552 uint64_t reserved_0_15 : 16;
4553 #else /* Word 0 - Little Endian */
4554 uint64_t reserved_0_15 : 16;
4555 uint64_t pa : 32; /**< [ 47: 16](R/W) Physical address bits \<46:16\> for the LPI pending table. */
4556 uint64_t reserved_48_61 : 14;
4557 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4558 0 = The coarse-grained map for the LPI pending table is valid.
4559 1 = The pending table has been zeroed out. */
4560 uint64_t reserved_63 : 1;
4561 #endif /* Word 0 - End */
4562 } cn88xxp1;
4563 struct bdk_gicrx_pendbaser_cn9
4564 {
4565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4566 uint64_t reserved_63 : 1;
4567 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4568 0 = The coarse-grained map for the LPI pending table is valid.
4569 1 = The pending table has been zeroed out. */
4570 uint64_t reserved_59_61 : 3;
4571 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
4572 uint64_t reserved_52_55 : 4;
4573 uint64_t pa : 36; /**< [ 51: 16](R/W) Physical address bits \<51:16\> for the LPI pending table.
4574 Software must set bits \<51:46\> and \<43\> to zero. */
4575 uint64_t reserved_12_15 : 4;
4576 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
4577 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
4578 uint64_t reserved_0_6 : 7;
4579 #else /* Word 0 - Little Endian */
4580 uint64_t reserved_0_6 : 7;
4581 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
4582 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
4583 uint64_t reserved_12_15 : 4;
4584 uint64_t pa : 36; /**< [ 51: 16](R/W) Physical address bits \<51:16\> for the LPI pending table.
4585 Software must set bits \<51:46\> and \<43\> to zero. */
4586 uint64_t reserved_52_55 : 4;
4587 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
4588 uint64_t reserved_59_61 : 3;
4589 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4590 0 = The coarse-grained map for the LPI pending table is valid.
4591 1 = The pending table has been zeroed out. */
4592 uint64_t reserved_63 : 1;
4593 #endif /* Word 0 - End */
4594 } cn9;
4595 struct bdk_gicrx_pendbaser_cn81xx
4596 {
4597 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4598 uint64_t reserved_63 : 1;
4599 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4600 0 = The coarse-grained map for the LPI pending table is valid.
4601 1 = The pending table has been zeroed out. */
4602 uint64_t reserved_59_61 : 3;
4603 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
4604 uint64_t reserved_48_55 : 8;
4605 uint64_t pa : 32; /**< [ 47: 16](R/W) Physical address bits \<46:16\> for the LPI pending table. */
4606 uint64_t reserved_12_15 : 4;
4607 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
4608 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
4609 uint64_t reserved_0_6 : 7;
4610 #else /* Word 0 - Little Endian */
4611 uint64_t reserved_0_6 : 7;
4612 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
4613 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
4614 uint64_t reserved_12_15 : 4;
4615 uint64_t pa : 32; /**< [ 47: 16](R/W) Physical address bits \<46:16\> for the LPI pending table. */
4616 uint64_t reserved_48_55 : 8;
4617 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
4618 uint64_t reserved_59_61 : 3;
4619 uint64_t pending_table_zero : 1; /**< [ 62: 62](WO) Pending zero:
4620 0 = The coarse-grained map for the LPI pending table is valid.
4621 1 = The pending table has been zeroed out. */
4622 uint64_t reserved_63 : 1;
4623 #endif /* Word 0 - End */
4624 } cn81xx;
4625 /* struct bdk_gicrx_pendbaser_cn81xx cn83xx; */
4626 /* struct bdk_gicrx_pendbaser_cn81xx cn88xxp2; */
4627 };
4628 typedef union bdk_gicrx_pendbaser bdk_gicrx_pendbaser_t;
4629
4630 static inline uint64_t BDK_GICRX_PENDBASER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PENDBASER(unsigned long a)4631 static inline uint64_t BDK_GICRX_PENDBASER(unsigned long a)
4632 {
4633 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4634 return 0x801080000078ll + 0x20000ll * ((a) & 0x3);
4635 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4636 return 0x801080000078ll + 0x20000ll * ((a) & 0x1f);
4637 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4638 return 0x801080000078ll + 0x20000ll * ((a) & 0x3f);
4639 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4640 return 0x801080000078ll + 0x20000ll * ((a) & 0x1f);
4641 __bdk_csr_fatal("GICRX_PENDBASER", 1, a, 0, 0, 0);
4642 }
4643
4644 #define typedef_BDK_GICRX_PENDBASER(a) bdk_gicrx_pendbaser_t
4645 #define bustype_BDK_GICRX_PENDBASER(a) BDK_CSR_TYPE_NCB
4646 #define basename_BDK_GICRX_PENDBASER(a) "GICRX_PENDBASER"
4647 #define device_bar_BDK_GICRX_PENDBASER(a) 0x4 /* PF_BAR4 */
4648 #define busnum_BDK_GICRX_PENDBASER(a) (a)
4649 #define arguments_BDK_GICRX_PENDBASER(a) (a),-1,-1,-1
4650
4651 /**
4652 * Register (NCB32b) gicr#_pidr0
4653 *
4654 * GIC Redistributor Peripheral Identification Register 0
4655 */
4656 union bdk_gicrx_pidr0
4657 {
4658 uint32_t u;
4659 struct bdk_gicrx_pidr0_s
4660 {
4661 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4662 uint32_t reserved_8_31 : 24;
4663 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GICR. */
4664 #else /* Word 0 - Little Endian */
4665 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GICR. */
4666 uint32_t reserved_8_31 : 24;
4667 #endif /* Word 0 - End */
4668 } s;
4669 /* struct bdk_gicrx_pidr0_s cn; */
4670 };
4671 typedef union bdk_gicrx_pidr0 bdk_gicrx_pidr0_t;
4672
4673 static inline uint64_t BDK_GICRX_PIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR0(unsigned long a)4674 static inline uint64_t BDK_GICRX_PIDR0(unsigned long a)
4675 {
4676 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4677 return 0x80108000ffe0ll + 0x20000ll * ((a) & 0x3);
4678 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4679 return 0x80108000ffe0ll + 0x20000ll * ((a) & 0x1f);
4680 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4681 return 0x80108000ffe0ll + 0x20000ll * ((a) & 0x3f);
4682 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4683 return 0x80108000ffe0ll + 0x20000ll * ((a) & 0x1f);
4684 __bdk_csr_fatal("GICRX_PIDR0", 1, a, 0, 0, 0);
4685 }
4686
4687 #define typedef_BDK_GICRX_PIDR0(a) bdk_gicrx_pidr0_t
4688 #define bustype_BDK_GICRX_PIDR0(a) BDK_CSR_TYPE_NCB32b
4689 #define basename_BDK_GICRX_PIDR0(a) "GICRX_PIDR0"
4690 #define device_bar_BDK_GICRX_PIDR0(a) 0x4 /* PF_BAR4 */
4691 #define busnum_BDK_GICRX_PIDR0(a) (a)
4692 #define arguments_BDK_GICRX_PIDR0(a) (a),-1,-1,-1
4693
4694 /**
4695 * Register (NCB32b) gicr#_pidr1
4696 *
4697 * GIC Redistributor Peripheral Identification Register 1
4698 */
4699 union bdk_gicrx_pidr1
4700 {
4701 uint32_t u;
4702 struct bdk_gicrx_pidr1_s
4703 {
4704 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4705 uint32_t reserved_8_31 : 24;
4706 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
4707 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
4708 #else /* Word 0 - Little Endian */
4709 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
4710 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
4711 uint32_t reserved_8_31 : 24;
4712 #endif /* Word 0 - End */
4713 } s;
4714 /* struct bdk_gicrx_pidr1_s cn; */
4715 };
4716 typedef union bdk_gicrx_pidr1 bdk_gicrx_pidr1_t;
4717
4718 static inline uint64_t BDK_GICRX_PIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR1(unsigned long a)4719 static inline uint64_t BDK_GICRX_PIDR1(unsigned long a)
4720 {
4721 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4722 return 0x80108000ffe4ll + 0x20000ll * ((a) & 0x3);
4723 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4724 return 0x80108000ffe4ll + 0x20000ll * ((a) & 0x1f);
4725 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4726 return 0x80108000ffe4ll + 0x20000ll * ((a) & 0x3f);
4727 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4728 return 0x80108000ffe4ll + 0x20000ll * ((a) & 0x1f);
4729 __bdk_csr_fatal("GICRX_PIDR1", 1, a, 0, 0, 0);
4730 }
4731
4732 #define typedef_BDK_GICRX_PIDR1(a) bdk_gicrx_pidr1_t
4733 #define bustype_BDK_GICRX_PIDR1(a) BDK_CSR_TYPE_NCB32b
4734 #define basename_BDK_GICRX_PIDR1(a) "GICRX_PIDR1"
4735 #define device_bar_BDK_GICRX_PIDR1(a) 0x4 /* PF_BAR4 */
4736 #define busnum_BDK_GICRX_PIDR1(a) (a)
4737 #define arguments_BDK_GICRX_PIDR1(a) (a),-1,-1,-1
4738
4739 /**
4740 * Register (NCB32b) gicr#_pidr2
4741 *
4742 * GIC Redistributor Peripheral Identification Register 2
4743 */
4744 union bdk_gicrx_pidr2
4745 {
4746 uint32_t u;
4747 struct bdk_gicrx_pidr2_s
4748 {
4749 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4750 uint32_t reserved_8_31 : 24;
4751 uint32_t archrev : 4; /**< [ 7: 4](RO) Architectural revision:
4752 0x1 = GICv1.
4753 0x2 = GICV2.
4754 0x3 = GICv3.
4755 0x4 = GICv4.
4756 0x5-0xF = Reserved. */
4757 uint32_t usesjepcode : 1; /**< [ 3: 3](RO) JEDEC assigned. */
4758 uint32_t jepid : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
4759 #else /* Word 0 - Little Endian */
4760 uint32_t jepid : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
4761 uint32_t usesjepcode : 1; /**< [ 3: 3](RO) JEDEC assigned. */
4762 uint32_t archrev : 4; /**< [ 7: 4](RO) Architectural revision:
4763 0x1 = GICv1.
4764 0x2 = GICV2.
4765 0x3 = GICv3.
4766 0x4 = GICv4.
4767 0x5-0xF = Reserved. */
4768 uint32_t reserved_8_31 : 24;
4769 #endif /* Word 0 - End */
4770 } s;
4771 /* struct bdk_gicrx_pidr2_s cn; */
4772 };
4773 typedef union bdk_gicrx_pidr2 bdk_gicrx_pidr2_t;
4774
4775 static inline uint64_t BDK_GICRX_PIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR2(unsigned long a)4776 static inline uint64_t BDK_GICRX_PIDR2(unsigned long a)
4777 {
4778 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4779 return 0x80108000ffe8ll + 0x20000ll * ((a) & 0x3);
4780 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4781 return 0x80108000ffe8ll + 0x20000ll * ((a) & 0x1f);
4782 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4783 return 0x80108000ffe8ll + 0x20000ll * ((a) & 0x3f);
4784 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4785 return 0x80108000ffe8ll + 0x20000ll * ((a) & 0x1f);
4786 __bdk_csr_fatal("GICRX_PIDR2", 1, a, 0, 0, 0);
4787 }
4788
4789 #define typedef_BDK_GICRX_PIDR2(a) bdk_gicrx_pidr2_t
4790 #define bustype_BDK_GICRX_PIDR2(a) BDK_CSR_TYPE_NCB32b
4791 #define basename_BDK_GICRX_PIDR2(a) "GICRX_PIDR2"
4792 #define device_bar_BDK_GICRX_PIDR2(a) 0x4 /* PF_BAR4 */
4793 #define busnum_BDK_GICRX_PIDR2(a) (a)
4794 #define arguments_BDK_GICRX_PIDR2(a) (a),-1,-1,-1
4795
4796 /**
4797 * Register (NCB32b) gicr#_pidr3
4798 *
4799 * GIC Redistributor Peripheral Identification Register 3
4800 */
4801 union bdk_gicrx_pidr3
4802 {
4803 uint32_t u;
4804 struct bdk_gicrx_pidr3_s
4805 {
4806 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4807 uint32_t reserved_8_31 : 24;
4808 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
4809 uint32_t cmod : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
4810 product, major and minor pass numbers. */
4811 #else /* Word 0 - Little Endian */
4812 uint32_t cmod : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
4813 product, major and minor pass numbers. */
4814 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
4815 uint32_t reserved_8_31 : 24;
4816 #endif /* Word 0 - End */
4817 } s;
4818 /* struct bdk_gicrx_pidr3_s cn; */
4819 };
4820 typedef union bdk_gicrx_pidr3 bdk_gicrx_pidr3_t;
4821
4822 static inline uint64_t BDK_GICRX_PIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR3(unsigned long a)4823 static inline uint64_t BDK_GICRX_PIDR3(unsigned long a)
4824 {
4825 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4826 return 0x80108000ffecll + 0x20000ll * ((a) & 0x3);
4827 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4828 return 0x80108000ffecll + 0x20000ll * ((a) & 0x1f);
4829 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4830 return 0x80108000ffecll + 0x20000ll * ((a) & 0x3f);
4831 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4832 return 0x80108000ffecll + 0x20000ll * ((a) & 0x1f);
4833 __bdk_csr_fatal("GICRX_PIDR3", 1, a, 0, 0, 0);
4834 }
4835
4836 #define typedef_BDK_GICRX_PIDR3(a) bdk_gicrx_pidr3_t
4837 #define bustype_BDK_GICRX_PIDR3(a) BDK_CSR_TYPE_NCB32b
4838 #define basename_BDK_GICRX_PIDR3(a) "GICRX_PIDR3"
4839 #define device_bar_BDK_GICRX_PIDR3(a) 0x4 /* PF_BAR4 */
4840 #define busnum_BDK_GICRX_PIDR3(a) (a)
4841 #define arguments_BDK_GICRX_PIDR3(a) (a),-1,-1,-1
4842
4843 /**
4844 * Register (NCB32b) gicr#_pidr4
4845 *
4846 * GIC Redistributor Peripheral Identification Register 4
4847 */
4848 union bdk_gicrx_pidr4
4849 {
4850 uint32_t u;
4851 struct bdk_gicrx_pidr4_s
4852 {
4853 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4854 uint32_t reserved_8_31 : 24;
4855 uint32_t cnt_4k : 4; /**< [ 7: 4](RO) This field is 0x4, indicating a 64 KB software-visible page. */
4856 uint32_t continuation_code : 4; /**< [ 3: 0](RO) 0x3 = Cavium JEP106 continuation code. */
4857 #else /* Word 0 - Little Endian */
4858 uint32_t continuation_code : 4; /**< [ 3: 0](RO) 0x3 = Cavium JEP106 continuation code. */
4859 uint32_t cnt_4k : 4; /**< [ 7: 4](RO) This field is 0x4, indicating a 64 KB software-visible page. */
4860 uint32_t reserved_8_31 : 24;
4861 #endif /* Word 0 - End */
4862 } s;
4863 /* struct bdk_gicrx_pidr4_s cn; */
4864 };
4865 typedef union bdk_gicrx_pidr4 bdk_gicrx_pidr4_t;
4866
4867 static inline uint64_t BDK_GICRX_PIDR4(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR4(unsigned long a)4868 static inline uint64_t BDK_GICRX_PIDR4(unsigned long a)
4869 {
4870 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4871 return 0x80108000ffd0ll + 0x20000ll * ((a) & 0x3);
4872 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4873 return 0x80108000ffd0ll + 0x20000ll * ((a) & 0x1f);
4874 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4875 return 0x80108000ffd0ll + 0x20000ll * ((a) & 0x3f);
4876 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4877 return 0x80108000ffd0ll + 0x20000ll * ((a) & 0x1f);
4878 __bdk_csr_fatal("GICRX_PIDR4", 1, a, 0, 0, 0);
4879 }
4880
4881 #define typedef_BDK_GICRX_PIDR4(a) bdk_gicrx_pidr4_t
4882 #define bustype_BDK_GICRX_PIDR4(a) BDK_CSR_TYPE_NCB32b
4883 #define basename_BDK_GICRX_PIDR4(a) "GICRX_PIDR4"
4884 #define device_bar_BDK_GICRX_PIDR4(a) 0x4 /* PF_BAR4 */
4885 #define busnum_BDK_GICRX_PIDR4(a) (a)
4886 #define arguments_BDK_GICRX_PIDR4(a) (a),-1,-1,-1
4887
4888 /**
4889 * Register (NCB32b) gicr#_pidr5
4890 *
4891 * GIC Redistributor Peripheral Identification Register 5
4892 */
4893 union bdk_gicrx_pidr5
4894 {
4895 uint32_t u;
4896 struct bdk_gicrx_pidr5_s
4897 {
4898 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4899 uint32_t reserved_0_31 : 32;
4900 #else /* Word 0 - Little Endian */
4901 uint32_t reserved_0_31 : 32;
4902 #endif /* Word 0 - End */
4903 } s;
4904 /* struct bdk_gicrx_pidr5_s cn; */
4905 };
4906 typedef union bdk_gicrx_pidr5 bdk_gicrx_pidr5_t;
4907
4908 static inline uint64_t BDK_GICRX_PIDR5(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR5(unsigned long a)4909 static inline uint64_t BDK_GICRX_PIDR5(unsigned long a)
4910 {
4911 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4912 return 0x80108000ffd4ll + 0x20000ll * ((a) & 0x3);
4913 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4914 return 0x80108000ffd4ll + 0x20000ll * ((a) & 0x1f);
4915 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4916 return 0x80108000ffd4ll + 0x20000ll * ((a) & 0x3f);
4917 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4918 return 0x80108000ffd4ll + 0x20000ll * ((a) & 0x1f);
4919 __bdk_csr_fatal("GICRX_PIDR5", 1, a, 0, 0, 0);
4920 }
4921
4922 #define typedef_BDK_GICRX_PIDR5(a) bdk_gicrx_pidr5_t
4923 #define bustype_BDK_GICRX_PIDR5(a) BDK_CSR_TYPE_NCB32b
4924 #define basename_BDK_GICRX_PIDR5(a) "GICRX_PIDR5"
4925 #define device_bar_BDK_GICRX_PIDR5(a) 0x4 /* PF_BAR4 */
4926 #define busnum_BDK_GICRX_PIDR5(a) (a)
4927 #define arguments_BDK_GICRX_PIDR5(a) (a),-1,-1,-1
4928
4929 /**
4930 * Register (NCB32b) gicr#_pidr6
4931 *
4932 * GIC Redistributor Peripheral Identification Register 6
4933 */
4934 union bdk_gicrx_pidr6
4935 {
4936 uint32_t u;
4937 struct bdk_gicrx_pidr6_s
4938 {
4939 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4940 uint32_t reserved_0_31 : 32;
4941 #else /* Word 0 - Little Endian */
4942 uint32_t reserved_0_31 : 32;
4943 #endif /* Word 0 - End */
4944 } s;
4945 /* struct bdk_gicrx_pidr6_s cn; */
4946 };
4947 typedef union bdk_gicrx_pidr6 bdk_gicrx_pidr6_t;
4948
4949 static inline uint64_t BDK_GICRX_PIDR6(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR6(unsigned long a)4950 static inline uint64_t BDK_GICRX_PIDR6(unsigned long a)
4951 {
4952 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4953 return 0x80108000ffd8ll + 0x20000ll * ((a) & 0x3);
4954 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4955 return 0x80108000ffd8ll + 0x20000ll * ((a) & 0x1f);
4956 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4957 return 0x80108000ffd8ll + 0x20000ll * ((a) & 0x3f);
4958 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
4959 return 0x80108000ffd8ll + 0x20000ll * ((a) & 0x1f);
4960 __bdk_csr_fatal("GICRX_PIDR6", 1, a, 0, 0, 0);
4961 }
4962
4963 #define typedef_BDK_GICRX_PIDR6(a) bdk_gicrx_pidr6_t
4964 #define bustype_BDK_GICRX_PIDR6(a) BDK_CSR_TYPE_NCB32b
4965 #define basename_BDK_GICRX_PIDR6(a) "GICRX_PIDR6"
4966 #define device_bar_BDK_GICRX_PIDR6(a) 0x4 /* PF_BAR4 */
4967 #define busnum_BDK_GICRX_PIDR6(a) (a)
4968 #define arguments_BDK_GICRX_PIDR6(a) (a),-1,-1,-1
4969
4970 /**
4971 * Register (NCB32b) gicr#_pidr7
4972 *
4973 * GIC Redistributor Peripheral Identification Register 7
4974 */
4975 union bdk_gicrx_pidr7
4976 {
4977 uint32_t u;
4978 struct bdk_gicrx_pidr7_s
4979 {
4980 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4981 uint32_t reserved_0_31 : 32;
4982 #else /* Word 0 - Little Endian */
4983 uint32_t reserved_0_31 : 32;
4984 #endif /* Word 0 - End */
4985 } s;
4986 /* struct bdk_gicrx_pidr7_s cn; */
4987 };
4988 typedef union bdk_gicrx_pidr7 bdk_gicrx_pidr7_t;
4989
4990 static inline uint64_t BDK_GICRX_PIDR7(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PIDR7(unsigned long a)4991 static inline uint64_t BDK_GICRX_PIDR7(unsigned long a)
4992 {
4993 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
4994 return 0x80108000ffdcll + 0x20000ll * ((a) & 0x3);
4995 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
4996 return 0x80108000ffdcll + 0x20000ll * ((a) & 0x1f);
4997 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
4998 return 0x80108000ffdcll + 0x20000ll * ((a) & 0x3f);
4999 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5000 return 0x80108000ffdcll + 0x20000ll * ((a) & 0x1f);
5001 __bdk_csr_fatal("GICRX_PIDR7", 1, a, 0, 0, 0);
5002 }
5003
5004 #define typedef_BDK_GICRX_PIDR7(a) bdk_gicrx_pidr7_t
5005 #define bustype_BDK_GICRX_PIDR7(a) BDK_CSR_TYPE_NCB32b
5006 #define basename_BDK_GICRX_PIDR7(a) "GICRX_PIDR7"
5007 #define device_bar_BDK_GICRX_PIDR7(a) 0x4 /* PF_BAR4 */
5008 #define busnum_BDK_GICRX_PIDR7(a) (a)
5009 #define arguments_BDK_GICRX_PIDR7(a) (a),-1,-1,-1
5010
5011 /**
5012 * Register (NCB) gicr#_propbaser
5013 *
5014 * GIC Redistributor LPI Configuration Table Address Register
5015 */
5016 union bdk_gicrx_propbaser
5017 {
5018 uint64_t u;
5019 struct bdk_gicrx_propbaser_s
5020 {
5021 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5022 uint64_t reserved_59_63 : 5;
5023 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
5024 uint64_t reserved_52_55 : 4;
5025 uint64_t pa : 40; /**< [ 51: 12](R/W) Physical address bits \<46:12\> for the LPI configuration table. */
5026 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
5027 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
5028 uint64_t reserved_5_6 : 2;
5029 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5030 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5031 GICD_TYPER[IDBITS]. */
5032 #else /* Word 0 - Little Endian */
5033 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5034 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5035 GICD_TYPER[IDBITS]. */
5036 uint64_t reserved_5_6 : 2;
5037 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
5038 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
5039 uint64_t pa : 40; /**< [ 51: 12](R/W) Physical address bits \<46:12\> for the LPI configuration table. */
5040 uint64_t reserved_52_55 : 4;
5041 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
5042 uint64_t reserved_59_63 : 5;
5043 #endif /* Word 0 - End */
5044 } s;
5045 struct bdk_gicrx_propbaser_cn88xxp1
5046 {
5047 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5048 uint64_t reserved_48_63 : 16;
5049 uint64_t pa : 36; /**< [ 47: 12](R/W) Physical address bits \<46:12\> for the LPI configuration table. */
5050 uint64_t reserved_5_11 : 7;
5051 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5052 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5053 GICD_TYPER[IDBITS]. */
5054 #else /* Word 0 - Little Endian */
5055 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5056 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5057 GICD_TYPER[IDBITS]. */
5058 uint64_t reserved_5_11 : 7;
5059 uint64_t pa : 36; /**< [ 47: 12](R/W) Physical address bits \<46:12\> for the LPI configuration table. */
5060 uint64_t reserved_48_63 : 16;
5061 #endif /* Word 0 - End */
5062 } cn88xxp1;
5063 struct bdk_gicrx_propbaser_cn9
5064 {
5065 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5066 uint64_t reserved_59_63 : 5;
5067 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
5068 uint64_t reserved_52_55 : 4;
5069 uint64_t pa : 40; /**< [ 51: 12](R/W) Physical address bits \<51:12\> for the LPI configuration table.
5070 Software must set bits \<51:46\> and \<43\> to zero. */
5071 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
5072 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
5073 uint64_t reserved_5_6 : 2;
5074 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5075 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5076 GICD_TYPER[IDBITS]. */
5077 #else /* Word 0 - Little Endian */
5078 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5079 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5080 GICD_TYPER[IDBITS]. */
5081 uint64_t reserved_5_6 : 2;
5082 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
5083 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
5084 uint64_t pa : 40; /**< [ 51: 12](R/W) Physical address bits \<51:12\> for the LPI configuration table.
5085 Software must set bits \<51:46\> and \<43\> to zero. */
5086 uint64_t reserved_52_55 : 4;
5087 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
5088 uint64_t reserved_59_63 : 5;
5089 #endif /* Word 0 - End */
5090 } cn9;
5091 struct bdk_gicrx_propbaser_cn81xx
5092 {
5093 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5094 uint64_t reserved_59_63 : 5;
5095 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
5096 uint64_t reserved_48_55 : 8;
5097 uint64_t pa : 36; /**< [ 47: 12](R/W) Physical address bits \<46:12\> for the LPI configuration table. */
5098 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
5099 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
5100 uint64_t reserved_5_6 : 2;
5101 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5102 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5103 GICD_TYPER[IDBITS]. */
5104 #else /* Word 0 - Little Endian */
5105 uint64_t num_bits : 5; /**< [ 4: 0](R/W) The number of bits of LPI ID supported, minus one. If this value exceeds the value of
5106 GICD_TYPER[IDBITS], then the number of bits must be treated as the value defined by
5107 GICD_TYPER[IDBITS]. */
5108 uint64_t reserved_5_6 : 2;
5109 uint64_t cacheability : 3; /**< [ 9: 7](R/W) Cacheability attributes. Ignored in CNXXXX. */
5110 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attributes. Ignored in CNXXXX. */
5111 uint64_t pa : 36; /**< [ 47: 12](R/W) Physical address bits \<46:12\> for the LPI configuration table. */
5112 uint64_t reserved_48_55 : 8;
5113 uint64_t outer_cacheability : 3; /**< [ 58: 56](R/W) Outer cacheability attributes. Ignored in CNXXXX. */
5114 uint64_t reserved_59_63 : 5;
5115 #endif /* Word 0 - End */
5116 } cn81xx;
5117 /* struct bdk_gicrx_propbaser_cn81xx cn83xx; */
5118 /* struct bdk_gicrx_propbaser_cn81xx cn88xxp2; */
5119 };
5120 typedef union bdk_gicrx_propbaser bdk_gicrx_propbaser_t;
5121
5122 static inline uint64_t BDK_GICRX_PROPBASER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_PROPBASER(unsigned long a)5123 static inline uint64_t BDK_GICRX_PROPBASER(unsigned long a)
5124 {
5125 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5126 return 0x801080000070ll + 0x20000ll * ((a) & 0x3);
5127 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5128 return 0x801080000070ll + 0x20000ll * ((a) & 0x1f);
5129 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5130 return 0x801080000070ll + 0x20000ll * ((a) & 0x3f);
5131 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5132 return 0x801080000070ll + 0x20000ll * ((a) & 0x1f);
5133 __bdk_csr_fatal("GICRX_PROPBASER", 1, a, 0, 0, 0);
5134 }
5135
5136 #define typedef_BDK_GICRX_PROPBASER(a) bdk_gicrx_propbaser_t
5137 #define bustype_BDK_GICRX_PROPBASER(a) BDK_CSR_TYPE_NCB
5138 #define basename_BDK_GICRX_PROPBASER(a) "GICRX_PROPBASER"
5139 #define device_bar_BDK_GICRX_PROPBASER(a) 0x4 /* PF_BAR4 */
5140 #define busnum_BDK_GICRX_PROPBASER(a) (a)
5141 #define arguments_BDK_GICRX_PROPBASER(a) (a),-1,-1,-1
5142
5143 /**
5144 * Register (NCB32b) gicr#_sctlr
5145 *
5146 * GIC Redistributor (Secure) Control Register
5147 * This register controls the behavior of the nonsecure redistributor.
5148 */
5149 union bdk_gicrx_sctlr
5150 {
5151 uint32_t u;
5152 struct bdk_gicrx_sctlr_s
5153 {
5154 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5155 uint32_t uwp : 1; /**< [ 31: 31](RO) Upstream write pending. Common to both security states. Read-only.
5156 0 = The effects of all upstream writes have been communicated to the parent
5157 redistributor, including any generate SGI packets.
5158 1 = The effects of all upstream writes have not been communicated to the parent
5159 redistributor, including any generate SGI packets. */
5160 uint32_t reserved_4_30 : 27;
5161 uint32_t rwp : 1; /**< [ 3: 3](RO) Register write pending. This bit indicates whether a register write for the current
5162 security state (banked) is in progress or not.
5163 0 = The effect of all register writes are visible to all descendants of the
5164 redistributor, including processors.
5165 1 = The effects of all register writes are not visible to all descendants of the
5166 redistributor.
5167
5168 Note: this field tracks completion of writes to GICR()_ICENABLER0 that clear
5169 the enable of one or more interrupts. */
5170 uint32_t reserved_1_2 : 2;
5171 uint32_t enable_lpis : 1; /**< [ 0: 0](R/W) Enable LPIs. Common to both security states. When this bit is clear,
5172 writes to generate physical LPIs to GICR()_SETLPIR will be ignored.
5173 When a write changes this bit from zero to one, this bit becomes RAO/WI and the
5174 redistributor must load the pending table from memory to check for any pending interrupts. */
5175 #else /* Word 0 - Little Endian */
5176 uint32_t enable_lpis : 1; /**< [ 0: 0](R/W) Enable LPIs. Common to both security states. When this bit is clear,
5177 writes to generate physical LPIs to GICR()_SETLPIR will be ignored.
5178 When a write changes this bit from zero to one, this bit becomes RAO/WI and the
5179 redistributor must load the pending table from memory to check for any pending interrupts. */
5180 uint32_t reserved_1_2 : 2;
5181 uint32_t rwp : 1; /**< [ 3: 3](RO) Register write pending. This bit indicates whether a register write for the current
5182 security state (banked) is in progress or not.
5183 0 = The effect of all register writes are visible to all descendants of the
5184 redistributor, including processors.
5185 1 = The effects of all register writes are not visible to all descendants of the
5186 redistributor.
5187
5188 Note: this field tracks completion of writes to GICR()_ICENABLER0 that clear
5189 the enable of one or more interrupts. */
5190 uint32_t reserved_4_30 : 27;
5191 uint32_t uwp : 1; /**< [ 31: 31](RO) Upstream write pending. Common to both security states. Read-only.
5192 0 = The effects of all upstream writes have been communicated to the parent
5193 redistributor, including any generate SGI packets.
5194 1 = The effects of all upstream writes have not been communicated to the parent
5195 redistributor, including any generate SGI packets. */
5196 #endif /* Word 0 - End */
5197 } s;
5198 /* struct bdk_gicrx_sctlr_s cn; */
5199 };
5200 typedef union bdk_gicrx_sctlr bdk_gicrx_sctlr_t;
5201
5202 static inline uint64_t BDK_GICRX_SCTLR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_SCTLR(unsigned long a)5203 static inline uint64_t BDK_GICRX_SCTLR(unsigned long a)
5204 {
5205 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5206 return 0x801080000000ll + 0x20000ll * ((a) & 0x3);
5207 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5208 return 0x801080000000ll + 0x20000ll * ((a) & 0x1f);
5209 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5210 return 0x801080000000ll + 0x20000ll * ((a) & 0x3f);
5211 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5212 return 0x801080000000ll + 0x20000ll * ((a) & 0x1f);
5213 __bdk_csr_fatal("GICRX_SCTLR", 1, a, 0, 0, 0);
5214 }
5215
5216 #define typedef_BDK_GICRX_SCTLR(a) bdk_gicrx_sctlr_t
5217 #define bustype_BDK_GICRX_SCTLR(a) BDK_CSR_TYPE_NCB32b
5218 #define basename_BDK_GICRX_SCTLR(a) "GICRX_SCTLR"
5219 #define device_bar_BDK_GICRX_SCTLR(a) 0x4 /* PF_BAR4 */
5220 #define busnum_BDK_GICRX_SCTLR(a) (a)
5221 #define arguments_BDK_GICRX_SCTLR(a) (a),-1,-1,-1
5222
5223 /**
5224 * Register (NCB32b) gicr#_seir
5225 *
5226 * GIC Redistributor Generate SEI Register
5227 */
5228 union bdk_gicrx_seir
5229 {
5230 uint32_t u;
5231 struct bdk_gicrx_seir_s
5232 {
5233 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5234 uint32_t reserved_16_31 : 16;
5235 uint32_t syndrome : 16; /**< [ 15: 0](WO) Syndrome value for the SEI to be generated. If another write to this register occurs
5236 before the previous has been forwarded to its recipients, the new value is ORed with the
5237 existing value. [SYNDROME] is sticky and indicates that at least one error of a
5238 class has occurred. */
5239 #else /* Word 0 - Little Endian */
5240 uint32_t syndrome : 16; /**< [ 15: 0](WO) Syndrome value for the SEI to be generated. If another write to this register occurs
5241 before the previous has been forwarded to its recipients, the new value is ORed with the
5242 existing value. [SYNDROME] is sticky and indicates that at least one error of a
5243 class has occurred. */
5244 uint32_t reserved_16_31 : 16;
5245 #endif /* Word 0 - End */
5246 } s;
5247 /* struct bdk_gicrx_seir_s cn; */
5248 };
5249 typedef union bdk_gicrx_seir bdk_gicrx_seir_t;
5250
5251 static inline uint64_t BDK_GICRX_SEIR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_SEIR(unsigned long a)5252 static inline uint64_t BDK_GICRX_SEIR(unsigned long a)
5253 {
5254 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5255 return 0x801080000068ll + 0x20000ll * ((a) & 0x3);
5256 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5257 return 0x801080000068ll + 0x20000ll * ((a) & 0x1f);
5258 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5259 return 0x801080000068ll + 0x20000ll * ((a) & 0x3f);
5260 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5261 return 0x801080000068ll + 0x20000ll * ((a) & 0x1f);
5262 __bdk_csr_fatal("GICRX_SEIR", 1, a, 0, 0, 0);
5263 }
5264
5265 #define typedef_BDK_GICRX_SEIR(a) bdk_gicrx_seir_t
5266 #define bustype_BDK_GICRX_SEIR(a) BDK_CSR_TYPE_NCB32b
5267 #define basename_BDK_GICRX_SEIR(a) "GICRX_SEIR"
5268 #define device_bar_BDK_GICRX_SEIR(a) 0x4 /* PF_BAR4 */
5269 #define busnum_BDK_GICRX_SEIR(a) (a)
5270 #define arguments_BDK_GICRX_SEIR(a) (a),-1,-1,-1
5271
5272 /**
5273 * Register (NCB32b) gicr#_setdel3tr_el1s
5274 *
5275 * GIC Redistributor Set Non-Maskable Interrupt Secure Registers
5276 */
5277 union bdk_gicrx_setdel3tr_el1s
5278 {
5279 uint32_t u;
5280 struct bdk_gicrx_setdel3tr_el1s_s
5281 {
5282 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5283 uint32_t vec : 32; /**< [ 31: 0](SWO) These write-only secure registers are used to generate DEL3T interrupts to the APs.
5284 The value written into these registers is not used. There is no interrupt ID for DEL3Ts.
5285 Whenever a register in this set is written, the DEL3T signal of the AP being
5286 managed by that register is asserted.
5287
5288 Each register in this set is RAZ/WI for nonsecure accesses. */
5289 #else /* Word 0 - Little Endian */
5290 uint32_t vec : 32; /**< [ 31: 0](SWO) These write-only secure registers are used to generate DEL3T interrupts to the APs.
5291 The value written into these registers is not used. There is no interrupt ID for DEL3Ts.
5292 Whenever a register in this set is written, the DEL3T signal of the AP being
5293 managed by that register is asserted.
5294
5295 Each register in this set is RAZ/WI for nonsecure accesses. */
5296 #endif /* Word 0 - End */
5297 } s;
5298 /* struct bdk_gicrx_setdel3tr_el1s_s cn; */
5299 };
5300 typedef union bdk_gicrx_setdel3tr_el1s bdk_gicrx_setdel3tr_el1s_t;
5301
5302 static inline uint64_t BDK_GICRX_SETDEL3TR_EL1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_SETDEL3TR_EL1S(unsigned long a)5303 static inline uint64_t BDK_GICRX_SETDEL3TR_EL1S(unsigned long a)
5304 {
5305 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5306 return 0x80108000c000ll + 0x20000ll * ((a) & 0x3);
5307 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5308 return 0x80108000c000ll + 0x20000ll * ((a) & 0x1f);
5309 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5310 return 0x80108000c000ll + 0x20000ll * ((a) & 0x3f);
5311 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5312 return 0x80108000c000ll + 0x20000ll * ((a) & 0x1f);
5313 __bdk_csr_fatal("GICRX_SETDEL3TR_EL1S", 1, a, 0, 0, 0);
5314 }
5315
5316 #define typedef_BDK_GICRX_SETDEL3TR_EL1S(a) bdk_gicrx_setdel3tr_el1s_t
5317 #define bustype_BDK_GICRX_SETDEL3TR_EL1S(a) BDK_CSR_TYPE_NCB32b
5318 #define basename_BDK_GICRX_SETDEL3TR_EL1S(a) "GICRX_SETDEL3TR_EL1S"
5319 #define device_bar_BDK_GICRX_SETDEL3TR_EL1S(a) 0x4 /* PF_BAR4 */
5320 #define busnum_BDK_GICRX_SETDEL3TR_EL1S(a) (a)
5321 #define arguments_BDK_GICRX_SETDEL3TR_EL1S(a) (a),-1,-1,-1
5322
5323 /**
5324 * Register (NCB) gicr#_setlpir
5325 *
5326 * GIC Redistributor Set LPI Register
5327 */
5328 union bdk_gicrx_setlpir
5329 {
5330 uint64_t u;
5331 struct bdk_gicrx_setlpir_s
5332 {
5333 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5334 uint64_t reserved_32_63 : 32;
5335 uint64_t pid : 32; /**< [ 31: 0](WO) Physical ID of the LPI to be generated. If the LPI is already pending, the write has no
5336 effect.
5337 If the LPI with the physical ID is not implemented, the write has no effect.
5338 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
5339 #else /* Word 0 - Little Endian */
5340 uint64_t pid : 32; /**< [ 31: 0](WO) Physical ID of the LPI to be generated. If the LPI is already pending, the write has no
5341 effect.
5342 If the LPI with the physical ID is not implemented, the write has no effect.
5343 If GICR()_(S)CTLR[ENABLE_LPIS] is zero, the write has no effect. */
5344 uint64_t reserved_32_63 : 32;
5345 #endif /* Word 0 - End */
5346 } s;
5347 /* struct bdk_gicrx_setlpir_s cn; */
5348 };
5349 typedef union bdk_gicrx_setlpir bdk_gicrx_setlpir_t;
5350
5351 static inline uint64_t BDK_GICRX_SETLPIR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_SETLPIR(unsigned long a)5352 static inline uint64_t BDK_GICRX_SETLPIR(unsigned long a)
5353 {
5354 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5355 return 0x801080000040ll + 0x20000ll * ((a) & 0x3);
5356 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5357 return 0x801080000040ll + 0x20000ll * ((a) & 0x1f);
5358 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5359 return 0x801080000040ll + 0x20000ll * ((a) & 0x3f);
5360 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5361 return 0x801080000040ll + 0x20000ll * ((a) & 0x1f);
5362 __bdk_csr_fatal("GICRX_SETLPIR", 1, a, 0, 0, 0);
5363 }
5364
5365 #define typedef_BDK_GICRX_SETLPIR(a) bdk_gicrx_setlpir_t
5366 #define bustype_BDK_GICRX_SETLPIR(a) BDK_CSR_TYPE_NCB
5367 #define basename_BDK_GICRX_SETLPIR(a) "GICRX_SETLPIR"
5368 #define device_bar_BDK_GICRX_SETLPIR(a) 0x4 /* PF_BAR4 */
5369 #define busnum_BDK_GICRX_SETLPIR(a) (a)
5370 #define arguments_BDK_GICRX_SETLPIR(a) (a),-1,-1,-1
5371
5372 /**
5373 * Register (NCB32b) gicr#_sstatusr
5374 *
5375 * GIC Redistributor (Secure) Status Register
5376 */
5377 union bdk_gicrx_sstatusr
5378 {
5379 uint32_t u;
5380 struct bdk_gicrx_sstatusr_s
5381 {
5382 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5383 uint32_t reserved_4_31 : 28;
5384 uint32_t wrod : 1; /**< [ 3: 3](R/W1C/H) This bit is set if a write to a read-only location is detected. Software must write a one
5385 to this bit to clear it. */
5386 uint32_t rwod : 1; /**< [ 2: 2](R/W1C/H) This bit is set if a read to a write-only location is detected. Software must write a one
5387 to this bit to clear it. */
5388 uint32_t wrd : 1; /**< [ 1: 1](R/W1C/H) This bit is set if a write to a reserved location is detected. Software must write a one
5389 to this bit to clear it. */
5390 uint32_t rrd : 1; /**< [ 0: 0](R/W1C/H) This bit is set if a read to a reserved location is detected. Software must write a one to
5391 this bit to clear it. */
5392 #else /* Word 0 - Little Endian */
5393 uint32_t rrd : 1; /**< [ 0: 0](R/W1C/H) This bit is set if a read to a reserved location is detected. Software must write a one to
5394 this bit to clear it. */
5395 uint32_t wrd : 1; /**< [ 1: 1](R/W1C/H) This bit is set if a write to a reserved location is detected. Software must write a one
5396 to this bit to clear it. */
5397 uint32_t rwod : 1; /**< [ 2: 2](R/W1C/H) This bit is set if a read to a write-only location is detected. Software must write a one
5398 to this bit to clear it. */
5399 uint32_t wrod : 1; /**< [ 3: 3](R/W1C/H) This bit is set if a write to a read-only location is detected. Software must write a one
5400 to this bit to clear it. */
5401 uint32_t reserved_4_31 : 28;
5402 #endif /* Word 0 - End */
5403 } s;
5404 /* struct bdk_gicrx_sstatusr_s cn; */
5405 };
5406 typedef union bdk_gicrx_sstatusr bdk_gicrx_sstatusr_t;
5407
5408 static inline uint64_t BDK_GICRX_SSTATUSR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_SSTATUSR(unsigned long a)5409 static inline uint64_t BDK_GICRX_SSTATUSR(unsigned long a)
5410 {
5411 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5412 return 0x801080000010ll + 0x20000ll * ((a) & 0x3);
5413 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5414 return 0x801080000010ll + 0x20000ll * ((a) & 0x1f);
5415 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5416 return 0x801080000010ll + 0x20000ll * ((a) & 0x3f);
5417 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5418 return 0x801080000010ll + 0x20000ll * ((a) & 0x1f);
5419 __bdk_csr_fatal("GICRX_SSTATUSR", 1, a, 0, 0, 0);
5420 }
5421
5422 #define typedef_BDK_GICRX_SSTATUSR(a) bdk_gicrx_sstatusr_t
5423 #define bustype_BDK_GICRX_SSTATUSR(a) BDK_CSR_TYPE_NCB32b
5424 #define basename_BDK_GICRX_SSTATUSR(a) "GICRX_SSTATUSR"
5425 #define device_bar_BDK_GICRX_SSTATUSR(a) 0x4 /* PF_BAR4 */
5426 #define busnum_BDK_GICRX_SSTATUSR(a) (a)
5427 #define arguments_BDK_GICRX_SSTATUSR(a) (a),-1,-1,-1
5428
5429 /**
5430 * Register (NCB32b) gicr#_syncr
5431 *
5432 * GIC Redistributor Sync Register
5433 */
5434 union bdk_gicrx_syncr
5435 {
5436 uint32_t u;
5437 struct bdk_gicrx_syncr_s
5438 {
5439 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5440 uint32_t reserved_1_31 : 31;
5441 uint32_t busy : 1; /**< [ 0: 0](RO) Reserved. When this register is read, it will only return read-data with [BUSY] as zero when
5442 none of the following operations are in progress:
5443 * Any writes to GICR()_CLRLPIR within the redistributor.
5444 * Any writes to GICR()_MOVLPIR within the redistributor.
5445 * Any writes to GICR()_MOVALLR within the redistributor.
5446 * Any writes to GICR()_INVLPIR within the redistributor.
5447 * Any writes to GICR()_INVALLR within the redistributor.
5448 * Any writes to another redistributor performed as a result of a previous write to
5449 GICR()_MOVLPIR or GICR()_MOVALLR have completed and arrived at the target redistributor.
5450 Including operations initiated by writing to GICR()_PENDBASER or GICR()_PROPBASER. */
5451 #else /* Word 0 - Little Endian */
5452 uint32_t busy : 1; /**< [ 0: 0](RO) Reserved. When this register is read, it will only return read-data with [BUSY] as zero when
5453 none of the following operations are in progress:
5454 * Any writes to GICR()_CLRLPIR within the redistributor.
5455 * Any writes to GICR()_MOVLPIR within the redistributor.
5456 * Any writes to GICR()_MOVALLR within the redistributor.
5457 * Any writes to GICR()_INVLPIR within the redistributor.
5458 * Any writes to GICR()_INVALLR within the redistributor.
5459 * Any writes to another redistributor performed as a result of a previous write to
5460 GICR()_MOVLPIR or GICR()_MOVALLR have completed and arrived at the target redistributor.
5461 Including operations initiated by writing to GICR()_PENDBASER or GICR()_PROPBASER. */
5462 uint32_t reserved_1_31 : 31;
5463 #endif /* Word 0 - End */
5464 } s;
5465 /* struct bdk_gicrx_syncr_s cn; */
5466 };
5467 typedef union bdk_gicrx_syncr bdk_gicrx_syncr_t;
5468
5469 static inline uint64_t BDK_GICRX_SYNCR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_SYNCR(unsigned long a)5470 static inline uint64_t BDK_GICRX_SYNCR(unsigned long a)
5471 {
5472 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5473 return 0x8010800000c0ll + 0x20000ll * ((a) & 0x3);
5474 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5475 return 0x8010800000c0ll + 0x20000ll * ((a) & 0x1f);
5476 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5477 return 0x8010800000c0ll + 0x20000ll * ((a) & 0x3f);
5478 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5479 return 0x8010800000c0ll + 0x20000ll * ((a) & 0x1f);
5480 __bdk_csr_fatal("GICRX_SYNCR", 1, a, 0, 0, 0);
5481 }
5482
5483 #define typedef_BDK_GICRX_SYNCR(a) bdk_gicrx_syncr_t
5484 #define bustype_BDK_GICRX_SYNCR(a) BDK_CSR_TYPE_NCB32b
5485 #define basename_BDK_GICRX_SYNCR(a) "GICRX_SYNCR"
5486 #define device_bar_BDK_GICRX_SYNCR(a) 0x4 /* PF_BAR4 */
5487 #define busnum_BDK_GICRX_SYNCR(a) (a)
5488 #define arguments_BDK_GICRX_SYNCR(a) (a),-1,-1,-1
5489
5490 /**
5491 * Register (NCB) gicr#_typer
5492 *
5493 * GIC Redistributor Type Register
5494 * This 64-bit read-only register is used to discover the properties of the redistributor and is
5495 * always accessible regardless of the ARE setting for a security state.
5496 */
5497 union bdk_gicrx_typer
5498 {
5499 uint64_t u;
5500 struct bdk_gicrx_typer_s
5501 {
5502 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5503 uint64_t a3 : 8; /**< [ 63: 56](RO) The affinity level 3 value for the redistributor. */
5504 uint64_t a2 : 8; /**< [ 55: 48](RO/H) The affinity level 2 value for the redistributor. */
5505 uint64_t a1 : 8; /**< [ 47: 40](RO/H) The affinity level 1 value for the redistributor. */
5506 uint64_t a0 : 8; /**< [ 39: 32](RO/H) The affinity level 0 value for the redistributor. */
5507 uint64_t reserved_26_31 : 6;
5508 uint64_t commonlpiaff : 2; /**< [ 25: 24](RAZ) The affinity level at which re-distributors share a LPI configuration table.
5509 0x0 = All re-distributors must share a config table.
5510 0x1 = All re-distributors with the same Aff3 value must share a LPI configuration table.
5511 0x2 = All re-distributors with the same Aff3.Aff2 value must share a LPI configuration.
5512 table.
5513 0x3 = All re-distributors with the same Aff3.Aff2.Aff1 value must share an LPI
5514 configuration table. */
5515 uint64_t pn : 16; /**< [ 23: 8](RO/H) The processor number, a unique identifier for the processor understood by the ITS. Should
5516 be the logical processor number supported by the redistributor, which is the redistributor
5517 ID, ie. the variable a. */
5518 uint64_t reserved_6_7 : 2;
5519 uint64_t dpgs : 1; /**< [ 5: 5](RAZ) GICR()_(S)CTLR[DPG*] bits are NOT supported. */
5520 uint64_t last : 1; /**< [ 4: 4](RO/H) Last. This bit is only set for the last redistributor in a set of contiguous redistributor
5521 register pages. Needs to be determined from fuse signals or SKU. */
5522 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed implementation:
5523 0 = Monolithic implementation.
5524 1 = Distributed implementation registers supported. */
5525 uint64_t reserved_1_2 : 2;
5526 uint64_t plpis : 1; /**< [ 0: 0](RO) Physical LPIs supported:
5527 0 = Physical LPIs not supported.
5528 1 = Physical LPIs supported. */
5529 #else /* Word 0 - Little Endian */
5530 uint64_t plpis : 1; /**< [ 0: 0](RO) Physical LPIs supported:
5531 0 = Physical LPIs not supported.
5532 1 = Physical LPIs supported. */
5533 uint64_t reserved_1_2 : 2;
5534 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed implementation:
5535 0 = Monolithic implementation.
5536 1 = Distributed implementation registers supported. */
5537 uint64_t last : 1; /**< [ 4: 4](RO/H) Last. This bit is only set for the last redistributor in a set of contiguous redistributor
5538 register pages. Needs to be determined from fuse signals or SKU. */
5539 uint64_t dpgs : 1; /**< [ 5: 5](RAZ) GICR()_(S)CTLR[DPG*] bits are NOT supported. */
5540 uint64_t reserved_6_7 : 2;
5541 uint64_t pn : 16; /**< [ 23: 8](RO/H) The processor number, a unique identifier for the processor understood by the ITS. Should
5542 be the logical processor number supported by the redistributor, which is the redistributor
5543 ID, ie. the variable a. */
5544 uint64_t commonlpiaff : 2; /**< [ 25: 24](RAZ) The affinity level at which re-distributors share a LPI configuration table.
5545 0x0 = All re-distributors must share a config table.
5546 0x1 = All re-distributors with the same Aff3 value must share a LPI configuration table.
5547 0x2 = All re-distributors with the same Aff3.Aff2 value must share a LPI configuration.
5548 table.
5549 0x3 = All re-distributors with the same Aff3.Aff2.Aff1 value must share an LPI
5550 configuration table. */
5551 uint64_t reserved_26_31 : 6;
5552 uint64_t a0 : 8; /**< [ 39: 32](RO/H) The affinity level 0 value for the redistributor. */
5553 uint64_t a1 : 8; /**< [ 47: 40](RO/H) The affinity level 1 value for the redistributor. */
5554 uint64_t a2 : 8; /**< [ 55: 48](RO/H) The affinity level 2 value for the redistributor. */
5555 uint64_t a3 : 8; /**< [ 63: 56](RO) The affinity level 3 value for the redistributor. */
5556 #endif /* Word 0 - End */
5557 } s;
5558 struct bdk_gicrx_typer_cn8
5559 {
5560 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5561 uint64_t a3 : 8; /**< [ 63: 56](RO) The affinity level 3 value for the redistributor. */
5562 uint64_t a2 : 8; /**< [ 55: 48](RO/H) The affinity level 2 value for the redistributor. */
5563 uint64_t a1 : 8; /**< [ 47: 40](RO/H) The affinity level 1 value for the redistributor. */
5564 uint64_t a0 : 8; /**< [ 39: 32](RO/H) The affinity level 0 value for the redistributor. */
5565 uint64_t reserved_24_31 : 8;
5566 uint64_t pn : 16; /**< [ 23: 8](RO/H) The processor number, a unique identifier for the processor understood by the ITS. Should
5567 be the logical processor number supported by the redistributor, which is the redistributor
5568 ID, ie. the variable a. */
5569 uint64_t reserved_6_7 : 2;
5570 uint64_t dpgs : 1; /**< [ 5: 5](RAZ) GICR()_(S)CTLR[DPG*] bits are NOT supported. */
5571 uint64_t last : 1; /**< [ 4: 4](RO/H) Last. This bit is only set for the last redistributor in a set of contiguous redistributor
5572 register pages. Needs to be determined from fuse signals or SKU. */
5573 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed implementation:
5574 0 = Monolithic implementation.
5575 1 = Distributed implementation registers supported. */
5576 uint64_t reserved_1_2 : 2;
5577 uint64_t plpis : 1; /**< [ 0: 0](RO) Physical LPIs supported:
5578 0 = Physical LPIs not supported.
5579 1 = Physical LPIs supported. */
5580 #else /* Word 0 - Little Endian */
5581 uint64_t plpis : 1; /**< [ 0: 0](RO) Physical LPIs supported:
5582 0 = Physical LPIs not supported.
5583 1 = Physical LPIs supported. */
5584 uint64_t reserved_1_2 : 2;
5585 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed implementation:
5586 0 = Monolithic implementation.
5587 1 = Distributed implementation registers supported. */
5588 uint64_t last : 1; /**< [ 4: 4](RO/H) Last. This bit is only set for the last redistributor in a set of contiguous redistributor
5589 register pages. Needs to be determined from fuse signals or SKU. */
5590 uint64_t dpgs : 1; /**< [ 5: 5](RAZ) GICR()_(S)CTLR[DPG*] bits are NOT supported. */
5591 uint64_t reserved_6_7 : 2;
5592 uint64_t pn : 16; /**< [ 23: 8](RO/H) The processor number, a unique identifier for the processor understood by the ITS. Should
5593 be the logical processor number supported by the redistributor, which is the redistributor
5594 ID, ie. the variable a. */
5595 uint64_t reserved_24_31 : 8;
5596 uint64_t a0 : 8; /**< [ 39: 32](RO/H) The affinity level 0 value for the redistributor. */
5597 uint64_t a1 : 8; /**< [ 47: 40](RO/H) The affinity level 1 value for the redistributor. */
5598 uint64_t a2 : 8; /**< [ 55: 48](RO/H) The affinity level 2 value for the redistributor. */
5599 uint64_t a3 : 8; /**< [ 63: 56](RO) The affinity level 3 value for the redistributor. */
5600 #endif /* Word 0 - End */
5601 } cn8;
5602 /* struct bdk_gicrx_typer_s cn9; */
5603 };
5604 typedef union bdk_gicrx_typer bdk_gicrx_typer_t;
5605
5606 static inline uint64_t BDK_GICRX_TYPER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_TYPER(unsigned long a)5607 static inline uint64_t BDK_GICRX_TYPER(unsigned long a)
5608 {
5609 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5610 return 0x801080000008ll + 0x20000ll * ((a) & 0x3);
5611 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5612 return 0x801080000008ll + 0x20000ll * ((a) & 0x1f);
5613 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5614 return 0x801080000008ll + 0x20000ll * ((a) & 0x3f);
5615 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5616 return 0x801080000008ll + 0x20000ll * ((a) & 0x1f);
5617 __bdk_csr_fatal("GICRX_TYPER", 1, a, 0, 0, 0);
5618 }
5619
5620 #define typedef_BDK_GICRX_TYPER(a) bdk_gicrx_typer_t
5621 #define bustype_BDK_GICRX_TYPER(a) BDK_CSR_TYPE_NCB
5622 #define basename_BDK_GICRX_TYPER(a) "GICRX_TYPER"
5623 #define device_bar_BDK_GICRX_TYPER(a) 0x4 /* PF_BAR4 */
5624 #define busnum_BDK_GICRX_TYPER(a) (a)
5625 #define arguments_BDK_GICRX_TYPER(a) (a),-1,-1,-1
5626
5627 /**
5628 * Register (NCB32b) gicr#_waker
5629 *
5630 * GIC Redistributor Wake Request Control Secure Register
5631 */
5632 union bdk_gicrx_waker
5633 {
5634 uint32_t u;
5635 struct bdk_gicrx_waker_s
5636 {
5637 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5638 uint32_t quiescent : 1; /**< [ 31: 31](SRO) Indicates that redistributor is quiescent and can be powered off. */
5639 uint32_t reserved_3_30 : 28;
5640 uint32_t ca : 1; /**< [ 2: 2](SRO) Children asleep.
5641 When [PS] is one, the redistributor treats the interrupt group enables as zero
5642 until a subsequent update to the enables is received. */
5643 uint32_t ps : 1; /**< [ 1: 1](SR/W) Processor sleep.
5644 0 = The redistributor never asserts WakeRequest.
5645 1 = The redistributor must assert WakeRequest and hold interrupts as pending if an enable
5646 bit is zero for an interrupt group and there is a pending interrupt for that group. */
5647 uint32_t sleep : 1; /**< [ 0: 0](SR/W) Sleep.
5648 0 = The parent never asserts WakeRequest.
5649 1 = The parent must assert WakeRequest and hold interrupts as pending. */
5650 #else /* Word 0 - Little Endian */
5651 uint32_t sleep : 1; /**< [ 0: 0](SR/W) Sleep.
5652 0 = The parent never asserts WakeRequest.
5653 1 = The parent must assert WakeRequest and hold interrupts as pending. */
5654 uint32_t ps : 1; /**< [ 1: 1](SR/W) Processor sleep.
5655 0 = The redistributor never asserts WakeRequest.
5656 1 = The redistributor must assert WakeRequest and hold interrupts as pending if an enable
5657 bit is zero for an interrupt group and there is a pending interrupt for that group. */
5658 uint32_t ca : 1; /**< [ 2: 2](SRO) Children asleep.
5659 When [PS] is one, the redistributor treats the interrupt group enables as zero
5660 until a subsequent update to the enables is received. */
5661 uint32_t reserved_3_30 : 28;
5662 uint32_t quiescent : 1; /**< [ 31: 31](SRO) Indicates that redistributor is quiescent and can be powered off. */
5663 #endif /* Word 0 - End */
5664 } s;
5665 struct bdk_gicrx_waker_cn9
5666 {
5667 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5668 uint32_t quiescent : 1; /**< [ 31: 31](SRO/H) Indicates that redistributor is quiescent and can be powered off. */
5669 uint32_t reserved_3_30 : 28;
5670 uint32_t ca : 1; /**< [ 2: 2](SRO/H) Children asleep.
5671 When [PS] is one, the redistributor treats the interrupt group enables as zero
5672 until a subsequent update to the enables is received. */
5673 uint32_t ps : 1; /**< [ 1: 1](SR/W) Processor sleep.
5674 0 = The redistributor never asserts WakeRequest.
5675 1 = The redistributor must assert WakeRequest and hold interrupts as pending if an enable
5676 bit is zero for an interrupt group and there is a pending interrupt for that group. */
5677 uint32_t sleep : 1; /**< [ 0: 0](SR/W) Sleep.
5678 0 = The parent never asserts WakeRequest.
5679 1 = The parent must assert WakeRequest and hold interrupts as pending. */
5680 #else /* Word 0 - Little Endian */
5681 uint32_t sleep : 1; /**< [ 0: 0](SR/W) Sleep.
5682 0 = The parent never asserts WakeRequest.
5683 1 = The parent must assert WakeRequest and hold interrupts as pending. */
5684 uint32_t ps : 1; /**< [ 1: 1](SR/W) Processor sleep.
5685 0 = The redistributor never asserts WakeRequest.
5686 1 = The redistributor must assert WakeRequest and hold interrupts as pending if an enable
5687 bit is zero for an interrupt group and there is a pending interrupt for that group. */
5688 uint32_t ca : 1; /**< [ 2: 2](SRO/H) Children asleep.
5689 When [PS] is one, the redistributor treats the interrupt group enables as zero
5690 until a subsequent update to the enables is received. */
5691 uint32_t reserved_3_30 : 28;
5692 uint32_t quiescent : 1; /**< [ 31: 31](SRO/H) Indicates that redistributor is quiescent and can be powered off. */
5693 #endif /* Word 0 - End */
5694 } cn9;
5695 /* struct bdk_gicrx_waker_cn9 cn81xx; */
5696 /* struct bdk_gicrx_waker_s cn88xx; */
5697 /* struct bdk_gicrx_waker_cn9 cn83xx; */
5698 };
5699 typedef union bdk_gicrx_waker bdk_gicrx_waker_t;
5700
5701 static inline uint64_t BDK_GICRX_WAKER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GICRX_WAKER(unsigned long a)5702 static inline uint64_t BDK_GICRX_WAKER(unsigned long a)
5703 {
5704 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
5705 return 0x801080000014ll + 0x20000ll * ((a) & 0x3);
5706 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=23))
5707 return 0x801080000014ll + 0x20000ll * ((a) & 0x1f);
5708 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=47))
5709 return 0x801080000014ll + 0x20000ll * ((a) & 0x3f);
5710 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
5711 return 0x801080000014ll + 0x20000ll * ((a) & 0x1f);
5712 __bdk_csr_fatal("GICRX_WAKER", 1, a, 0, 0, 0);
5713 }
5714
5715 #define typedef_BDK_GICRX_WAKER(a) bdk_gicrx_waker_t
5716 #define bustype_BDK_GICRX_WAKER(a) BDK_CSR_TYPE_NCB32b
5717 #define basename_BDK_GICRX_WAKER(a) "GICRX_WAKER"
5718 #define device_bar_BDK_GICRX_WAKER(a) 0x4 /* PF_BAR4 */
5719 #define busnum_BDK_GICRX_WAKER(a) (a)
5720 #define arguments_BDK_GICRX_WAKER(a) (a),-1,-1,-1
5721
5722 /**
5723 * Register (NCB) gits_baser#
5724 *
5725 * GIC ITS Device Table Registers
5726 * This set of 64-bit registers specify the base address and size of a number of implementation
5727 * defined tables required by the ITS.
5728 * An implementation can provide up to eight such registers.
5729 * Where a register is not implemented, it is RES0.
5730 * Bits [63:32] and bits [31:0] may be accessed independently.
5731 */
5732 union bdk_gits_baserx
5733 {
5734 uint64_t u;
5735 struct bdk_gits_baserx_s
5736 {
5737 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5738 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
5739 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
5740 discards any writes to the interrupt translation page.
5741 1 = Memory has been allocated to the table by software. */
5742 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
5743 table or a two-level table where the first level
5744 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
5745 support flat tables.
5746 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
5747 associated with each table entry.
5748 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
5749 descriptors to pages that are used
5750 to store the data associated with each table entry. Each 64-bit descriptor has the
5751 following format:
5752 * Bits\<63\> = Valid.
5753 * Bits\<62:48\> = Reserved.
5754 * Bits\<47:N\> = Physical address.
5755 * Bits\<N-1:0\> = Reserved.
5756 * Where N is the number of bits required to specify the page size.
5757 Note: software must ensure that each pointer in the first level table specifies a unique
5758 physical address otherwise the effects are unpredictable.
5759 For a two level table, if an entry is invalid:
5760 * If the type field specifies a valid table type other than interrupt collections, the
5761 ITS
5762 discards any writes to the interrupt translation page.
5763 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
5764 zero,
5765 the ITS discards any writes to the interrupt translation page. */
5766 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
5767 0x0 = Noncacheable, nonbufferable.
5768 0x1 = Noncacheable.
5769 0x2 = Read-allocate, writethrough.
5770 0x3 = Read-allocate, writeback.
5771 0x4 = Write-allocate, writethrough.
5772 0x5 = Write-allocate, writeback.
5773 0x6 = Read-allocate, write-allocate, writethrough.
5774 0x7 = Read-allocate, write-allocate, writeback.
5775
5776 In CNXXXX not implemented, ignored. */
5777 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
5778 associated table. The field may have the following values:
5779 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
5780 memory.
5781 0x1 = Devices. This register corresponds to a table that scales according to the number of
5782 devices serviced by the ITS and requires
5783 (Entry-size * number-of-devices) bytes of memory.
5784 0x2 = Virtual processors. This register corresponds to a table that scales according to
5785 the number of virtual processors in the system and
5786 requires (Entry-size * number-of-processors) bytes ofmemory.
5787 0x3 = Physical processors.
5788 0x4 = Interrupt collections.
5789 0x5 = Reserved.
5790 0x6 = Reserved.
5791 0x7 = Reserved.
5792
5793 Software must always provision memory for GITS_BASER() registers where this field
5794 indicate "devices","interrupt collections" or "physical processors". */
5795 uint64_t reserved_12_55 : 44;
5796 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
5797 0x0 = Accesses are nonshareable.
5798 0x1 = Accesses are inner-shareable.
5799 0x2 = Accesses are outer-shareable.
5800 0x3 = Reserved. Treated as 0x0.
5801
5802 Ignored in CNXXXX. */
5803 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
5804 0x0 = 4 KB pages.
5805 0x1 = 16 KB pages (not supported, reserved).
5806 0x2 = 64 KB pages.
5807 0x3 = Reserved. Treated as 64 KB pages. */
5808 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
5809 #else /* Word 0 - Little Endian */
5810 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
5811 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
5812 0x0 = 4 KB pages.
5813 0x1 = 16 KB pages (not supported, reserved).
5814 0x2 = 64 KB pages.
5815 0x3 = Reserved. Treated as 64 KB pages. */
5816 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
5817 0x0 = Accesses are nonshareable.
5818 0x1 = Accesses are inner-shareable.
5819 0x2 = Accesses are outer-shareable.
5820 0x3 = Reserved. Treated as 0x0.
5821
5822 Ignored in CNXXXX. */
5823 uint64_t reserved_12_55 : 44;
5824 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
5825 associated table. The field may have the following values:
5826 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
5827 memory.
5828 0x1 = Devices. This register corresponds to a table that scales according to the number of
5829 devices serviced by the ITS and requires
5830 (Entry-size * number-of-devices) bytes of memory.
5831 0x2 = Virtual processors. This register corresponds to a table that scales according to
5832 the number of virtual processors in the system and
5833 requires (Entry-size * number-of-processors) bytes ofmemory.
5834 0x3 = Physical processors.
5835 0x4 = Interrupt collections.
5836 0x5 = Reserved.
5837 0x6 = Reserved.
5838 0x7 = Reserved.
5839
5840 Software must always provision memory for GITS_BASER() registers where this field
5841 indicate "devices","interrupt collections" or "physical processors". */
5842 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
5843 0x0 = Noncacheable, nonbufferable.
5844 0x1 = Noncacheable.
5845 0x2 = Read-allocate, writethrough.
5846 0x3 = Read-allocate, writeback.
5847 0x4 = Write-allocate, writethrough.
5848 0x5 = Write-allocate, writeback.
5849 0x6 = Read-allocate, write-allocate, writethrough.
5850 0x7 = Read-allocate, write-allocate, writeback.
5851
5852 In CNXXXX not implemented, ignored. */
5853 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
5854 table or a two-level table where the first level
5855 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
5856 support flat tables.
5857 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
5858 associated with each table entry.
5859 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
5860 descriptors to pages that are used
5861 to store the data associated with each table entry. Each 64-bit descriptor has the
5862 following format:
5863 * Bits\<63\> = Valid.
5864 * Bits\<62:48\> = Reserved.
5865 * Bits\<47:N\> = Physical address.
5866 * Bits\<N-1:0\> = Reserved.
5867 * Where N is the number of bits required to specify the page size.
5868 Note: software must ensure that each pointer in the first level table specifies a unique
5869 physical address otherwise the effects are unpredictable.
5870 For a two level table, if an entry is invalid:
5871 * If the type field specifies a valid table type other than interrupt collections, the
5872 ITS
5873 discards any writes to the interrupt translation page.
5874 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
5875 zero,
5876 the ITS discards any writes to the interrupt translation page. */
5877 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
5878 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
5879 discards any writes to the interrupt translation page.
5880 1 = Memory has been allocated to the table by software. */
5881 #endif /* Word 0 - End */
5882 } s;
5883 struct bdk_gits_baserx_cn88xxp1
5884 {
5885 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5886 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
5887 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
5888 discards any writes to the interrupt translation page.
5889 1 = Memory has been allocated to the table by software. */
5890 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
5891 table or a two-level table where the first level
5892 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
5893 support flat tables.
5894 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
5895 associated with each table entry.
5896 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
5897 descriptors to pages that are used
5898 to store the data associated with each table entry. Each 64-bit descriptor has the
5899 following format:
5900 * Bits\<63\> = Valid.
5901 * Bits\<62:48\> = Reserved.
5902 * Bits\<47:N\> = Physical address.
5903 * Bits\<N-1:0\> = Reserved.
5904 * Where N is the number of bits required to specify the page size.
5905 Note: software must ensure that each pointer in the first level table specifies a unique
5906 physical address otherwise the effects are unpredictable.
5907 For a two level table, if an entry is invalid:
5908 * If the type field specifies a valid table type other than interrupt collections, the
5909 ITS
5910 discards any writes to the interrupt translation page.
5911 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
5912 zero,
5913 the ITS discards any writes to the interrupt translation page. */
5914 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
5915 0x0 = Noncacheable, nonbufferable.
5916 0x1 = Noncacheable.
5917 0x2 = Read-allocate, writethrough.
5918 0x3 = Read-allocate, writeback.
5919 0x4 = Write-allocate, writethrough.
5920 0x5 = Write-allocate, writeback.
5921 0x6 = Read-allocate, write-allocate, writethrough.
5922 0x7 = Read-allocate, write-allocate, writeback.
5923
5924 In CNXXXX not implemented, ignored. */
5925 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
5926 associated table. The field may have the following values:
5927 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
5928 memory.
5929 0x1 = Devices. This register corresponds to a table that scales according to the number of
5930 devices serviced by the ITS and requires
5931 (Entry-size * number-of-devices) bytes of memory.
5932 0x2 = Virtual processors. This register corresponds to a table that scales according to
5933 the number of virtual processors in the system and
5934 requires (Entry-size * number-of-processors) bytes ofmemory.
5935 0x3 = Physical processors.
5936 0x4 = Interrupt collections.
5937 0x5 = Reserved.
5938 0x6 = Reserved.
5939 0x7 = Reserved.
5940
5941 Software must always provision memory for GITS_BASER() registers where this field
5942 indicate "devices","interrupt collections" or "physical processors". */
5943 uint64_t entry_size : 8; /**< [ 55: 48](RO) This field is read-only and specifies the number of bytes per entry, minus one. */
5944 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
5945 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. This field provides bits [41:12] of the base physical address of the
5946 table.
5947 Bits [11:0] of the base physical address are zero. The address must be aligned to the size
5948 specified in the page size field. Otherwise the effect is CONSTRAINED UNPREDICTABLE, and
5949 can
5950 be one of the following:
5951 * Bits X:12 (where X is derived from the page size) are treated as zero.
5952 * The value of bits X:12 are used when calculating the address of a table access.
5953
5954 In CNXXXX where the address must be in DRAM this contains fewer than 48 bits of
5955 physical address bits. */
5956 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
5957 0x0 = Accesses are nonshareable.
5958 0x1 = Accesses are inner-shareable.
5959 0x2 = Accesses are outer-shareable.
5960 0x3 = Reserved. Treated as 0x0.
5961
5962 Ignored in CNXXXX. */
5963 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
5964 0x0 = 4 KB pages.
5965 0x1 = 16 KB pages (not supported, reserved).
5966 0x2 = 64 KB pages.
5967 0x3 = Reserved. Treated as 64 KB pages. */
5968 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
5969 #else /* Word 0 - Little Endian */
5970 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
5971 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
5972 0x0 = 4 KB pages.
5973 0x1 = 16 KB pages (not supported, reserved).
5974 0x2 = 64 KB pages.
5975 0x3 = Reserved. Treated as 64 KB pages. */
5976 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
5977 0x0 = Accesses are nonshareable.
5978 0x1 = Accesses are inner-shareable.
5979 0x2 = Accesses are outer-shareable.
5980 0x3 = Reserved. Treated as 0x0.
5981
5982 Ignored in CNXXXX. */
5983 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. This field provides bits [41:12] of the base physical address of the
5984 table.
5985 Bits [11:0] of the base physical address are zero. The address must be aligned to the size
5986 specified in the page size field. Otherwise the effect is CONSTRAINED UNPREDICTABLE, and
5987 can
5988 be one of the following:
5989 * Bits X:12 (where X is derived from the page size) are treated as zero.
5990 * The value of bits X:12 are used when calculating the address of a table access.
5991
5992 In CNXXXX where the address must be in DRAM this contains fewer than 48 bits of
5993 physical address bits. */
5994 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
5995 uint64_t entry_size : 8; /**< [ 55: 48](RO) This field is read-only and specifies the number of bytes per entry, minus one. */
5996 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
5997 associated table. The field may have the following values:
5998 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
5999 memory.
6000 0x1 = Devices. This register corresponds to a table that scales according to the number of
6001 devices serviced by the ITS and requires
6002 (Entry-size * number-of-devices) bytes of memory.
6003 0x2 = Virtual processors. This register corresponds to a table that scales according to
6004 the number of virtual processors in the system and
6005 requires (Entry-size * number-of-processors) bytes ofmemory.
6006 0x3 = Physical processors.
6007 0x4 = Interrupt collections.
6008 0x5 = Reserved.
6009 0x6 = Reserved.
6010 0x7 = Reserved.
6011
6012 Software must always provision memory for GITS_BASER() registers where this field
6013 indicate "devices","interrupt collections" or "physical processors". */
6014 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
6015 0x0 = Noncacheable, nonbufferable.
6016 0x1 = Noncacheable.
6017 0x2 = Read-allocate, writethrough.
6018 0x3 = Read-allocate, writeback.
6019 0x4 = Write-allocate, writethrough.
6020 0x5 = Write-allocate, writeback.
6021 0x6 = Read-allocate, write-allocate, writethrough.
6022 0x7 = Read-allocate, write-allocate, writeback.
6023
6024 In CNXXXX not implemented, ignored. */
6025 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
6026 table or a two-level table where the first level
6027 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
6028 support flat tables.
6029 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
6030 associated with each table entry.
6031 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
6032 descriptors to pages that are used
6033 to store the data associated with each table entry. Each 64-bit descriptor has the
6034 following format:
6035 * Bits\<63\> = Valid.
6036 * Bits\<62:48\> = Reserved.
6037 * Bits\<47:N\> = Physical address.
6038 * Bits\<N-1:0\> = Reserved.
6039 * Where N is the number of bits required to specify the page size.
6040 Note: software must ensure that each pointer in the first level table specifies a unique
6041 physical address otherwise the effects are unpredictable.
6042 For a two level table, if an entry is invalid:
6043 * If the type field specifies a valid table type other than interrupt collections, the
6044 ITS
6045 discards any writes to the interrupt translation page.
6046 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
6047 zero,
6048 the ITS discards any writes to the interrupt translation page. */
6049 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
6050 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
6051 discards any writes to the interrupt translation page.
6052 1 = Memory has been allocated to the table by software. */
6053 #endif /* Word 0 - End */
6054 } cn88xxp1;
6055 struct bdk_gits_baserx_cn9
6056 {
6057 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6058 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
6059 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
6060 discards any writes to the interrupt translation page.
6061 1 = Memory has been allocated to the table by software. */
6062 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
6063 table or a two-level table where the first level
6064 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
6065 support flat tables.
6066 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
6067 associated with each table entry.
6068 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
6069 descriptors to pages that are used
6070 to store the data associated with each table entry. Each 64-bit descriptor has the
6071 following format:
6072 * Bits\<63\> = Valid.
6073 * Bits\<62:52\> = Reserved.
6074 * Bits\<51:N\> = Physical address.
6075 * Bits\<N-1:0\> = Reserved.
6076 * Where N is the number of bits required to specify the page size.
6077 Note: software must ensure that each pointer in the first level table specifies a unique
6078 physical address otherwise the effects are unpredictable.
6079 For a two level table, if an entry is invalid:
6080 * If the type field specifies a valid table type other than interrupt collections, the
6081 ITS
6082 discards any writes to the interrupt translation page.
6083 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
6084 zero,
6085 the ITS discards any writes to the interrupt translation page. */
6086 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table. If the Type field is
6087 zero this field is RAZ/WI.
6088 0x0 = Device-nGnRnE.
6089 0x1 = Normal inner noncacheable.
6090 0x2 = Normal inner cacheable read-allocate, write-through.
6091 0x3 = Normal inner cacheable read-allocate, write-back.
6092 0x4 = Normal inner cacheable write-allocate,write-through.
6093 0x5 = Normal inner cacheable write-allocate,write-back.
6094 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6095 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6096
6097 In CNXXXX not implemented, ignored. */
6098 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
6099 associated table. The field may have the following values:
6100 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
6101 memory.
6102 0x1 = Devices. This register corresponds to a table that scales according to the number of
6103 devices serviced by the ITS and requires
6104 (Entry-size * number-of-devices) bytes of memory.
6105 0x2 = Virtual processors. This register corresponds to a table that scales according to
6106 the number of virtual processors in the system and
6107 requires (Entry-size * number-of-processors) bytes ofmemory.
6108 0x3 = Physical processors.
6109 0x4 = Interrupt collections.
6110 0x5 = Reserved.
6111 0x6 = Reserved.
6112 0x7 = Reserved.
6113
6114 Software must always provision memory for GITS_BASER() registers where this field
6115 indicate "devices","interrupt collections" or "physical processors". */
6116 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6117 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6118 as the inner cacheable.
6119 0x1 = Normal outer noncacheable.
6120 0x2 = Normal outer cacheable read-allocate, write-through.
6121 0x3 = Normal outer cacheable read-allocate, write-back.
6122 0x4 = Normal outer cacheable write-allocate, write-through.
6123 0x5 = Normal outer cacheable write-allocate, write-back.
6124 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6125 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6126
6127 In CNXXXX not implemented, ignored. */
6128 uint64_t entry_size : 5; /**< [ 52: 48](RO) This field is read-only and specifies the number of bytes per entry, minus one. */
6129 uint64_t physical_address : 36; /**< [ 47: 12](R/W) Physical address.
6130 Software must configure this field to point to a valid DRAM base address.
6131 When page size is 4 KB or 16 KB:
6132 * This field provides bits \<47:12\> of the base physical address of the table.
6133 * Bits \<51:48\> and \<11:0\> of the base physical address are zero.
6134 * The address must be aligned to the size specified in the page size field.
6135 Otherwise the effect is CONSTRAINED UNPREDICTABLE, and
6136 can be one of the following:
6137 * Bits X:12 (where X is derived from the page size) are treated as zero.
6138 * The value of bits X:12 are used when calculating the address of a table access.
6139
6140 When page size is 64 KB:
6141 * This field provides bits \<51:16\> of the base physical address of the table.
6142 * Bits \<15:12\> of this field provide bits \<51:48\> of the base physical address.
6143 * Bits \<15:0\> of the base physical address are zero.
6144
6145 In CNXXXX where the address must be in DRAM this contains fewer than 52 bits of
6146 physical address bits. */
6147 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute:
6148 0x0 = Accesses are nonshareable.
6149 0x1 = Accesses are inner-shareable.
6150 0x2 = Accesses are outer-shareable.
6151 0x3 = Reserved. Treated as 0x0.
6152
6153 Ignored in CNXXXX. */
6154 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
6155 0x0 = 4 KB pages.
6156 0x1 = 16 KB pages (not supported, reserved).
6157 0x2 = 64 KB pages.
6158 0x3 = Reserved. Treated as 64 KB pages. */
6159 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
6160 #else /* Word 0 - Little Endian */
6161 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
6162 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
6163 0x0 = 4 KB pages.
6164 0x1 = 16 KB pages (not supported, reserved).
6165 0x2 = 64 KB pages.
6166 0x3 = Reserved. Treated as 64 KB pages. */
6167 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute:
6168 0x0 = Accesses are nonshareable.
6169 0x1 = Accesses are inner-shareable.
6170 0x2 = Accesses are outer-shareable.
6171 0x3 = Reserved. Treated as 0x0.
6172
6173 Ignored in CNXXXX. */
6174 uint64_t physical_address : 36; /**< [ 47: 12](R/W) Physical address.
6175 Software must configure this field to point to a valid DRAM base address.
6176 When page size is 4 KB or 16 KB:
6177 * This field provides bits \<47:12\> of the base physical address of the table.
6178 * Bits \<51:48\> and \<11:0\> of the base physical address are zero.
6179 * The address must be aligned to the size specified in the page size field.
6180 Otherwise the effect is CONSTRAINED UNPREDICTABLE, and
6181 can be one of the following:
6182 * Bits X:12 (where X is derived from the page size) are treated as zero.
6183 * The value of bits X:12 are used when calculating the address of a table access.
6184
6185 When page size is 64 KB:
6186 * This field provides bits \<51:16\> of the base physical address of the table.
6187 * Bits \<15:12\> of this field provide bits \<51:48\> of the base physical address.
6188 * Bits \<15:0\> of the base physical address are zero.
6189
6190 In CNXXXX where the address must be in DRAM this contains fewer than 52 bits of
6191 physical address bits. */
6192 uint64_t entry_size : 5; /**< [ 52: 48](RO) This field is read-only and specifies the number of bytes per entry, minus one. */
6193 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6194 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6195 as the inner cacheable.
6196 0x1 = Normal outer noncacheable.
6197 0x2 = Normal outer cacheable read-allocate, write-through.
6198 0x3 = Normal outer cacheable read-allocate, write-back.
6199 0x4 = Normal outer cacheable write-allocate, write-through.
6200 0x5 = Normal outer cacheable write-allocate, write-back.
6201 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6202 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6203
6204 In CNXXXX not implemented, ignored. */
6205 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
6206 associated table. The field may have the following values:
6207 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
6208 memory.
6209 0x1 = Devices. This register corresponds to a table that scales according to the number of
6210 devices serviced by the ITS and requires
6211 (Entry-size * number-of-devices) bytes of memory.
6212 0x2 = Virtual processors. This register corresponds to a table that scales according to
6213 the number of virtual processors in the system and
6214 requires (Entry-size * number-of-processors) bytes ofmemory.
6215 0x3 = Physical processors.
6216 0x4 = Interrupt collections.
6217 0x5 = Reserved.
6218 0x6 = Reserved.
6219 0x7 = Reserved.
6220
6221 Software must always provision memory for GITS_BASER() registers where this field
6222 indicate "devices","interrupt collections" or "physical processors". */
6223 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table. If the Type field is
6224 zero this field is RAZ/WI.
6225 0x0 = Device-nGnRnE.
6226 0x1 = Normal inner noncacheable.
6227 0x2 = Normal inner cacheable read-allocate, write-through.
6228 0x3 = Normal inner cacheable read-allocate, write-back.
6229 0x4 = Normal inner cacheable write-allocate,write-through.
6230 0x5 = Normal inner cacheable write-allocate,write-back.
6231 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6232 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6233
6234 In CNXXXX not implemented, ignored. */
6235 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
6236 table or a two-level table where the first level
6237 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
6238 support flat tables.
6239 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
6240 associated with each table entry.
6241 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
6242 descriptors to pages that are used
6243 to store the data associated with each table entry. Each 64-bit descriptor has the
6244 following format:
6245 * Bits\<63\> = Valid.
6246 * Bits\<62:52\> = Reserved.
6247 * Bits\<51:N\> = Physical address.
6248 * Bits\<N-1:0\> = Reserved.
6249 * Where N is the number of bits required to specify the page size.
6250 Note: software must ensure that each pointer in the first level table specifies a unique
6251 physical address otherwise the effects are unpredictable.
6252 For a two level table, if an entry is invalid:
6253 * If the type field specifies a valid table type other than interrupt collections, the
6254 ITS
6255 discards any writes to the interrupt translation page.
6256 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
6257 zero,
6258 the ITS discards any writes to the interrupt translation page. */
6259 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
6260 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
6261 discards any writes to the interrupt translation page.
6262 1 = Memory has been allocated to the table by software. */
6263 #endif /* Word 0 - End */
6264 } cn9;
6265 struct bdk_gits_baserx_cn81xx
6266 {
6267 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6268 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
6269 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
6270 discards any writes to the interrupt translation page.
6271 1 = Memory has been allocated to the table by software. */
6272 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
6273 table or a two-level table where the first level
6274 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
6275 support flat tables.
6276 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
6277 associated with each table entry.
6278 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
6279 descriptors to pages that are used
6280 to store the data associated with each table entry. Each 64-bit descriptor has the
6281 following format:
6282 * Bits\<63\> = Valid.
6283 * Bits\<62:48\> = Reserved.
6284 * Bits\<47:N\> = Physical address.
6285 * Bits\<N-1:0\> = Reserved.
6286 * Where N is the number of bits required to specify the page size.
6287 Note: software must ensure that each pointer in the first level table specifies a unique
6288 physical address otherwise the effects are unpredictable.
6289 For a two level table, if an entry is invalid:
6290 * If the type field specifies a valid table type other than interrupt collections, the
6291 ITS
6292 discards any writes to the interrupt translation page.
6293 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
6294 zero,
6295 the ITS discards any writes to the interrupt translation page. */
6296 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table. If the Type field is
6297 zero this field is RAZ/WI.
6298 0x0 = Device-nGnRnE.
6299 0x1 = Normal inner noncacheable.
6300 0x2 = Normal inner cacheable read-allocate, write-through.
6301 0x3 = Normal inner cacheable read-allocate, write-back.
6302 0x4 = Normal inner cacheable write-allocate,write-through.
6303 0x5 = Normal inner cacheable write-allocate,write-back.
6304 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6305 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6306
6307 In CNXXXX not implemented, ignored. */
6308 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
6309 associated table. The field may have the following values:
6310 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
6311 memory.
6312 0x1 = Devices. This register corresponds to a table that scales according to the number of
6313 devices serviced by the ITS and requires
6314 (Entry-size * number-of-devices) bytes of memory.
6315 0x2 = Virtual processors. This register corresponds to a table that scales according to
6316 the number of virtual processors in the system and
6317 requires (Entry-size * number-of-processors) bytes ofmemory.
6318 0x3 = Physical processors.
6319 0x4 = Interrupt collections.
6320 0x5 = Reserved.
6321 0x6 = Reserved.
6322 0x7 = Reserved.
6323
6324 Software must always provision memory for GITS_BASER() registers where this field
6325 indicate "devices","interrupt collections" or "physical processors". */
6326 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6327 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6328 as the inner cacheable.
6329 0x1 = Normal outer noncacheable.
6330 0x2 = Normal outer cacheable read-allocate, write-through.
6331 0x3 = Normal outer cacheable read-allocate, write-back.
6332 0x4 = Normal outer cacheable write-allocate, write-through.
6333 0x5 = Normal outer cacheable write-allocate, write-back.
6334 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6335 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6336
6337 In CNXXXX not implemented, ignored. */
6338 uint64_t entry_size : 5; /**< [ 52: 48](RO) This field is read-only and specifies the number of bytes per entry, minus one. */
6339 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
6340 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. This field provides bits [41:12] of the base physical address of the
6341 table.
6342 Bits [11:0] of the base physical address are zero. The address must be aligned to the size
6343 specified in the page size field. Otherwise the effect is CONSTRAINED UNPREDICTABLE, and
6344 can
6345 be one of the following:
6346 * Bits X:12 (where X is derived from the page size) are treated as zero.
6347 * The value of bits X:12 are used when calculating the address of a table access.
6348
6349 In CNXXXX where the address must be in DRAM this contains fewer than 48 bits of
6350 physical address bits. */
6351 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute:
6352 0x0 = Accesses are nonshareable.
6353 0x1 = Accesses are inner-shareable.
6354 0x2 = Accesses are outer-shareable.
6355 0x3 = Reserved. Treated as 0x0.
6356
6357 Ignored in CNXXXX. */
6358 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
6359 0x0 = 4 KB pages.
6360 0x1 = 16 KB pages (not supported, reserved).
6361 0x2 = 64 KB pages.
6362 0x3 = Reserved. Treated as 64 KB pages. */
6363 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
6364 #else /* Word 0 - Little Endian */
6365 uint64_t size : 8; /**< [ 7: 0](R/W) Size. The number of pages of memory allocated to the table, minus one. */
6366 uint64_t pagesize : 2; /**< [ 9: 8](R/W) Page size:
6367 0x0 = 4 KB pages.
6368 0x1 = 16 KB pages (not supported, reserved).
6369 0x2 = 64 KB pages.
6370 0x3 = Reserved. Treated as 64 KB pages. */
6371 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute:
6372 0x0 = Accesses are nonshareable.
6373 0x1 = Accesses are inner-shareable.
6374 0x2 = Accesses are outer-shareable.
6375 0x3 = Reserved. Treated as 0x0.
6376
6377 Ignored in CNXXXX. */
6378 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. This field provides bits [41:12] of the base physical address of the
6379 table.
6380 Bits [11:0] of the base physical address are zero. The address must be aligned to the size
6381 specified in the page size field. Otherwise the effect is CONSTRAINED UNPREDICTABLE, and
6382 can
6383 be one of the following:
6384 * Bits X:12 (where X is derived from the page size) are treated as zero.
6385 * The value of bits X:12 are used when calculating the address of a table access.
6386
6387 In CNXXXX where the address must be in DRAM this contains fewer than 48 bits of
6388 physical address bits. */
6389 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
6390 uint64_t entry_size : 5; /**< [ 52: 48](RO) This field is read-only and specifies the number of bytes per entry, minus one. */
6391 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6392 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6393 as the inner cacheable.
6394 0x1 = Normal outer noncacheable.
6395 0x2 = Normal outer cacheable read-allocate, write-through.
6396 0x3 = Normal outer cacheable read-allocate, write-back.
6397 0x4 = Normal outer cacheable write-allocate, write-through.
6398 0x5 = Normal outer cacheable write-allocate, write-back.
6399 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6400 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6401
6402 In CNXXXX not implemented, ignored. */
6403 uint64_t tbl_type : 3; /**< [ 58: 56](RO) This field is read-only and specifies the type of entity that requires entries in the
6404 associated table. The field may have the following values:
6405 0x0 = Unimplemented. This register does not correspond to an ITS table and requires no
6406 memory.
6407 0x1 = Devices. This register corresponds to a table that scales according to the number of
6408 devices serviced by the ITS and requires
6409 (Entry-size * number-of-devices) bytes of memory.
6410 0x2 = Virtual processors. This register corresponds to a table that scales according to
6411 the number of virtual processors in the system and
6412 requires (Entry-size * number-of-processors) bytes ofmemory.
6413 0x3 = Physical processors.
6414 0x4 = Interrupt collections.
6415 0x5 = Reserved.
6416 0x6 = Reserved.
6417 0x7 = Reserved.
6418
6419 Software must always provision memory for GITS_BASER() registers where this field
6420 indicate "devices","interrupt collections" or "physical processors". */
6421 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table. If the Type field is
6422 zero this field is RAZ/WI.
6423 0x0 = Device-nGnRnE.
6424 0x1 = Normal inner noncacheable.
6425 0x2 = Normal inner cacheable read-allocate, write-through.
6426 0x3 = Normal inner cacheable read-allocate, write-back.
6427 0x4 = Normal inner cacheable write-allocate,write-through.
6428 0x5 = Normal inner cacheable write-allocate,write-back.
6429 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6430 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6431
6432 In CNXXXX not implemented, ignored. */
6433 uint64_t indirect : 1; /**< [ 62: 62](RO) Indirect.This field indicates whether an implemented register specifies a single, flat
6434 table or a two-level table where the first level
6435 contains a list of descriptors. Note: this field is RAZ/WI for implementations that only
6436 support flat tables.
6437 0 = Single level. [SIZE] indicates a number of pages used by the ITS to store data
6438 associated with each table entry.
6439 1 = Two level. [SIZE] indicates a number of pages which contain an array of 64-bit
6440 descriptors to pages that are used
6441 to store the data associated with each table entry. Each 64-bit descriptor has the
6442 following format:
6443 * Bits\<63\> = Valid.
6444 * Bits\<62:48\> = Reserved.
6445 * Bits\<47:N\> = Physical address.
6446 * Bits\<N-1:0\> = Reserved.
6447 * Where N is the number of bits required to specify the page size.
6448 Note: software must ensure that each pointer in the first level table specifies a unique
6449 physical address otherwise the effects are unpredictable.
6450 For a two level table, if an entry is invalid:
6451 * If the type field specifies a valid table type other than interrupt collections, the
6452 ITS
6453 discards any writes to the interrupt translation page.
6454 * If the type field specifies the interrupt collections table and GITS_TYPER.HCC is
6455 zero,
6456 the ITS discards any writes to the interrupt translation page. */
6457 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid:
6458 0 = No memory has been allocated to the table and if the type field is nonzero, the ITS
6459 discards any writes to the interrupt translation page.
6460 1 = Memory has been allocated to the table by software. */
6461 #endif /* Word 0 - End */
6462 } cn81xx;
6463 /* struct bdk_gits_baserx_cn81xx cn83xx; */
6464 /* struct bdk_gits_baserx_cn81xx cn88xxp2; */
6465 };
6466 typedef union bdk_gits_baserx bdk_gits_baserx_t;
6467
6468 static inline uint64_t BDK_GITS_BASERX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GITS_BASERX(unsigned long a)6469 static inline uint64_t BDK_GITS_BASERX(unsigned long a)
6470 {
6471 if (a==0)
6472 return 0x801000020100ll + 8ll * ((a) & 0x0);
6473 __bdk_csr_fatal("GITS_BASERX", 1, a, 0, 0, 0);
6474 }
6475
6476 #define typedef_BDK_GITS_BASERX(a) bdk_gits_baserx_t
6477 #define bustype_BDK_GITS_BASERX(a) BDK_CSR_TYPE_NCB
6478 #define basename_BDK_GITS_BASERX(a) "GITS_BASERX"
6479 #define device_bar_BDK_GITS_BASERX(a) 0x2 /* PF_BAR2 */
6480 #define busnum_BDK_GITS_BASERX(a) (a)
6481 #define arguments_BDK_GITS_BASERX(a) (a),-1,-1,-1
6482
6483 /**
6484 * Register (NCB) gits_baser#_rowi
6485 *
6486 * GIC ITS Table Registers
6487 * This set of 64-bit registers specify the base address and size of a number of implementation
6488 * defined tables required by the ITS:
6489 * An implementation can provide up to eight such registers.
6490 * Where a register is not implemented, it is RES0.
6491 */
6492 union bdk_gits_baserx_rowi
6493 {
6494 uint64_t u;
6495 struct bdk_gits_baserx_rowi_s
6496 {
6497 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6498 uint64_t reserved_0_63 : 64;
6499 #else /* Word 0 - Little Endian */
6500 uint64_t reserved_0_63 : 64;
6501 #endif /* Word 0 - End */
6502 } s;
6503 /* struct bdk_gits_baserx_rowi_s cn; */
6504 };
6505 typedef union bdk_gits_baserx_rowi bdk_gits_baserx_rowi_t;
6506
6507 static inline uint64_t BDK_GITS_BASERX_ROWI(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GITS_BASERX_ROWI(unsigned long a)6508 static inline uint64_t BDK_GITS_BASERX_ROWI(unsigned long a)
6509 {
6510 if ((a>=1)&&(a<=7))
6511 return 0x801000020100ll + 8ll * ((a) & 0x7);
6512 __bdk_csr_fatal("GITS_BASERX_ROWI", 1, a, 0, 0, 0);
6513 }
6514
6515 #define typedef_BDK_GITS_BASERX_ROWI(a) bdk_gits_baserx_rowi_t
6516 #define bustype_BDK_GITS_BASERX_ROWI(a) BDK_CSR_TYPE_NCB
6517 #define basename_BDK_GITS_BASERX_ROWI(a) "GITS_BASERX_ROWI"
6518 #define device_bar_BDK_GITS_BASERX_ROWI(a) 0x2 /* PF_BAR2 */
6519 #define busnum_BDK_GITS_BASERX_ROWI(a) (a)
6520 #define arguments_BDK_GITS_BASERX_ROWI(a) (a),-1,-1,-1
6521
6522 /**
6523 * Register (NCB) gits_cbaser
6524 *
6525 * GIC ITS Command Queue Base Register
6526 * This register holds the physical memory address of the ITS command queue.
6527 * Note: when GITS_CBASER is successfully written, the value of GITS_CREADR is set to zero. See
6528 * GIC
6529 * spec for details on the ITS initialization sequence. Bits [63:32] and bits [31:0] may be
6530 * accessed
6531 * independently. When GITS_CTLR[ENABLED] is one or GITS_CTLR[QUIESCENT] is zero, this register is
6532 * read-only.
6533 */
6534 union bdk_gits_cbaser
6535 {
6536 uint64_t u;
6537 struct bdk_gits_cbaser_s
6538 {
6539 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6540 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6541 When set to one, indicates that memory has been allocated by software for the command
6542 queue
6543 When set to zero, no memory has been allocated to the command queue and the ITS discards
6544 any writes to the interrupt translation page. */
6545 uint64_t reserved_62 : 1;
6546 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
6547 0x0 = Noncacheable, nonbufferable.
6548 0x1 = Noncacheable.
6549 0x2 = Read-allocate, writethrough.
6550 0x3 = Read-allocate, writeback.
6551 0x4 = Write-allocate, writethrough.
6552 0x5 = Write-allocate, writeback.
6553 0x6 = Read-allocate, write-allocate, writethrough.
6554 0x7 = Read-allocate, write-allocate, writeback.
6555
6556 In CNXXXX not implemented, ignored. */
6557 uint64_t reserved_56_58 : 3;
6558 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6559 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6560 as the inner cacheable.
6561 0x1 = Normal outer noncacheable.
6562 0x2 = Normal outer cacheable read-allocate, write-through.
6563 0x3 = Normal outer cacheable read-allocate, write-back.
6564 0x4 = Normal outer cacheable write-allocate, write-through.
6565 0x5 = Normal outer cacheable write-allocate, write-back.
6566 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6567 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6568
6569 In CNXXXX not implemented, ignored. */
6570 uint64_t reserved_12_52 : 41;
6571 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
6572 0x0 = Accesses are nonshareable.
6573 0x1 = Accesses are inner-shareable.
6574 0x2 = Accesses are outer-shareable.
6575 0x3 = Reserved. Treated as 0x0.
6576
6577 Ignored in CNXXXX. */
6578 uint64_t reserved_8_9 : 2;
6579 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6580 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6581 (SIZE+1)). */
6582 #else /* Word 0 - Little Endian */
6583 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6584 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6585 (SIZE+1)). */
6586 uint64_t reserved_8_9 : 2;
6587 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
6588 0x0 = Accesses are nonshareable.
6589 0x1 = Accesses are inner-shareable.
6590 0x2 = Accesses are outer-shareable.
6591 0x3 = Reserved. Treated as 0x0.
6592
6593 Ignored in CNXXXX. */
6594 uint64_t reserved_12_52 : 41;
6595 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6596 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6597 as the inner cacheable.
6598 0x1 = Normal outer noncacheable.
6599 0x2 = Normal outer cacheable read-allocate, write-through.
6600 0x3 = Normal outer cacheable read-allocate, write-back.
6601 0x4 = Normal outer cacheable write-allocate, write-through.
6602 0x5 = Normal outer cacheable write-allocate, write-back.
6603 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6604 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6605
6606 In CNXXXX not implemented, ignored. */
6607 uint64_t reserved_56_58 : 3;
6608 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
6609 0x0 = Noncacheable, nonbufferable.
6610 0x1 = Noncacheable.
6611 0x2 = Read-allocate, writethrough.
6612 0x3 = Read-allocate, writeback.
6613 0x4 = Write-allocate, writethrough.
6614 0x5 = Write-allocate, writeback.
6615 0x6 = Read-allocate, write-allocate, writethrough.
6616 0x7 = Read-allocate, write-allocate, writeback.
6617
6618 In CNXXXX not implemented, ignored. */
6619 uint64_t reserved_62 : 1;
6620 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6621 When set to one, indicates that memory has been allocated by software for the command
6622 queue
6623 When set to zero, no memory has been allocated to the command queue and the ITS discards
6624 any writes to the interrupt translation page. */
6625 #endif /* Word 0 - End */
6626 } s;
6627 struct bdk_gits_cbaser_cn88xxp1
6628 {
6629 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6630 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6631 When set to one, indicates that memory has been allocated by software for the command
6632 queue
6633 When set to zero, no memory has been allocated to the command queue and the ITS discards
6634 any writes to the interrupt translation page. */
6635 uint64_t reserved_62 : 1;
6636 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
6637 0x0 = Noncacheable, nonbufferable.
6638 0x1 = Noncacheable.
6639 0x2 = Read-allocate, writethrough.
6640 0x3 = Read-allocate, writeback.
6641 0x4 = Write-allocate, writethrough.
6642 0x5 = Write-allocate, writeback.
6643 0x6 = Read-allocate, write-allocate, writethrough.
6644 0x7 = Read-allocate, write-allocate, writeback.
6645
6646 In CNXXXX not implemented, ignored. */
6647 uint64_t reserved_48_58 : 11;
6648 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
6649 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. Provides bits \<47:12\> of the physical address of the memory
6650 containing the command queue. Bits \<11:0\> of the base address of the queue are
6651 zero. */
6652 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
6653 0x0 = Accesses are nonshareable.
6654 0x1 = Accesses are inner-shareable.
6655 0x2 = Accesses are outer-shareable.
6656 0x3 = Reserved. Treated as 0x0.
6657
6658 Ignored in CNXXXX. */
6659 uint64_t reserved_8_9 : 2;
6660 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6661 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6662 (SIZE+1)). */
6663 #else /* Word 0 - Little Endian */
6664 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6665 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6666 (SIZE+1)). */
6667 uint64_t reserved_8_9 : 2;
6668 uint64_t shareability : 2; /**< [ 11: 10](RO) Shareability attribute:
6669 0x0 = Accesses are nonshareable.
6670 0x1 = Accesses are inner-shareable.
6671 0x2 = Accesses are outer-shareable.
6672 0x3 = Reserved. Treated as 0x0.
6673
6674 Ignored in CNXXXX. */
6675 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. Provides bits \<47:12\> of the physical address of the memory
6676 containing the command queue. Bits \<11:0\> of the base address of the queue are
6677 zero. */
6678 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
6679 uint64_t reserved_48_58 : 11;
6680 uint64_t cacheability : 3; /**< [ 61: 59](RO) Cacheability attribute:
6681 0x0 = Noncacheable, nonbufferable.
6682 0x1 = Noncacheable.
6683 0x2 = Read-allocate, writethrough.
6684 0x3 = Read-allocate, writeback.
6685 0x4 = Write-allocate, writethrough.
6686 0x5 = Write-allocate, writeback.
6687 0x6 = Read-allocate, write-allocate, writethrough.
6688 0x7 = Read-allocate, write-allocate, writeback.
6689
6690 In CNXXXX not implemented, ignored. */
6691 uint64_t reserved_62 : 1;
6692 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6693 When set to one, indicates that memory has been allocated by software for the command
6694 queue
6695 When set to zero, no memory has been allocated to the command queue and the ITS discards
6696 any writes to the interrupt translation page. */
6697 #endif /* Word 0 - End */
6698 } cn88xxp1;
6699 struct bdk_gits_cbaser_cn9
6700 {
6701 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6702 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6703 When set to one, indicates that memory has been allocated by software for the command
6704 queue
6705 When set to zero, no memory has been allocated to the command queue and the ITS discards
6706 any writes to the interrupt translation page. */
6707 uint64_t reserved_62 : 1;
6708 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table.
6709 0x0 = Device-nGnRnE.
6710 0x1 = Normal inner noncacheable.
6711 0x2 = Normal inner cacheable read-allocate, write-through.
6712 0x3 = Normal inner cacheable read-allocate, write-back.
6713 0x4 = Normal inner cacheable write-allocate, write-through.
6714 0x5 = Normal inner cacheable write-allocate, write-back.
6715 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6716 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6717 In CNXXXX not implemented, ignored. */
6718 uint64_t reserved_56_58 : 3;
6719 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6720 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6721 as the inner cacheable.
6722 0x1 = Normal outer noncacheable.
6723 0x2 = Normal outer cacheable read-allocate, write-through.
6724 0x3 = Normal outer cacheable read-allocate, write-back.
6725 0x4 = Normal outer cacheable write-allocate, write-through.
6726 0x5 = Normal outer cacheable write-allocate, write-back.
6727 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6728 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6729
6730 In CNXXXX not implemented, ignored. */
6731 uint64_t reserved_52 : 1;
6732 uint64_t physical_address : 40; /**< [ 51: 12](R/W) Physical address. Provides bits \<51:12\> of the physical address of the memory
6733 containing the command queue. Bits \<11:0\> of the base address of the queue are
6734 zero.
6735 Software must configure this field to point to a valid DRAM base address.
6736 If bits \<15:12\> are not all zeros, behavior is CONSTRAINED UNPREDICTABLE
6737 and the result of the calculation of an address for a command queue read
6738 can be corrupted. */
6739 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute. The shareability attributes of accesses to the table.
6740 0x0 = Accesses are non-shareable.
6741 0x1 = Accesses are inner-shareable.
6742 0x2 = Accesses are outer-shareable.
6743 0x3 = Reserved. Treated as 0x0.
6744
6745 In CNXXXX not implemented, ignored. */
6746 uint64_t reserved_8_9 : 2;
6747 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6748 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6749 (SIZE+1)). */
6750 #else /* Word 0 - Little Endian */
6751 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6752 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6753 (SIZE+1)). */
6754 uint64_t reserved_8_9 : 2;
6755 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute. The shareability attributes of accesses to the table.
6756 0x0 = Accesses are non-shareable.
6757 0x1 = Accesses are inner-shareable.
6758 0x2 = Accesses are outer-shareable.
6759 0x3 = Reserved. Treated as 0x0.
6760
6761 In CNXXXX not implemented, ignored. */
6762 uint64_t physical_address : 40; /**< [ 51: 12](R/W) Physical address. Provides bits \<51:12\> of the physical address of the memory
6763 containing the command queue. Bits \<11:0\> of the base address of the queue are
6764 zero.
6765 Software must configure this field to point to a valid DRAM base address.
6766 If bits \<15:12\> are not all zeros, behavior is CONSTRAINED UNPREDICTABLE
6767 and the result of the calculation of an address for a command queue read
6768 can be corrupted. */
6769 uint64_t reserved_52 : 1;
6770 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6771 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6772 as the inner cacheable.
6773 0x1 = Normal outer noncacheable.
6774 0x2 = Normal outer cacheable read-allocate, write-through.
6775 0x3 = Normal outer cacheable read-allocate, write-back.
6776 0x4 = Normal outer cacheable write-allocate, write-through.
6777 0x5 = Normal outer cacheable write-allocate, write-back.
6778 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6779 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6780
6781 In CNXXXX not implemented, ignored. */
6782 uint64_t reserved_56_58 : 3;
6783 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table.
6784 0x0 = Device-nGnRnE.
6785 0x1 = Normal inner noncacheable.
6786 0x2 = Normal inner cacheable read-allocate, write-through.
6787 0x3 = Normal inner cacheable read-allocate, write-back.
6788 0x4 = Normal inner cacheable write-allocate, write-through.
6789 0x5 = Normal inner cacheable write-allocate, write-back.
6790 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6791 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6792 In CNXXXX not implemented, ignored. */
6793 uint64_t reserved_62 : 1;
6794 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6795 When set to one, indicates that memory has been allocated by software for the command
6796 queue
6797 When set to zero, no memory has been allocated to the command queue and the ITS discards
6798 any writes to the interrupt translation page. */
6799 #endif /* Word 0 - End */
6800 } cn9;
6801 struct bdk_gits_cbaser_cn81xx
6802 {
6803 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6804 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6805 When set to one, indicates that memory has been allocated by software for the command
6806 queue
6807 When set to zero, no memory has been allocated to the command queue and the ITS discards
6808 any writes to the interrupt translation page. */
6809 uint64_t reserved_62 : 1;
6810 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table.
6811 0x0 = Device-nGnRnE.
6812 0x1 = Normal inner noncacheable.
6813 0x2 = Normal inner cacheable read-allocate, write-through.
6814 0x3 = Normal inner cacheable read-allocate, write-back.
6815 0x4 = Normal inner cacheable write-allocate, write-through.
6816 0x5 = Normal inner cacheable write-allocate, write-back.
6817 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6818 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6819 In CNXXXX not implemented, ignored. */
6820 uint64_t reserved_56_58 : 3;
6821 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6822 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6823 as the inner cacheable.
6824 0x1 = Normal outer noncacheable.
6825 0x2 = Normal outer cacheable read-allocate, write-through.
6826 0x3 = Normal outer cacheable read-allocate, write-back.
6827 0x4 = Normal outer cacheable write-allocate, write-through.
6828 0x5 = Normal outer cacheable write-allocate, write-back.
6829 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6830 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6831
6832 In CNXXXX not implemented, ignored. */
6833 uint64_t reserved_48_52 : 5;
6834 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
6835 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. Provides bits \<47:12\> of the physical address of the memory
6836 containing the command queue. Bits \<11:0\> of the base address of the queue are
6837 zero. */
6838 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute. The shareability attributes of accesses to the table.
6839 0x0 = Accesses are non-shareable.
6840 0x1 = Accesses are inner-shareable.
6841 0x2 = Accesses are outer-shareable.
6842 0x3 = Reserved. Treated as 0x0.
6843
6844 In CNXXXX not implemented, ignored. */
6845 uint64_t reserved_8_9 : 2;
6846 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6847 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6848 (SIZE+1)). */
6849 #else /* Word 0 - Little Endian */
6850 uint64_t size : 8; /**< [ 7: 0](R/W) The number of 4 KB pages of physical memory provided for the command queue, minus one.
6851 The command queue is a circular buffer and wraps at physical address \<47:0\> + (4096 *
6852 (SIZE+1)). */
6853 uint64_t reserved_8_9 : 2;
6854 uint64_t shareability : 2; /**< [ 11: 10](R/W) Shareability attribute. The shareability attributes of accesses to the table.
6855 0x0 = Accesses are non-shareable.
6856 0x1 = Accesses are inner-shareable.
6857 0x2 = Accesses are outer-shareable.
6858 0x3 = Reserved. Treated as 0x0.
6859
6860 In CNXXXX not implemented, ignored. */
6861 uint64_t physical_address : 30; /**< [ 41: 12](R/W) Physical address. Provides bits \<47:12\> of the physical address of the memory
6862 containing the command queue. Bits \<11:0\> of the base address of the queue are
6863 zero. */
6864 uint64_t arsvd : 6; /**< [ 47: 42](R/W) Reserved; must be zero. This field will be ignored if not zero. */
6865 uint64_t reserved_48_52 : 5;
6866 uint64_t outer_cacheability : 3; /**< [ 55: 53](R/W) Outer cacheability. The cacheability attributes of accesses to the table.
6867 0x0 = Memory type defined in bits[61:59]; for normal memory outer cacheability is the same
6868 as the inner cacheable.
6869 0x1 = Normal outer noncacheable.
6870 0x2 = Normal outer cacheable read-allocate, write-through.
6871 0x3 = Normal outer cacheable read-allocate, write-back.
6872 0x4 = Normal outer cacheable write-allocate, write-through.
6873 0x5 = Normal outer cacheable write-allocate, write-back.
6874 0x6 = Normal outer cacheable read-allocate, write-allocate, write-through.
6875 0x7 = Normal outer cacheable read-allocate, write-allocate, write-back.
6876
6877 In CNXXXX not implemented, ignored. */
6878 uint64_t reserved_56_58 : 3;
6879 uint64_t cacheability : 3; /**< [ 61: 59](R/W) Cacheability. The cacheability attributes of accesses to the table.
6880 0x0 = Device-nGnRnE.
6881 0x1 = Normal inner noncacheable.
6882 0x2 = Normal inner cacheable read-allocate, write-through.
6883 0x3 = Normal inner cacheable read-allocate, write-back.
6884 0x4 = Normal inner cacheable write-allocate, write-through.
6885 0x5 = Normal inner cacheable write-allocate, write-back.
6886 0x6 = Normal inner cacheable read-allocate, write-allocate, write-through.
6887 0x7 = Normal inner cacheable read-allocate, write-allocate, write-back.
6888 In CNXXXX not implemented, ignored. */
6889 uint64_t reserved_62 : 1;
6890 uint64_t valid : 1; /**< [ 63: 63](R/W) Valid.
6891 When set to one, indicates that memory has been allocated by software for the command
6892 queue
6893 When set to zero, no memory has been allocated to the command queue and the ITS discards
6894 any writes to the interrupt translation page. */
6895 #endif /* Word 0 - End */
6896 } cn81xx;
6897 /* struct bdk_gits_cbaser_cn81xx cn83xx; */
6898 /* struct bdk_gits_cbaser_cn81xx cn88xxp2; */
6899 };
6900 typedef union bdk_gits_cbaser bdk_gits_cbaser_t;
6901
6902 #define BDK_GITS_CBASER BDK_GITS_CBASER_FUNC()
6903 static inline uint64_t BDK_GITS_CBASER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CBASER_FUNC(void)6904 static inline uint64_t BDK_GITS_CBASER_FUNC(void)
6905 {
6906 return 0x801000020080ll;
6907 }
6908
6909 #define typedef_BDK_GITS_CBASER bdk_gits_cbaser_t
6910 #define bustype_BDK_GITS_CBASER BDK_CSR_TYPE_NCB
6911 #define basename_BDK_GITS_CBASER "GITS_CBASER"
6912 #define device_bar_BDK_GITS_CBASER 0x2 /* PF_BAR2 */
6913 #define busnum_BDK_GITS_CBASER 0
6914 #define arguments_BDK_GITS_CBASER -1,-1,-1,-1
6915
6916 /**
6917 * Register (NCB32b) gits_cidr0
6918 *
6919 * GIC ITS Component Identification Register 0
6920 */
6921 union bdk_gits_cidr0
6922 {
6923 uint32_t u;
6924 struct bdk_gits_cidr0_s
6925 {
6926 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6927 uint32_t reserved_8_31 : 24;
6928 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
6929 #else /* Word 0 - Little Endian */
6930 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
6931 uint32_t reserved_8_31 : 24;
6932 #endif /* Word 0 - End */
6933 } s;
6934 /* struct bdk_gits_cidr0_s cn; */
6935 };
6936 typedef union bdk_gits_cidr0 bdk_gits_cidr0_t;
6937
6938 #define BDK_GITS_CIDR0 BDK_GITS_CIDR0_FUNC()
6939 static inline uint64_t BDK_GITS_CIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CIDR0_FUNC(void)6940 static inline uint64_t BDK_GITS_CIDR0_FUNC(void)
6941 {
6942 return 0x80100002fff0ll;
6943 }
6944
6945 #define typedef_BDK_GITS_CIDR0 bdk_gits_cidr0_t
6946 #define bustype_BDK_GITS_CIDR0 BDK_CSR_TYPE_NCB32b
6947 #define basename_BDK_GITS_CIDR0 "GITS_CIDR0"
6948 #define device_bar_BDK_GITS_CIDR0 0x2 /* PF_BAR2 */
6949 #define busnum_BDK_GITS_CIDR0 0
6950 #define arguments_BDK_GITS_CIDR0 -1,-1,-1,-1
6951
6952 /**
6953 * Register (NCB32b) gits_cidr1
6954 *
6955 * GIC ITS Component Identification Register 1
6956 */
6957 union bdk_gits_cidr1
6958 {
6959 uint32_t u;
6960 struct bdk_gits_cidr1_s
6961 {
6962 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6963 uint32_t reserved_8_31 : 24;
6964 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
6965 #else /* Word 0 - Little Endian */
6966 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
6967 uint32_t reserved_8_31 : 24;
6968 #endif /* Word 0 - End */
6969 } s;
6970 /* struct bdk_gits_cidr1_s cn; */
6971 };
6972 typedef union bdk_gits_cidr1 bdk_gits_cidr1_t;
6973
6974 #define BDK_GITS_CIDR1 BDK_GITS_CIDR1_FUNC()
6975 static inline uint64_t BDK_GITS_CIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CIDR1_FUNC(void)6976 static inline uint64_t BDK_GITS_CIDR1_FUNC(void)
6977 {
6978 return 0x80100002fff4ll;
6979 }
6980
6981 #define typedef_BDK_GITS_CIDR1 bdk_gits_cidr1_t
6982 #define bustype_BDK_GITS_CIDR1 BDK_CSR_TYPE_NCB32b
6983 #define basename_BDK_GITS_CIDR1 "GITS_CIDR1"
6984 #define device_bar_BDK_GITS_CIDR1 0x2 /* PF_BAR2 */
6985 #define busnum_BDK_GITS_CIDR1 0
6986 #define arguments_BDK_GITS_CIDR1 -1,-1,-1,-1
6987
6988 /**
6989 * Register (NCB32b) gits_cidr2
6990 *
6991 * GIC ITS Component Identification Register 2
6992 */
6993 union bdk_gits_cidr2
6994 {
6995 uint32_t u;
6996 struct bdk_gits_cidr2_s
6997 {
6998 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6999 uint32_t reserved_8_31 : 24;
7000 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
7001 #else /* Word 0 - Little Endian */
7002 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
7003 uint32_t reserved_8_31 : 24;
7004 #endif /* Word 0 - End */
7005 } s;
7006 /* struct bdk_gits_cidr2_s cn; */
7007 };
7008 typedef union bdk_gits_cidr2 bdk_gits_cidr2_t;
7009
7010 #define BDK_GITS_CIDR2 BDK_GITS_CIDR2_FUNC()
7011 static inline uint64_t BDK_GITS_CIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CIDR2_FUNC(void)7012 static inline uint64_t BDK_GITS_CIDR2_FUNC(void)
7013 {
7014 return 0x80100002fff8ll;
7015 }
7016
7017 #define typedef_BDK_GITS_CIDR2 bdk_gits_cidr2_t
7018 #define bustype_BDK_GITS_CIDR2 BDK_CSR_TYPE_NCB32b
7019 #define basename_BDK_GITS_CIDR2 "GITS_CIDR2"
7020 #define device_bar_BDK_GITS_CIDR2 0x2 /* PF_BAR2 */
7021 #define busnum_BDK_GITS_CIDR2 0
7022 #define arguments_BDK_GITS_CIDR2 -1,-1,-1,-1
7023
7024 /**
7025 * Register (NCB32b) gits_cidr3
7026 *
7027 * GIC ITS Component Identification Register 3
7028 */
7029 union bdk_gits_cidr3
7030 {
7031 uint32_t u;
7032 struct bdk_gits_cidr3_s
7033 {
7034 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7035 uint32_t reserved_8_31 : 24;
7036 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
7037 #else /* Word 0 - Little Endian */
7038 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
7039 uint32_t reserved_8_31 : 24;
7040 #endif /* Word 0 - End */
7041 } s;
7042 /* struct bdk_gits_cidr3_s cn; */
7043 };
7044 typedef union bdk_gits_cidr3 bdk_gits_cidr3_t;
7045
7046 #define BDK_GITS_CIDR3 BDK_GITS_CIDR3_FUNC()
7047 static inline uint64_t BDK_GITS_CIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CIDR3_FUNC(void)7048 static inline uint64_t BDK_GITS_CIDR3_FUNC(void)
7049 {
7050 return 0x80100002fffcll;
7051 }
7052
7053 #define typedef_BDK_GITS_CIDR3 bdk_gits_cidr3_t
7054 #define bustype_BDK_GITS_CIDR3 BDK_CSR_TYPE_NCB32b
7055 #define basename_BDK_GITS_CIDR3 "GITS_CIDR3"
7056 #define device_bar_BDK_GITS_CIDR3 0x2 /* PF_BAR2 */
7057 #define busnum_BDK_GITS_CIDR3 0
7058 #define arguments_BDK_GITS_CIDR3 -1,-1,-1,-1
7059
7060 /**
7061 * Register (NCB) gits_creadr
7062 *
7063 * GIC ITS Command Queue Read Register
7064 * Offset in the ITS command queue from GITS_CBASER where the next command will be read by the
7065 * ITS.
7066 *
7067 * The command queue is considered to be empty when GITS_CWRITER is equal to GITS_CREADR.
7068 *
7069 * The command queue is considered to be full when GITS_CWRITER is equal to (GITS_CREADR minus
7070 * 32), taking wrapping into account.
7071 *
7072 * Note: when GITS_CBASER is written, the value of GITS_CREADR is set to zero.
7073 */
7074 union bdk_gits_creadr
7075 {
7076 uint64_t u;
7077 struct bdk_gits_creadr_s
7078 {
7079 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7080 uint64_t reserved_20_63 : 44;
7081 uint64_t offset : 15; /**< [ 19: 5](RO/H) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where the ITS will
7082 read the next command. Bits \<4:0\> of the offset are zero. */
7083 uint64_t reserved_1_4 : 4;
7084 uint64_t stalled : 1; /**< [ 0: 0](RAZ) ITS commands are not stalled due to an error. */
7085 #else /* Word 0 - Little Endian */
7086 uint64_t stalled : 1; /**< [ 0: 0](RAZ) ITS commands are not stalled due to an error. */
7087 uint64_t reserved_1_4 : 4;
7088 uint64_t offset : 15; /**< [ 19: 5](RO/H) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where the ITS will
7089 read the next command. Bits \<4:0\> of the offset are zero. */
7090 uint64_t reserved_20_63 : 44;
7091 #endif /* Word 0 - End */
7092 } s;
7093 struct bdk_gits_creadr_cn8
7094 {
7095 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7096 uint64_t reserved_20_63 : 44;
7097 uint64_t offset : 15; /**< [ 19: 5](RO/H) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where the ITS will
7098 read the next command. Bits \<4:0\> of the offset are zero. */
7099 uint64_t reserved_0_4 : 5;
7100 #else /* Word 0 - Little Endian */
7101 uint64_t reserved_0_4 : 5;
7102 uint64_t offset : 15; /**< [ 19: 5](RO/H) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where the ITS will
7103 read the next command. Bits \<4:0\> of the offset are zero. */
7104 uint64_t reserved_20_63 : 44;
7105 #endif /* Word 0 - End */
7106 } cn8;
7107 /* struct bdk_gits_creadr_s cn9; */
7108 };
7109 typedef union bdk_gits_creadr bdk_gits_creadr_t;
7110
7111 #define BDK_GITS_CREADR BDK_GITS_CREADR_FUNC()
7112 static inline uint64_t BDK_GITS_CREADR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CREADR_FUNC(void)7113 static inline uint64_t BDK_GITS_CREADR_FUNC(void)
7114 {
7115 return 0x801000020090ll;
7116 }
7117
7118 #define typedef_BDK_GITS_CREADR bdk_gits_creadr_t
7119 #define bustype_BDK_GITS_CREADR BDK_CSR_TYPE_NCB
7120 #define basename_BDK_GITS_CREADR "GITS_CREADR"
7121 #define device_bar_BDK_GITS_CREADR 0x2 /* PF_BAR2 */
7122 #define busnum_BDK_GITS_CREADR 0
7123 #define arguments_BDK_GITS_CREADR -1,-1,-1,-1
7124
7125 /**
7126 * Register (NCB32b) gits_ctlr
7127 *
7128 * GIC ITS Control Register
7129 * This register controls the behavior of the interrupt translation service.
7130 */
7131 union bdk_gits_ctlr
7132 {
7133 uint32_t u;
7134 struct bdk_gits_ctlr_s
7135 {
7136 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7137 uint32_t quiescent : 1; /**< [ 31: 31](RO/H) This bit indicates whether the ITS has completed all operations following a write of
7138 enable to zero.
7139 0 = The ITS is not quiescent.
7140 1 = The ITS is quiescent, has completed all operations required to make any mapping data
7141 consistent with external memory and may be powered off. Note: in CCPI
7142 implementations,
7143 the ITS must also have forwarded any required operations to the redistributors and
7144 received confirmation that they have reached the appropriate redistributor. */
7145 uint32_t reserved_1_30 : 30;
7146 uint32_t enabled : 1; /**< [ 0: 0](R/W) Enabled:
7147 0 = ITS is disabled. Writes to the interrupt translation space will be ignored and no
7148 further command queue entries will be processed.
7149 1 = ITS is enabled. Writes to the interrupt translation space will result in interrupt
7150 translations and the command queue will be processed.
7151
7152 If a write to this register changes enabled from one to zero, the ITS must ensure that any
7153 caches containing mapping data must be made
7154 consistent with external memory and [QUIESCENT] must read as one until this has been
7155 completed. */
7156 #else /* Word 0 - Little Endian */
7157 uint32_t enabled : 1; /**< [ 0: 0](R/W) Enabled:
7158 0 = ITS is disabled. Writes to the interrupt translation space will be ignored and no
7159 further command queue entries will be processed.
7160 1 = ITS is enabled. Writes to the interrupt translation space will result in interrupt
7161 translations and the command queue will be processed.
7162
7163 If a write to this register changes enabled from one to zero, the ITS must ensure that any
7164 caches containing mapping data must be made
7165 consistent with external memory and [QUIESCENT] must read as one until this has been
7166 completed. */
7167 uint32_t reserved_1_30 : 30;
7168 uint32_t quiescent : 1; /**< [ 31: 31](RO/H) This bit indicates whether the ITS has completed all operations following a write of
7169 enable to zero.
7170 0 = The ITS is not quiescent.
7171 1 = The ITS is quiescent, has completed all operations required to make any mapping data
7172 consistent with external memory and may be powered off. Note: in CCPI
7173 implementations,
7174 the ITS must also have forwarded any required operations to the redistributors and
7175 received confirmation that they have reached the appropriate redistributor. */
7176 #endif /* Word 0 - End */
7177 } s;
7178 /* struct bdk_gits_ctlr_s cn; */
7179 };
7180 typedef union bdk_gits_ctlr bdk_gits_ctlr_t;
7181
7182 #define BDK_GITS_CTLR BDK_GITS_CTLR_FUNC()
7183 static inline uint64_t BDK_GITS_CTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CTLR_FUNC(void)7184 static inline uint64_t BDK_GITS_CTLR_FUNC(void)
7185 {
7186 return 0x801000020000ll;
7187 }
7188
7189 #define typedef_BDK_GITS_CTLR bdk_gits_ctlr_t
7190 #define bustype_BDK_GITS_CTLR BDK_CSR_TYPE_NCB32b
7191 #define basename_BDK_GITS_CTLR "GITS_CTLR"
7192 #define device_bar_BDK_GITS_CTLR 0x2 /* PF_BAR2 */
7193 #define busnum_BDK_GITS_CTLR 0
7194 #define arguments_BDK_GITS_CTLR -1,-1,-1,-1
7195
7196 /**
7197 * Register (NCB) gits_cwriter
7198 *
7199 * GIC ITS Command Queue Write Register
7200 * Offset in the ITS command queue from GITS_CBASER where the next command will be written by
7201 * software.
7202 *
7203 * The command queue is considered to be empty when GITS_CWRITER is equal to GITS_CREADR.
7204 *
7205 * The command queue is considered to be full when GITS_CWRITER is equal to (GITS_CREADR minus
7206 * 32), taking wrapping into account.
7207 *
7208 * Each command in the queue comprises 32 bytes. See section 5.13 for details of the commands
7209 * supported and the format of each command.
7210 */
7211 union bdk_gits_cwriter
7212 {
7213 uint64_t u;
7214 struct bdk_gits_cwriter_s
7215 {
7216 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7217 uint64_t reserved_20_63 : 44;
7218 uint64_t offset : 15; /**< [ 19: 5](R/W) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where software will
7219 write the next command. Bits \<4:0\> of the offset are zero. */
7220 uint64_t reserved_1_4 : 4;
7221 uint64_t retry : 1; /**< [ 0: 0](RAZ) Retry of processing of ITS commands not supported. */
7222 #else /* Word 0 - Little Endian */
7223 uint64_t retry : 1; /**< [ 0: 0](RAZ) Retry of processing of ITS commands not supported. */
7224 uint64_t reserved_1_4 : 4;
7225 uint64_t offset : 15; /**< [ 19: 5](R/W) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where software will
7226 write the next command. Bits \<4:0\> of the offset are zero. */
7227 uint64_t reserved_20_63 : 44;
7228 #endif /* Word 0 - End */
7229 } s;
7230 struct bdk_gits_cwriter_cn8
7231 {
7232 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7233 uint64_t reserved_20_63 : 44;
7234 uint64_t offset : 15; /**< [ 19: 5](R/W) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where software will
7235 write the next command. Bits \<4:0\> of the offset are zero. */
7236 uint64_t reserved_0_4 : 5;
7237 #else /* Word 0 - Little Endian */
7238 uint64_t reserved_0_4 : 5;
7239 uint64_t offset : 15; /**< [ 19: 5](R/W) Offset. Provides bits \<19:5\> of the offset from GITS_CBASER where software will
7240 write the next command. Bits \<4:0\> of the offset are zero. */
7241 uint64_t reserved_20_63 : 44;
7242 #endif /* Word 0 - End */
7243 } cn8;
7244 /* struct bdk_gits_cwriter_s cn9; */
7245 };
7246 typedef union bdk_gits_cwriter bdk_gits_cwriter_t;
7247
7248 #define BDK_GITS_CWRITER BDK_GITS_CWRITER_FUNC()
7249 static inline uint64_t BDK_GITS_CWRITER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_CWRITER_FUNC(void)7250 static inline uint64_t BDK_GITS_CWRITER_FUNC(void)
7251 {
7252 return 0x801000020088ll;
7253 }
7254
7255 #define typedef_BDK_GITS_CWRITER bdk_gits_cwriter_t
7256 #define bustype_BDK_GITS_CWRITER BDK_CSR_TYPE_NCB
7257 #define basename_BDK_GITS_CWRITER "GITS_CWRITER"
7258 #define device_bar_BDK_GITS_CWRITER 0x2 /* PF_BAR2 */
7259 #define busnum_BDK_GITS_CWRITER 0
7260 #define arguments_BDK_GITS_CWRITER -1,-1,-1,-1
7261
7262 /**
7263 * Register (NCB32b) gits_iidr
7264 *
7265 * GIC ITS Implementation Identification Register
7266 * This 32-bit register is read-only and specifies the version and features supported by the ITS.
7267 */
7268 union bdk_gits_iidr
7269 {
7270 uint32_t u;
7271 struct bdk_gits_iidr_s
7272 {
7273 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7274 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
7275 In CNXXXX, enumerated by PCC_PROD_E. */
7276 uint32_t reserved_20_23 : 4;
7277 uint32_t variant : 4; /**< [ 19: 16](RO) Indicates the major revision or variant of the product.
7278 On CNXXXX, this is the major revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
7279 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
7280 On CNXXXX, this is the minor revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
7281 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer:
7282 0x34C = Cavium. */
7283 #else /* Word 0 - Little Endian */
7284 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer:
7285 0x34C = Cavium. */
7286 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
7287 On CNXXXX, this is the minor revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
7288 uint32_t variant : 4; /**< [ 19: 16](RO) Indicates the major revision or variant of the product.
7289 On CNXXXX, this is the major revision. See FUS_FUSE_NUM_E::CHIP_ID(). */
7290 uint32_t reserved_20_23 : 4;
7291 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
7292 In CNXXXX, enumerated by PCC_PROD_E. */
7293 #endif /* Word 0 - End */
7294 } s;
7295 /* struct bdk_gits_iidr_s cn; */
7296 };
7297 typedef union bdk_gits_iidr bdk_gits_iidr_t;
7298
7299 #define BDK_GITS_IIDR BDK_GITS_IIDR_FUNC()
7300 static inline uint64_t BDK_GITS_IIDR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_IIDR_FUNC(void)7301 static inline uint64_t BDK_GITS_IIDR_FUNC(void)
7302 {
7303 return 0x801000020004ll;
7304 }
7305
7306 #define typedef_BDK_GITS_IIDR bdk_gits_iidr_t
7307 #define bustype_BDK_GITS_IIDR BDK_CSR_TYPE_NCB32b
7308 #define basename_BDK_GITS_IIDR "GITS_IIDR"
7309 #define device_bar_BDK_GITS_IIDR 0x2 /* PF_BAR2 */
7310 #define busnum_BDK_GITS_IIDR 0
7311 #define arguments_BDK_GITS_IIDR -1,-1,-1,-1
7312
7313 /**
7314 * Register (NCB) gits_imp_cseir
7315 *
7316 * GIC ITS Implementation Defined Command SEI Register
7317 * This register holds the SEI status of the ITS command error.
7318 */
7319 union bdk_gits_imp_cseir
7320 {
7321 uint64_t u;
7322 struct bdk_gits_imp_cseir_s
7323 {
7324 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7325 uint64_t reserved_52_63 : 12;
7326 uint64_t creadr : 15; /**< [ 51: 37](RO/H) The read pointer of the first command with error. */
7327 uint64_t reserved_26_36 : 11;
7328 uint64_t cwriter_oor : 1; /**< [ 25: 25](RO/H) When set, it means command write pointer is out of range. */
7329 uint64_t m : 1; /**< [ 24: 24](RO/H) When set, it means multiple command errors have happened. */
7330 uint64_t reserved_17_23 : 7;
7331 uint64_t v : 1; /**< [ 16: 16](R/W1C/H) When set, the command error is valid. For meaning/encoding of {7'b0, V, CMD,
7332 ERROR}, please see ITS Command error encodings in the GIC specfication. Writing
7333 one to this field, will clear the whole register. */
7334 uint64_t cmd : 8; /**< [ 15: 8](RO/H) Type field of first ITS command that has the error. */
7335 uint64_t error : 8; /**< [ 7: 0](RO/H) Error code for the first error. */
7336 #else /* Word 0 - Little Endian */
7337 uint64_t error : 8; /**< [ 7: 0](RO/H) Error code for the first error. */
7338 uint64_t cmd : 8; /**< [ 15: 8](RO/H) Type field of first ITS command that has the error. */
7339 uint64_t v : 1; /**< [ 16: 16](R/W1C/H) When set, the command error is valid. For meaning/encoding of {7'b0, V, CMD,
7340 ERROR}, please see ITS Command error encodings in the GIC specfication. Writing
7341 one to this field, will clear the whole register. */
7342 uint64_t reserved_17_23 : 7;
7343 uint64_t m : 1; /**< [ 24: 24](RO/H) When set, it means multiple command errors have happened. */
7344 uint64_t cwriter_oor : 1; /**< [ 25: 25](RO/H) When set, it means command write pointer is out of range. */
7345 uint64_t reserved_26_36 : 11;
7346 uint64_t creadr : 15; /**< [ 51: 37](RO/H) The read pointer of the first command with error. */
7347 uint64_t reserved_52_63 : 12;
7348 #endif /* Word 0 - End */
7349 } s;
7350 /* struct bdk_gits_imp_cseir_s cn; */
7351 };
7352 typedef union bdk_gits_imp_cseir bdk_gits_imp_cseir_t;
7353
7354 #define BDK_GITS_IMP_CSEIR BDK_GITS_IMP_CSEIR_FUNC()
7355 static inline uint64_t BDK_GITS_IMP_CSEIR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_IMP_CSEIR_FUNC(void)7356 static inline uint64_t BDK_GITS_IMP_CSEIR_FUNC(void)
7357 {
7358 return 0x801000020020ll;
7359 }
7360
7361 #define typedef_BDK_GITS_IMP_CSEIR bdk_gits_imp_cseir_t
7362 #define bustype_BDK_GITS_IMP_CSEIR BDK_CSR_TYPE_NCB
7363 #define basename_BDK_GITS_IMP_CSEIR "GITS_IMP_CSEIR"
7364 #define device_bar_BDK_GITS_IMP_CSEIR 0x2 /* PF_BAR2 */
7365 #define busnum_BDK_GITS_IMP_CSEIR 0
7366 #define arguments_BDK_GITS_IMP_CSEIR -1,-1,-1,-1
7367
7368 /**
7369 * Register (NCB) gits_imp_tseir
7370 *
7371 * GIC ITS Implementation Defined Translator SEI Register
7372 * This register holds the SEI status of the ITS translator error.
7373 */
7374 union bdk_gits_imp_tseir
7375 {
7376 uint64_t u;
7377 struct bdk_gits_imp_tseir_s
7378 {
7379 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7380 uint64_t v : 1; /**< [ 63: 63](R/W1C/H) When set, the translator error is valid. Write one to this field will clear [V], [M],
7381 [DEV_ID], [INT_ID], and [ERROR]. */
7382 uint64_t m : 1; /**< [ 62: 62](RO/H) When set, it means multiple errors have happened. */
7383 uint64_t reserved_56_61 : 6;
7384 uint64_t dev_id : 24; /**< [ 55: 32](RO/H) Input device ID to the interrupt translator. */
7385 uint64_t reserved_28_31 : 4;
7386 uint64_t int_id : 20; /**< [ 27: 8](RO/H) Input interrupt ID to the interrupt translator. */
7387 uint64_t error : 8; /**< [ 7: 0](RO/H) Error code for the first error. Valid encoding is enumerated by GITS_CMD_ERR_E
7388 and one of GITS_CMD_ERR_E::CSEI_UNMAPPED_DEVICE,
7389 GITS_CMD_ERR_E::CSEI_DEVICE_OOR, GITS_CMD_ERR_E::CSEI_ID_OOR,
7390 GITS_CMD_ERR_E::CSEI_UNMAPPED_INTERRUPT, or
7391 GITS_CMD_ERR_E::CSEI_UNMAPPED_COLLECTION. */
7392 #else /* Word 0 - Little Endian */
7393 uint64_t error : 8; /**< [ 7: 0](RO/H) Error code for the first error. Valid encoding is enumerated by GITS_CMD_ERR_E
7394 and one of GITS_CMD_ERR_E::CSEI_UNMAPPED_DEVICE,
7395 GITS_CMD_ERR_E::CSEI_DEVICE_OOR, GITS_CMD_ERR_E::CSEI_ID_OOR,
7396 GITS_CMD_ERR_E::CSEI_UNMAPPED_INTERRUPT, or
7397 GITS_CMD_ERR_E::CSEI_UNMAPPED_COLLECTION. */
7398 uint64_t int_id : 20; /**< [ 27: 8](RO/H) Input interrupt ID to the interrupt translator. */
7399 uint64_t reserved_28_31 : 4;
7400 uint64_t dev_id : 24; /**< [ 55: 32](RO/H) Input device ID to the interrupt translator. */
7401 uint64_t reserved_56_61 : 6;
7402 uint64_t m : 1; /**< [ 62: 62](RO/H) When set, it means multiple errors have happened. */
7403 uint64_t v : 1; /**< [ 63: 63](R/W1C/H) When set, the translator error is valid. Write one to this field will clear [V], [M],
7404 [DEV_ID], [INT_ID], and [ERROR]. */
7405 #endif /* Word 0 - End */
7406 } s;
7407 struct bdk_gits_imp_tseir_cn8
7408 {
7409 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7410 uint64_t v : 1; /**< [ 63: 63](R/W1C/H) When set, the translator error is valid. Write one to this field will clear [V], [M],
7411 [DEV_ID], [INT_ID], and [ERROR]. */
7412 uint64_t m : 1; /**< [ 62: 62](RO/H) When set, it means multiple errors have happened. */
7413 uint64_t reserved_53_61 : 9;
7414 uint64_t dev_id : 21; /**< [ 52: 32](RO/H) Input device ID to the interrupt translator. */
7415 uint64_t reserved_28_31 : 4;
7416 uint64_t int_id : 20; /**< [ 27: 8](RO/H) Input interrupt ID to the interrupt translator. */
7417 uint64_t error : 8; /**< [ 7: 0](RO/H) Error code for the first error. Valid encoding is enumerated by GITS_CMD_ERR_E
7418 and one of GITS_CMD_ERR_E::CSEI_UNMAPPED_DEVICE,
7419 GITS_CMD_ERR_E::CSEI_DEVICE_OOR, GITS_CMD_ERR_E::CSEI_ID_OOR,
7420 GITS_CMD_ERR_E::CSEI_UNMAPPED_INTERRUPT, or
7421 GITS_CMD_ERR_E::CSEI_UNMAPPED_COLLECTION. */
7422 #else /* Word 0 - Little Endian */
7423 uint64_t error : 8; /**< [ 7: 0](RO/H) Error code for the first error. Valid encoding is enumerated by GITS_CMD_ERR_E
7424 and one of GITS_CMD_ERR_E::CSEI_UNMAPPED_DEVICE,
7425 GITS_CMD_ERR_E::CSEI_DEVICE_OOR, GITS_CMD_ERR_E::CSEI_ID_OOR,
7426 GITS_CMD_ERR_E::CSEI_UNMAPPED_INTERRUPT, or
7427 GITS_CMD_ERR_E::CSEI_UNMAPPED_COLLECTION. */
7428 uint64_t int_id : 20; /**< [ 27: 8](RO/H) Input interrupt ID to the interrupt translator. */
7429 uint64_t reserved_28_31 : 4;
7430 uint64_t dev_id : 21; /**< [ 52: 32](RO/H) Input device ID to the interrupt translator. */
7431 uint64_t reserved_53_61 : 9;
7432 uint64_t m : 1; /**< [ 62: 62](RO/H) When set, it means multiple errors have happened. */
7433 uint64_t v : 1; /**< [ 63: 63](R/W1C/H) When set, the translator error is valid. Write one to this field will clear [V], [M],
7434 [DEV_ID], [INT_ID], and [ERROR]. */
7435 #endif /* Word 0 - End */
7436 } cn8;
7437 /* struct bdk_gits_imp_tseir_s cn9; */
7438 };
7439 typedef union bdk_gits_imp_tseir bdk_gits_imp_tseir_t;
7440
7441 #define BDK_GITS_IMP_TSEIR BDK_GITS_IMP_TSEIR_FUNC()
7442 static inline uint64_t BDK_GITS_IMP_TSEIR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_IMP_TSEIR_FUNC(void)7443 static inline uint64_t BDK_GITS_IMP_TSEIR_FUNC(void)
7444 {
7445 return 0x801000020028ll;
7446 }
7447
7448 #define typedef_BDK_GITS_IMP_TSEIR bdk_gits_imp_tseir_t
7449 #define bustype_BDK_GITS_IMP_TSEIR BDK_CSR_TYPE_NCB
7450 #define basename_BDK_GITS_IMP_TSEIR "GITS_IMP_TSEIR"
7451 #define device_bar_BDK_GITS_IMP_TSEIR 0x2 /* PF_BAR2 */
7452 #define busnum_BDK_GITS_IMP_TSEIR 0
7453 #define arguments_BDK_GITS_IMP_TSEIR -1,-1,-1,-1
7454
7455 /**
7456 * Register (NCB32b) gits_pidr0
7457 *
7458 * GIC ITS Peripheral Identification Register 0
7459 */
7460 union bdk_gits_pidr0
7461 {
7462 uint32_t u;
7463 struct bdk_gits_pidr0_s
7464 {
7465 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7466 uint32_t reserved_8_31 : 24;
7467 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GITS. */
7468 #else /* Word 0 - Little Endian */
7469 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GITS. */
7470 uint32_t reserved_8_31 : 24;
7471 #endif /* Word 0 - End */
7472 } s;
7473 /* struct bdk_gits_pidr0_s cn; */
7474 };
7475 typedef union bdk_gits_pidr0 bdk_gits_pidr0_t;
7476
7477 #define BDK_GITS_PIDR0 BDK_GITS_PIDR0_FUNC()
7478 static inline uint64_t BDK_GITS_PIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR0_FUNC(void)7479 static inline uint64_t BDK_GITS_PIDR0_FUNC(void)
7480 {
7481 return 0x80100002ffe0ll;
7482 }
7483
7484 #define typedef_BDK_GITS_PIDR0 bdk_gits_pidr0_t
7485 #define bustype_BDK_GITS_PIDR0 BDK_CSR_TYPE_NCB32b
7486 #define basename_BDK_GITS_PIDR0 "GITS_PIDR0"
7487 #define device_bar_BDK_GITS_PIDR0 0x2 /* PF_BAR2 */
7488 #define busnum_BDK_GITS_PIDR0 0
7489 #define arguments_BDK_GITS_PIDR0 -1,-1,-1,-1
7490
7491 /**
7492 * Register (NCB32b) gits_pidr1
7493 *
7494 * GIC ITS Peripheral Identification Register 1
7495 */
7496 union bdk_gits_pidr1
7497 {
7498 uint32_t u;
7499 struct bdk_gits_pidr1_s
7500 {
7501 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7502 uint32_t reserved_8_31 : 24;
7503 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
7504 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
7505 #else /* Word 0 - Little Endian */
7506 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
7507 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
7508 uint32_t reserved_8_31 : 24;
7509 #endif /* Word 0 - End */
7510 } s;
7511 /* struct bdk_gits_pidr1_s cn; */
7512 };
7513 typedef union bdk_gits_pidr1 bdk_gits_pidr1_t;
7514
7515 #define BDK_GITS_PIDR1 BDK_GITS_PIDR1_FUNC()
7516 static inline uint64_t BDK_GITS_PIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR1_FUNC(void)7517 static inline uint64_t BDK_GITS_PIDR1_FUNC(void)
7518 {
7519 return 0x80100002ffe4ll;
7520 }
7521
7522 #define typedef_BDK_GITS_PIDR1 bdk_gits_pidr1_t
7523 #define bustype_BDK_GITS_PIDR1 BDK_CSR_TYPE_NCB32b
7524 #define basename_BDK_GITS_PIDR1 "GITS_PIDR1"
7525 #define device_bar_BDK_GITS_PIDR1 0x2 /* PF_BAR2 */
7526 #define busnum_BDK_GITS_PIDR1 0
7527 #define arguments_BDK_GITS_PIDR1 -1,-1,-1,-1
7528
7529 /**
7530 * Register (NCB32b) gits_pidr2
7531 *
7532 * GIC ITS Peripheral Identification Register 2
7533 */
7534 union bdk_gits_pidr2
7535 {
7536 uint32_t u;
7537 struct bdk_gits_pidr2_s
7538 {
7539 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7540 uint32_t reserved_8_31 : 24;
7541 uint32_t archrev : 4; /**< [ 7: 4](RO) Architectural revision:
7542 0x1 = GICv1.
7543 0x2 = GICV2.
7544 0x3 = GICv3.
7545 0x4 = GICv4.
7546 0x5-0xF = Reserved. */
7547 uint32_t usesjepcode : 1; /**< [ 3: 3](RO) JEDEC assigned. */
7548 uint32_t jepid : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
7549 #else /* Word 0 - Little Endian */
7550 uint32_t jepid : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
7551 uint32_t usesjepcode : 1; /**< [ 3: 3](RO) JEDEC assigned. */
7552 uint32_t archrev : 4; /**< [ 7: 4](RO) Architectural revision:
7553 0x1 = GICv1.
7554 0x2 = GICV2.
7555 0x3 = GICv3.
7556 0x4 = GICv4.
7557 0x5-0xF = Reserved. */
7558 uint32_t reserved_8_31 : 24;
7559 #endif /* Word 0 - End */
7560 } s;
7561 /* struct bdk_gits_pidr2_s cn; */
7562 };
7563 typedef union bdk_gits_pidr2 bdk_gits_pidr2_t;
7564
7565 #define BDK_GITS_PIDR2 BDK_GITS_PIDR2_FUNC()
7566 static inline uint64_t BDK_GITS_PIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR2_FUNC(void)7567 static inline uint64_t BDK_GITS_PIDR2_FUNC(void)
7568 {
7569 return 0x80100002ffe8ll;
7570 }
7571
7572 #define typedef_BDK_GITS_PIDR2 bdk_gits_pidr2_t
7573 #define bustype_BDK_GITS_PIDR2 BDK_CSR_TYPE_NCB32b
7574 #define basename_BDK_GITS_PIDR2 "GITS_PIDR2"
7575 #define device_bar_BDK_GITS_PIDR2 0x2 /* PF_BAR2 */
7576 #define busnum_BDK_GITS_PIDR2 0
7577 #define arguments_BDK_GITS_PIDR2 -1,-1,-1,-1
7578
7579 /**
7580 * Register (NCB32b) gits_pidr3
7581 *
7582 * GIC ITS Peripheral Identification Register 3
7583 */
7584 union bdk_gits_pidr3
7585 {
7586 uint32_t u;
7587 struct bdk_gits_pidr3_s
7588 {
7589 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7590 uint32_t reserved_8_31 : 24;
7591 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
7592 uint32_t cmod : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
7593 product, major and minor pass numbers. */
7594 #else /* Word 0 - Little Endian */
7595 uint32_t cmod : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
7596 product, major and minor pass numbers. */
7597 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
7598 uint32_t reserved_8_31 : 24;
7599 #endif /* Word 0 - End */
7600 } s;
7601 /* struct bdk_gits_pidr3_s cn; */
7602 };
7603 typedef union bdk_gits_pidr3 bdk_gits_pidr3_t;
7604
7605 #define BDK_GITS_PIDR3 BDK_GITS_PIDR3_FUNC()
7606 static inline uint64_t BDK_GITS_PIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR3_FUNC(void)7607 static inline uint64_t BDK_GITS_PIDR3_FUNC(void)
7608 {
7609 return 0x80100002ffecll;
7610 }
7611
7612 #define typedef_BDK_GITS_PIDR3 bdk_gits_pidr3_t
7613 #define bustype_BDK_GITS_PIDR3 BDK_CSR_TYPE_NCB32b
7614 #define basename_BDK_GITS_PIDR3 "GITS_PIDR3"
7615 #define device_bar_BDK_GITS_PIDR3 0x2 /* PF_BAR2 */
7616 #define busnum_BDK_GITS_PIDR3 0
7617 #define arguments_BDK_GITS_PIDR3 -1,-1,-1,-1
7618
7619 /**
7620 * Register (NCB32b) gits_pidr4
7621 *
7622 * GIC ITS Peripheral Identification Register 1
7623 */
7624 union bdk_gits_pidr4
7625 {
7626 uint32_t u;
7627 struct bdk_gits_pidr4_s
7628 {
7629 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7630 uint32_t reserved_8_31 : 24;
7631 uint32_t cnt_4k : 4; /**< [ 7: 4](RO) 4 KB Count. This field is 0x4, indicating this is a 64 KB software-visible page. */
7632 uint32_t continuation_code : 4; /**< [ 3: 0](RO) JEP106 continuation code, least significant nibble. Indicates Cavium. */
7633 #else /* Word 0 - Little Endian */
7634 uint32_t continuation_code : 4; /**< [ 3: 0](RO) JEP106 continuation code, least significant nibble. Indicates Cavium. */
7635 uint32_t cnt_4k : 4; /**< [ 7: 4](RO) 4 KB Count. This field is 0x4, indicating this is a 64 KB software-visible page. */
7636 uint32_t reserved_8_31 : 24;
7637 #endif /* Word 0 - End */
7638 } s;
7639 /* struct bdk_gits_pidr4_s cn; */
7640 };
7641 typedef union bdk_gits_pidr4 bdk_gits_pidr4_t;
7642
7643 #define BDK_GITS_PIDR4 BDK_GITS_PIDR4_FUNC()
7644 static inline uint64_t BDK_GITS_PIDR4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR4_FUNC(void)7645 static inline uint64_t BDK_GITS_PIDR4_FUNC(void)
7646 {
7647 return 0x80100002ffd0ll;
7648 }
7649
7650 #define typedef_BDK_GITS_PIDR4 bdk_gits_pidr4_t
7651 #define bustype_BDK_GITS_PIDR4 BDK_CSR_TYPE_NCB32b
7652 #define basename_BDK_GITS_PIDR4 "GITS_PIDR4"
7653 #define device_bar_BDK_GITS_PIDR4 0x2 /* PF_BAR2 */
7654 #define busnum_BDK_GITS_PIDR4 0
7655 #define arguments_BDK_GITS_PIDR4 -1,-1,-1,-1
7656
7657 /**
7658 * Register (NCB32b) gits_pidr5
7659 *
7660 * GIC ITS Peripheral Identification Register 5
7661 */
7662 union bdk_gits_pidr5
7663 {
7664 uint32_t u;
7665 struct bdk_gits_pidr5_s
7666 {
7667 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7668 uint32_t reserved_0_31 : 32;
7669 #else /* Word 0 - Little Endian */
7670 uint32_t reserved_0_31 : 32;
7671 #endif /* Word 0 - End */
7672 } s;
7673 /* struct bdk_gits_pidr5_s cn; */
7674 };
7675 typedef union bdk_gits_pidr5 bdk_gits_pidr5_t;
7676
7677 #define BDK_GITS_PIDR5 BDK_GITS_PIDR5_FUNC()
7678 static inline uint64_t BDK_GITS_PIDR5_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR5_FUNC(void)7679 static inline uint64_t BDK_GITS_PIDR5_FUNC(void)
7680 {
7681 return 0x80100002ffd4ll;
7682 }
7683
7684 #define typedef_BDK_GITS_PIDR5 bdk_gits_pidr5_t
7685 #define bustype_BDK_GITS_PIDR5 BDK_CSR_TYPE_NCB32b
7686 #define basename_BDK_GITS_PIDR5 "GITS_PIDR5"
7687 #define device_bar_BDK_GITS_PIDR5 0x2 /* PF_BAR2 */
7688 #define busnum_BDK_GITS_PIDR5 0
7689 #define arguments_BDK_GITS_PIDR5 -1,-1,-1,-1
7690
7691 /**
7692 * Register (NCB32b) gits_pidr6
7693 *
7694 * GIC ITS Peripheral Identification Register 6
7695 */
7696 union bdk_gits_pidr6
7697 {
7698 uint32_t u;
7699 struct bdk_gits_pidr6_s
7700 {
7701 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7702 uint32_t reserved_0_31 : 32;
7703 #else /* Word 0 - Little Endian */
7704 uint32_t reserved_0_31 : 32;
7705 #endif /* Word 0 - End */
7706 } s;
7707 /* struct bdk_gits_pidr6_s cn; */
7708 };
7709 typedef union bdk_gits_pidr6 bdk_gits_pidr6_t;
7710
7711 #define BDK_GITS_PIDR6 BDK_GITS_PIDR6_FUNC()
7712 static inline uint64_t BDK_GITS_PIDR6_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR6_FUNC(void)7713 static inline uint64_t BDK_GITS_PIDR6_FUNC(void)
7714 {
7715 return 0x80100002ffd8ll;
7716 }
7717
7718 #define typedef_BDK_GITS_PIDR6 bdk_gits_pidr6_t
7719 #define bustype_BDK_GITS_PIDR6 BDK_CSR_TYPE_NCB32b
7720 #define basename_BDK_GITS_PIDR6 "GITS_PIDR6"
7721 #define device_bar_BDK_GITS_PIDR6 0x2 /* PF_BAR2 */
7722 #define busnum_BDK_GITS_PIDR6 0
7723 #define arguments_BDK_GITS_PIDR6 -1,-1,-1,-1
7724
7725 /**
7726 * Register (NCB32b) gits_pidr7
7727 *
7728 * GIC ITS Peripheral Identification Register 7
7729 */
7730 union bdk_gits_pidr7
7731 {
7732 uint32_t u;
7733 struct bdk_gits_pidr7_s
7734 {
7735 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7736 uint32_t reserved_0_31 : 32;
7737 #else /* Word 0 - Little Endian */
7738 uint32_t reserved_0_31 : 32;
7739 #endif /* Word 0 - End */
7740 } s;
7741 /* struct bdk_gits_pidr7_s cn; */
7742 };
7743 typedef union bdk_gits_pidr7 bdk_gits_pidr7_t;
7744
7745 #define BDK_GITS_PIDR7 BDK_GITS_PIDR7_FUNC()
7746 static inline uint64_t BDK_GITS_PIDR7_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_PIDR7_FUNC(void)7747 static inline uint64_t BDK_GITS_PIDR7_FUNC(void)
7748 {
7749 return 0x80100002ffdcll;
7750 }
7751
7752 #define typedef_BDK_GITS_PIDR7 bdk_gits_pidr7_t
7753 #define bustype_BDK_GITS_PIDR7 BDK_CSR_TYPE_NCB32b
7754 #define basename_BDK_GITS_PIDR7 "GITS_PIDR7"
7755 #define device_bar_BDK_GITS_PIDR7 0x2 /* PF_BAR2 */
7756 #define busnum_BDK_GITS_PIDR7 0
7757 #define arguments_BDK_GITS_PIDR7 -1,-1,-1,-1
7758
7759 /**
7760 * Register (NCB32b) gits_translater
7761 *
7762 * GIC ITS Translate Register
7763 * This 32-bit register is write-only. The value written to this register specifies an interrupt
7764 * identifier to be translated for the requesting device.
7765 * A unique device identifier is provided for each requesting device and this is presented to the
7766 * ITS on writes to this register. This device identifier
7767 * is used to index a device table that maps the incoming device identifier to an interrupt
7768 * translation table for that device.
7769 *
7770 * Note that writes to this register with a device identifier that has not been mapped will be
7771 * ignored.
7772 *
7773 * Note that writes to this register with a device identifier that exceed the supported device
7774 * identifier size will be ignored.
7775 *
7776 * Note that this register is provided to enable the generation (and translation) of message
7777 * based interrupts from devices (e.g. MSI or MSI-X writes from PCIe devices).
7778 *
7779 * The register is at the same offset as GICD_SETSPI_NSR in the distributor and GICR()_SETLPIR in
7780 * the redistributor to allow virtualization of guest operating systems
7781 * that directly program devices simply by ensuring the address programmed by the guest can be
7782 * translated by an SMMU to target GITS_TRANSLATER.
7783 */
7784 union bdk_gits_translater
7785 {
7786 uint32_t u;
7787 struct bdk_gits_translater_s
7788 {
7789 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7790 uint32_t int_id : 32; /**< [ 31: 0](WO/H) Interrupt ID. The ID of interrupt to be translated for the requesting device.
7791
7792 Note: the number of interrupt identifier bits is defined by
7793 GITS_TYPER[IDBITS]. Nonzero identifier bits outside this range are ignored.
7794
7795 Note: 16-bit access to bits \<15:0\> of this register must be supported. When written by a
7796 16-bit transaction, bits \<31:16\> are written as zero. This register can not be accessed by
7797 CPU. */
7798 #else /* Word 0 - Little Endian */
7799 uint32_t int_id : 32; /**< [ 31: 0](WO/H) Interrupt ID. The ID of interrupt to be translated for the requesting device.
7800
7801 Note: the number of interrupt identifier bits is defined by
7802 GITS_TYPER[IDBITS]. Nonzero identifier bits outside this range are ignored.
7803
7804 Note: 16-bit access to bits \<15:0\> of this register must be supported. When written by a
7805 16-bit transaction, bits \<31:16\> are written as zero. This register can not be accessed by
7806 CPU. */
7807 #endif /* Word 0 - End */
7808 } s;
7809 /* struct bdk_gits_translater_s cn; */
7810 };
7811 typedef union bdk_gits_translater bdk_gits_translater_t;
7812
7813 #define BDK_GITS_TRANSLATER BDK_GITS_TRANSLATER_FUNC()
7814 static inline uint64_t BDK_GITS_TRANSLATER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_TRANSLATER_FUNC(void)7815 static inline uint64_t BDK_GITS_TRANSLATER_FUNC(void)
7816 {
7817 return 0x801000030040ll;
7818 }
7819
7820 #define typedef_BDK_GITS_TRANSLATER bdk_gits_translater_t
7821 #define bustype_BDK_GITS_TRANSLATER BDK_CSR_TYPE_NCB32b
7822 #define basename_BDK_GITS_TRANSLATER "GITS_TRANSLATER"
7823 #define device_bar_BDK_GITS_TRANSLATER 0x2 /* PF_BAR2 */
7824 #define busnum_BDK_GITS_TRANSLATER 0
7825 #define arguments_BDK_GITS_TRANSLATER -1,-1,-1,-1
7826
7827 /**
7828 * Register (NCB) gits_typer
7829 *
7830 * GIC ITS Type Register
7831 * This register describes features supported by the ITS.
7832 */
7833 union bdk_gits_typer
7834 {
7835 uint64_t u;
7836 struct bdk_gits_typer_s
7837 {
7838 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7839 uint64_t reserved_37_63 : 27;
7840 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit collection ID, GITS_TYPER[CID_BITS] is RES0.
7841 1 = GITS_TYPER[CID_BITS] indicates supported collection ID size
7842 CNXXXX implementations do not support collections in external memory, this bit
7843 reads as zero and number of collections supported is reported by GITS_TYPER[HCC]. */
7844 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
7845 When GITS_TYPER.CIL==0, this field is RES0. */
7846 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
7847 provisioning of external memory. If this field is nonzero,
7848 collections in the range zero to (HCC minus one) are solely maintained in storage within
7849 the ITS.
7850
7851 Internal:
7852 Note when this field is nonzero and an ITS is dynamically powered-off and back
7853 on,
7854 software must ensure that any hardware collections
7855 are re-mapped following power-on. */
7856 uint64_t reserved_20_23 : 4;
7857 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported. See section 4.9.16.
7858 0 = Target addresses correspond to linear processor numbers. See section 5.4.6.
7859 1 = Target addresses correspond to the base physical address of re-distributors. */
7860 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
7861 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-its device ID is defined
7862 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
7863 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
7864 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
7865 implemented is four bytes (32-bit). */
7866 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
7867 uint64_t cct : 1; /**< [ 2: 2](RAZ) Memory backed collection is not supported. */
7868 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and direct injection of Virtual LPIs supported.
7869 This field is zero in GICv3 implementations. */
7870 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
7871 #else /* Word 0 - Little Endian */
7872 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
7873 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and direct injection of Virtual LPIs supported.
7874 This field is zero in GICv3 implementations. */
7875 uint64_t cct : 1; /**< [ 2: 2](RAZ) Memory backed collection is not supported. */
7876 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
7877 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
7878 implemented is four bytes (32-bit). */
7879 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
7880 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-its device ID is defined
7881 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
7882 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
7883 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported. See section 4.9.16.
7884 0 = Target addresses correspond to linear processor numbers. See section 5.4.6.
7885 1 = Target addresses correspond to the base physical address of re-distributors. */
7886 uint64_t reserved_20_23 : 4;
7887 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
7888 provisioning of external memory. If this field is nonzero,
7889 collections in the range zero to (HCC minus one) are solely maintained in storage within
7890 the ITS.
7891
7892 Internal:
7893 Note when this field is nonzero and an ITS is dynamically powered-off and back
7894 on,
7895 software must ensure that any hardware collections
7896 are re-mapped following power-on. */
7897 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
7898 When GITS_TYPER.CIL==0, this field is RES0. */
7899 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit collection ID, GITS_TYPER[CID_BITS] is RES0.
7900 1 = GITS_TYPER[CID_BITS] indicates supported collection ID size
7901 CNXXXX implementations do not support collections in external memory, this bit
7902 reads as zero and number of collections supported is reported by GITS_TYPER[HCC]. */
7903 uint64_t reserved_37_63 : 27;
7904 #endif /* Word 0 - End */
7905 } s;
7906 struct bdk_gits_typer_cn88xxp1
7907 {
7908 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7909 uint64_t reserved_32_63 : 32;
7910 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
7911 provisioning of external memory. If this field is nonzero,
7912 collections in the range zero to (HCC minus one) are solely maintained in storage within
7913 the ITS.
7914
7915 Internal:
7916 Note when this field is nonzero and an ITS is dynamically powered-off and back
7917 on,
7918 software must ensure that any hardware collections
7919 are re-mapped following power-on. */
7920 uint64_t reserved_20_23 : 4;
7921 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported. See section 4.9.16.
7922 0 = Target addresses correspond to linear processor numbers. See section 5.4.6.
7923 1 = Target addresses correspond to the base physical address of re-distributors. */
7924 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
7925 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-its device ID is defined
7926 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
7927 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
7928 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
7929 implemented is four bytes (32-bit). */
7930 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
7931 uint64_t reserved_1_2 : 2;
7932 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
7933 #else /* Word 0 - Little Endian */
7934 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
7935 uint64_t reserved_1_2 : 2;
7936 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
7937 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
7938 implemented is four bytes (32-bit). */
7939 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
7940 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-its device ID is defined
7941 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
7942 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
7943 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported. See section 4.9.16.
7944 0 = Target addresses correspond to linear processor numbers. See section 5.4.6.
7945 1 = Target addresses correspond to the base physical address of re-distributors. */
7946 uint64_t reserved_20_23 : 4;
7947 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
7948 provisioning of external memory. If this field is nonzero,
7949 collections in the range zero to (HCC minus one) are solely maintained in storage within
7950 the ITS.
7951
7952 Internal:
7953 Note when this field is nonzero and an ITS is dynamically powered-off and back
7954 on,
7955 software must ensure that any hardware collections
7956 are re-mapped following power-on. */
7957 uint64_t reserved_32_63 : 32;
7958 #endif /* Word 0 - End */
7959 } cn88xxp1;
7960 struct bdk_gits_typer_cn9
7961 {
7962 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7963 uint64_t reserved_37_63 : 27;
7964 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit collection ID, GITS_TYPER[CID_BITS] is RES0.
7965 1 = GITS_TYPER[CID_BITS] indicates supported collection ID size
7966 CNXXXX implementations do not support collections in external memory, this bit
7967 reads as zero and number of collections supported is reported by GITS_TYPER[HCC]. */
7968 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
7969 When GITS_TYPER.CIL==0, this field is RES0. */
7970 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
7971 provisioning of external memory. If this field is nonzero,
7972 collections in the range zero to (HCC minus one) are solely maintained in storage within
7973 the ITS.
7974 NOTE: Note when this field is nonzero and an ITS is dynamically powered-off and back
7975 on, software must ensure that any hardware collections are remapped following power-on.
7976 A powered back on event is defined as cold reset is asserted and the deasserted from ITS
7977 point of view. */
7978 uint64_t reserved_20_23 : 4;
7979 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported.
7980 0 = Target addresses correspond to linear processor numbers.
7981 1 = Target addresses correspond to the base physical address of re-distributors. */
7982 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
7983 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 24-bit device ID is defined
7984 as {node_id[1:0], iob_id[1:0], ecam_id[3:0], stream_id[15:0]}. */
7985 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
7986 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
7987 implemented is four bytes (32-bit). */
7988 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
7989 uint64_t cct : 1; /**< [ 2: 2](RAZ) Memory backed collection is not supported. */
7990 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and direct injection of Virtual LPIs supported.
7991 This field is zero in GICv3 implementations. */
7992 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
7993 #else /* Word 0 - Little Endian */
7994 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
7995 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and direct injection of Virtual LPIs supported.
7996 This field is zero in GICv3 implementations. */
7997 uint64_t cct : 1; /**< [ 2: 2](RAZ) Memory backed collection is not supported. */
7998 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
7999 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
8000 implemented is four bytes (32-bit). */
8001 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
8002 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 24-bit device ID is defined
8003 as {node_id[1:0], iob_id[1:0], ecam_id[3:0], stream_id[15:0]}. */
8004 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
8005 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported.
8006 0 = Target addresses correspond to linear processor numbers.
8007 1 = Target addresses correspond to the base physical address of re-distributors. */
8008 uint64_t reserved_20_23 : 4;
8009 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
8010 provisioning of external memory. If this field is nonzero,
8011 collections in the range zero to (HCC minus one) are solely maintained in storage within
8012 the ITS.
8013 NOTE: Note when this field is nonzero and an ITS is dynamically powered-off and back
8014 on, software must ensure that any hardware collections are remapped following power-on.
8015 A powered back on event is defined as cold reset is asserted and the deasserted from ITS
8016 point of view. */
8017 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
8018 When GITS_TYPER.CIL==0, this field is RES0. */
8019 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit collection ID, GITS_TYPER[CID_BITS] is RES0.
8020 1 = GITS_TYPER[CID_BITS] indicates supported collection ID size
8021 CNXXXX implementations do not support collections in external memory, this bit
8022 reads as zero and number of collections supported is reported by GITS_TYPER[HCC]. */
8023 uint64_t reserved_37_63 : 27;
8024 #endif /* Word 0 - End */
8025 } cn9;
8026 struct bdk_gits_typer_cn81xx
8027 {
8028 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8029 uint64_t reserved_37_63 : 27;
8030 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit collection ID, GITS_TYPER[CID_BITS] is RES0.
8031 1 = GITS_TYPER[CID_BITS] indicates supported collection ID size
8032 CNXXXX implementations do not support collections in external memory, this bit
8033 reads as zero and number of collections supported is reported by GITS_TYPER[HCC]. */
8034 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
8035 When GITS_TYPER.CIL==0, this field is RES0. */
8036 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
8037 provisioning of external memory. If this field is nonzero,
8038 collections in the range zero to (HCC minus one) are solely maintained in storage within
8039 the ITS.
8040 NOTE: Note when this field is nonzero and an ITS is dynamically powered-off and back
8041 on, software must ensure that any hardware collections are remapped following power-on.
8042 A powered back on event is defined as cold reset is asserted and the deasserted from ITS
8043 point of view. */
8044 uint64_t reserved_20_23 : 4;
8045 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported.
8046 0 = Target addresses correspond to linear processor numbers.
8047 1 = Target addresses correspond to the base physical address of re-distributors. */
8048 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
8049 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-bit device ID is defined
8050 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
8051 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
8052 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
8053 implemented is four bytes (32-bit). */
8054 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
8055 uint64_t reserved_2 : 1;
8056 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and direct injection of Virtual LPIs supported.
8057 This field is zero in GICv3 implementations. */
8058 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
8059 #else /* Word 0 - Little Endian */
8060 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
8061 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and direct injection of Virtual LPIs supported.
8062 This field is zero in GICv3 implementations. */
8063 uint64_t reserved_2 : 1;
8064 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
8065 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
8066 implemented is four bytes (32-bit). */
8067 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
8068 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-bit device ID is defined
8069 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
8070 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
8071 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported.
8072 0 = Target addresses correspond to linear processor numbers.
8073 1 = Target addresses correspond to the base physical address of re-distributors. */
8074 uint64_t reserved_20_23 : 4;
8075 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
8076 provisioning of external memory. If this field is nonzero,
8077 collections in the range zero to (HCC minus one) are solely maintained in storage within
8078 the ITS.
8079 NOTE: Note when this field is nonzero and an ITS is dynamically powered-off and back
8080 on, software must ensure that any hardware collections are remapped following power-on.
8081 A powered back on event is defined as cold reset is asserted and the deasserted from ITS
8082 point of view. */
8083 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
8084 When GITS_TYPER.CIL==0, this field is RES0. */
8085 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit collection ID, GITS_TYPER[CID_BITS] is RES0.
8086 1 = GITS_TYPER[CID_BITS] indicates supported collection ID size
8087 CNXXXX implementations do not support collections in external memory, this bit
8088 reads as zero and number of collections supported is reported by GITS_TYPER[HCC]. */
8089 uint64_t reserved_37_63 : 27;
8090 #endif /* Word 0 - End */
8091 } cn81xx;
8092 /* struct bdk_gits_typer_cn81xx cn83xx; */
8093 struct bdk_gits_typer_cn88xxp2
8094 {
8095 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8096 uint64_t reserved_37_63 : 27;
8097 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit Collection ID, GITS_TYPER[CIDbits] is RES0.
8098 1 = GITS_TYPER[CIDBITS] indicates supported collection ID size
8099 CNXXXX implementations do not support collections in external memory, this bit is
8100 RAZ and number of Collections supported is reported by GITS_TYPER[HCC]. */
8101 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
8102 When GITS_TYPER.CIL==0, this field is RES0. */
8103 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
8104 provisioning of external memory. If this field is nonzero,
8105 collections in the range zero to (HCC minus one) are solely maintained in storage within
8106 the ITS.
8107
8108 NOTE: Note when this field is nonzero and an ITS is dynamically powered-off and back
8109 on, software must ensure that any hardware collections are remapped following power-on.
8110 A powered back on event is defined as cold reset is asserted and the deasserted from ITS
8111 point of view. */
8112 uint64_t reserved_20_23 : 4;
8113 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported.
8114 0 = Target addresses correspond to linear processor numbers.
8115 1 = Target addresses correspond to the base physical address of re-distributors. */
8116 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
8117 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-bit device ID is defined
8118 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
8119 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
8120 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
8121 implemented is four bytes (32-bit). */
8122 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
8123 uint64_t reserved_2 : 1;
8124 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and Direct injection of Virtual LPIs supported. This field is
8125 clear in GICv3 implementations. */
8126 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
8127 #else /* Word 0 - Little Endian */
8128 uint64_t physical : 1; /**< [ 0: 0](RO) Reserved, one. */
8129 uint64_t vlpi : 1; /**< [ 1: 1](RAZ) Reserved. Virtual LPIs and Direct injection of Virtual LPIs supported. This field is
8130 clear in GICv3 implementations. */
8131 uint64_t reserved_2 : 1;
8132 uint64_t distributed : 1; /**< [ 3: 3](RO) Distributed ITS implementation supported. */
8133 uint64_t itte_size : 4; /**< [ 7: 4](RO) ITT entry size. Number of bytes per entry, minus one. The ITT entry size
8134 implemented is four bytes (32-bit). */
8135 uint64_t idbits : 5; /**< [ 12: 8](RO) The number of interrupt identifier bits supported, minus one. */
8136 uint64_t devbits : 5; /**< [ 17: 13](RO) The number of device identifier bits supported, minus one. The 21-bit device ID is defined
8137 as {node_id[1:0], iob_id[2:0], stream_id[15:0]}. */
8138 uint64_t seis : 1; /**< [ 18: 18](RO) Locally generated system error interrupts supported. */
8139 uint64_t pta : 1; /**< [ 19: 19](RO) Physical target addresses supported.
8140 0 = Target addresses correspond to linear processor numbers.
8141 1 = Target addresses correspond to the base physical address of re-distributors. */
8142 uint64_t reserved_20_23 : 4;
8143 uint64_t hcc : 8; /**< [ 31: 24](RO) Hardware collection count. The number of collections supported by the ITS without
8144 provisioning of external memory. If this field is nonzero,
8145 collections in the range zero to (HCC minus one) are solely maintained in storage within
8146 the ITS.
8147
8148 NOTE: Note when this field is nonzero and an ITS is dynamically powered-off and back
8149 on, software must ensure that any hardware collections are remapped following power-on.
8150 A powered back on event is defined as cold reset is asserted and the deasserted from ITS
8151 point of view. */
8152 uint64_t cid_bits : 4; /**< [ 35: 32](RAZ) Number of collection ID bits. The number of bits of collection ID - 1.
8153 When GITS_TYPER.CIL==0, this field is RES0. */
8154 uint64_t cil : 1; /**< [ 36: 36](RAZ) 0 = ITS supports 16-bit Collection ID, GITS_TYPER[CIDbits] is RES0.
8155 1 = GITS_TYPER[CIDBITS] indicates supported collection ID size
8156 CNXXXX implementations do not support collections in external memory, this bit is
8157 RAZ and number of Collections supported is reported by GITS_TYPER[HCC]. */
8158 uint64_t reserved_37_63 : 27;
8159 #endif /* Word 0 - End */
8160 } cn88xxp2;
8161 };
8162 typedef union bdk_gits_typer bdk_gits_typer_t;
8163
8164 #define BDK_GITS_TYPER BDK_GITS_TYPER_FUNC()
8165 static inline uint64_t BDK_GITS_TYPER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GITS_TYPER_FUNC(void)8166 static inline uint64_t BDK_GITS_TYPER_FUNC(void)
8167 {
8168 return 0x801000020008ll;
8169 }
8170
8171 #define typedef_BDK_GITS_TYPER bdk_gits_typer_t
8172 #define bustype_BDK_GITS_TYPER BDK_CSR_TYPE_NCB
8173 #define basename_BDK_GITS_TYPER "GITS_TYPER"
8174 #define device_bar_BDK_GITS_TYPER 0x2 /* PF_BAR2 */
8175 #define busnum_BDK_GITS_TYPER 0
8176 #define arguments_BDK_GITS_TYPER -1,-1,-1,-1
8177
8178 #endif /* __BDK_CSRS_GIC_H__ */
8179