1 /* 2 * Copyright © 2022 Imagination Technologies Ltd. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef PVR_ROGUE_FWIF_H 25 #define PVR_ROGUE_FWIF_H 26 27 #include <assert.h> 28 #include <stddef.h> 29 #include <stdint.h> 30 31 #include "hwdef/rogue_hw_defs.h" 32 #include "pvr_rogue_fwif_shared.h" 33 #include "pvr_winsys.h" 34 #include "util/macros.h" 35 36 /** 37 * \name Frag DM command flags. 38 * Flags supported by the Frag DM command i.e. /ref rogue_fwif_cmd_3d . 39 */ 40 /**@{*/ 41 /** Render needs flipped sample positions. */ 42 #define ROGUE_FWIF_RENDERFLAGS_FLIP_SAMPLE_POSITIONS 0x00000001UL 43 /** 44 * The scene has been aborted, free the parameters and dummy process to 45 * completion. 46 */ 47 #define ROGUE_FWIF_RENDERFLAGS_ABORT 0x00000002UL 48 /** The TA before this was not marked as LAST. */ 49 #define ROGUE_FWIF_RENDERFLAGS_3D_ONLY 0x00000004UL 50 /** Use single core in a multi core setup. */ 51 #define ROGUE_FWIF_RENDERFLAGS_SINGLE_CORE 0x00000008UL 52 /** 53 * This render has visibility result associated with it. Setting this flag will 54 * cause the firmware to collect the visibility results. 55 */ 56 #define ROGUE_FWIF_RENDERFLAGS_GETVISRESULTS 0x00000020UL 57 /** Indicates whether a depth buffer is present. */ 58 #define ROGUE_FWIF_RENDERFLAGS_DEPTHBUFFER 0x00000080UL 59 /** Indicates whether a stencil buffer is present. */ 60 #define ROGUE_FWIF_RENDERFLAGS_STENCILBUFFER 0x00000100UL 61 /** This render needs DRM Security. */ 62 #define ROGUE_FWIF_RENDERFLAGS_SECURE 0x00002000UL 63 /** 64 * This flags goes in hand with ABORT and explicitly ensures no mem free is 65 * issued in case of first TA job. 66 */ 67 #define ROGUE_FWIF_RENDERFLAGS_ABORT_NOFREE 0x00004000UL 68 /** Force disabling of pixel merging. */ 69 #define ROGUE_FWIF_RENDERFLAGS_DISABLE_PIXELMERGE 0x00008000UL 70 71 /** Force 4 lines of coeffs on render. */ 72 #define ROGUE_FWIF_RENDERFLAGS_CSRM_MAX_COEFFS 0x00020000UL 73 74 /** Partial render must write to scratch buffer. */ 75 #define ROGUE_FWIF_RENDERFLAGS_SPMSCRATCHBUFFER 0x00080000UL 76 77 /** Render uses paired tile feature, empty tiles must always be enabled. */ 78 #define ROGUE_FWIF_RENDERFLAGS_PAIRED_TILES 0x00100000UL 79 80 #define ROGUE_FWIF_RENDERFLAGS_RESERVED 0x01000000UL 81 82 /** Disallow compute overlapped with this render. */ 83 #define ROGUE_FWIF_RENDERFLAGS_PREVENT_CDM_OVERLAP 0x04000000UL 84 /**@}*/ 85 /* End of \name Frag DM command flags. */ 86 87 /** 88 * The host must indicate if this is the first and/or last command to be issued 89 * for the specified task. 90 */ 91 92 /** 93 * \name Geom DM command flags. 94 * Flags supported by the Geom DM command i.e. \ref rogue_fwif_cmd_ta . 95 */ 96 /**@{*/ 97 #define ROGUE_FWIF_TAFLAGS_FIRSTKICK 0x00000001UL 98 #define ROGUE_FWIF_TAFLAGS_LASTKICK 0x00000002UL 99 #define ROGUE_FWIF_TAFLAGS_FLIP_SAMPLE_POSITIONS 0x00000004UL 100 /** Use single core in a multi core setup. */ 101 #define ROGUE_FWIF_TAFLAGS_SINGLE_CORE 0x00000008UL 102 103 /** Enable Tile Region Protection for this TA. */ 104 #define ROGUE_FWIF_TAFLAGS_TRP 0x00000010UL 105 106 /** 107 * Indicates the particular TA needs to be aborted. 108 * The scene has been aborted, discard this TA command. 109 */ 110 #define ROGUE_FWIF_TAFLAGS_TA_ABORT 0x00000100UL 111 #define ROGUE_FWIF_TAFLAGS_SECURE 0x00080000UL 112 113 /** 114 * Indicates that the CSRM should be reconfigured to support maximum coeff 115 * space before this command is scheduled. 116 */ 117 #define ROGUE_FWIF_TAFLAGS_CSRM_MAX_COEFFS 0x00200000UL 118 119 #define ROGUE_FWIF_TAFLAGS_PHR_TRIGGER 0x02000000UL 120 /**@}/ 121 * End of \name Geom DM command flags. */ 122 123 /* Flags for transfer queue commands. */ 124 #define ROGUE_FWIF_CMDTRANSFER_FLAG_SECURE 0x00000001U 125 /** Use single core in a multi core setup. */ 126 #define ROGUE_FWIF_CMDTRANSFER_SINGLE_CORE 0x00000002U 127 #define ROGUE_FWIF_CMDTRANSFER_TRP 0x00000004U 128 129 /* Flags for 2D commands. */ 130 #define ROGUE_FWIF_CMD2D_FLAG_SECURE 0x00000001U 131 132 #define ROGUE_FWIF_CMD3DTQ_SLICE_WIDTH_MASK 0x00000038UL 133 #define ROGUE_FWIF_CMD3DTQ_SLICE_WIDTH_SHIFT (3) 134 #define ROGUE_FWIF_CMD3DTQ_SLICE_GRANULARITY (0x10U) 135 136 /* Flags for compute commands. */ 137 #define ROGUE_FWIF_COMPUTE_FLAG_SECURE 0x00000001U 138 #define ROGUE_FWIF_COMPUTE_FLAG_PREVENT_ALL_OVERLAP 0x00000002U 139 #define ROGUE_FWIF_COMPUTE_FLAG_FORCE_TPU_CLK 0x00000004U 140 141 #define ROGUE_FWIF_COMPUTE_FLAG_PREVENT_ALL_NON_TAOOM_OVERLAP 0x00000010U 142 143 /** Use single core in a multi core setup. */ 144 #define ROGUE_FWIF_COMPUTE_FLAG_SINGLE_CORE 0x00000020U 145 146 /*********************************************** 147 Parameter/HWRTData control structures. 148 ***********************************************/ 149 150 /** 151 * \brief Configuration registers which need to be loaded by the firmware before 152 * a TA job can be started. 153 */ 154 struct rogue_fwif_ta_regs { 155 uint64_t vdm_ctrl_stream_base; 156 uint64_t tpu_border_colour_table; 157 158 /* Only used when feature VDM_DRAWINDIRECT present. */ 159 uint64_t vdm_draw_indirect0; 160 /* Only used when feature VDM_DRAWINDIRECT present. */ 161 uint32_t vdm_draw_indirect1; 162 163 uint32_t ppp_ctrl; 164 uint32_t te_psg; 165 /* Only used when BRN 49927 present. */ 166 uint32_t tpu; 167 168 uint32_t vdm_context_resume_task0_size; 169 /* Only used when feature VDM_OBJECT_LEVEL_LLS present. */ 170 uint32_t vdm_context_resume_task3_size; 171 172 /* Only used when BRN 67381 present. */ 173 uint32_t pds_ctrl; 174 175 uint32_t view_idx; 176 177 /* Only used when feature TESSELLATION present */ 178 uint32_t pds_coeff_free_prog; 179 180 uint32_t padding; 181 }; 182 183 /** 184 * \brief Dummy region header registers. 185 */ 186 /* Only used when BRN 44455 or BRN 63027 present. */ 187 struct rogue_fwif_dummy_rgnhdr_init_geom_regs { 188 uint64_t te_psgregion_addr; 189 }; 190 191 /** 192 * \brief DM command for geometry processing phase of a render/3D operation. 193 * Represents the command data for a ROGUE_FWIF_CCB_CMD_TYPE_GEOM type client 194 * CCB command. 195 * 196 * The Rogue TA can be used to tile a whole scene's objects as per TA behavior 197 * on ROGUE. 198 */ 199 struct rogue_fwif_cmd_ta { 200 /** 201 * rogue_fwif_cmd_ta_3d_shared field must always be at the beginning of the 202 * struct. 203 * 204 * The command struct (rogue_fwif_cmd_ta) is shared between Client and 205 * Firmware. Kernel is unable to perform read/write operations on the 206 * command struct, the SHARED region is the only exception from this rule. 207 * This region must be the first member so that Kernel can easily access it. 208 * For more info, see pvr_cmd_ta_3d definition. 209 */ 210 struct rogue_fwif_cmd_ta_3d_shared cmd_shared; 211 212 alignas(8) struct rogue_fwif_ta_regs regs; 213 alignas(8) uint32_t flags; 214 /** 215 * Holds the TA/3D fence value to allow the 3D partial render command 216 * to go through. 217 */ 218 struct rogue_fwif_ufo partial_render_ta_3d_fence; 219 220 /* Only used when BRN 44455 or BRN 63027 present. */ 221 alignas(8) struct rogue_fwif_dummy_rgnhdr_init_geom_regs 222 dummy_rgnhdr_init_geom_regs; 223 224 /* Only used when BRN 61484 or BRN 66333 present. */ 225 uint32_t brn61484_66333_live_rt; 226 227 uint32_t padding; 228 }; 229 230 static_assert( 231 offsetof(struct rogue_fwif_cmd_ta, cmd_shared) == 0U, 232 "rogue_fwif_cmd_ta_3d_shared must be the first member of rogue_fwif_cmd_ta"); 233 234 static_assert( 235 sizeof(struct rogue_fwif_cmd_ta) <= ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 236 "kernel expects command size be increased to match current TA command size"); 237 238 /** 239 * \brief Configuration registers which need to be loaded by the firmware before 240 * ISP can be started. 241 */ 242 struct rogue_fwif_3d_regs { 243 /** 244 * All 32 bit values should be added in the top section. This then requires 245 * only a single alignas(8) to align all the 64 bit values in the second 246 * section. 247 */ 248 uint32_t usc_pixel_output_ctrl; 249 250 #define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U 251 uint32_t usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL]; 252 253 uint32_t isp_bgobjdepth; 254 uint32_t isp_bgobjvals; 255 uint32_t isp_aa; 256 /* Only used when feature S7_TOP_INFRASTRUCTURE present. */ 257 uint32_t isp_xtp_pipe_enable; 258 259 uint32_t isp_ctl; 260 261 /* Only used when feature CLUSTER_GROUPING present. */ 262 uint32_t tpu; 263 264 uint32_t event_pixel_pds_info; 265 266 uint32_t pixel_phantom; 267 268 uint32_t view_idx; 269 270 uint32_t event_pixel_pds_data; 271 272 /* Only used when BRN 65101 present. */ 273 uint32_t brn65101_event_pixel_pds_data; 274 275 /* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */ 276 uint32_t isp_oclqry_stride; 277 278 /* Only used when feature ZLS_SUBTILE present. */ 279 uint32_t isp_zls_pixels; 280 281 /* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */ 282 uint32_t rgx_cr_blackpearl_fix; 283 284 /* All values below the alignas(8) must be 64 bit. */ 285 alignas(8) uint64_t isp_scissor_base; 286 uint64_t isp_dbias_base; 287 uint64_t isp_oclqry_base; 288 uint64_t isp_zlsctl; 289 uint64_t isp_zload_store_base; 290 uint64_t isp_stencil_load_store_base; 291 292 /* 293 * Only used when feature FBCDC_ALGORITHM present and value < 3 or feature 294 * FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must 295 * not be present. 296 */ 297 uint64_t fb_cdc_zls; 298 299 #define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U 300 uint64_t pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS]; 301 uint64_t tpu_border_colour_table; 302 uint64_t pds_bgnd[3U]; 303 304 /* Only used when BRN 65101 present. */ 305 uint64_t pds_bgnd_brn65101[3U]; 306 307 uint64_t pds_pr_bgnd[3U]; 308 309 /* Only used when BRN 62850 or 62865 present. */ 310 uint64_t isp_dummy_stencil_store_base; 311 312 /* Only used when BRN 66193 present. */ 313 uint64_t isp_dummy_depth_store_base; 314 315 /* Only used when BRN 67182 present. */ 316 uint32_t rgnhdr_single_rt_size; 317 /* Only used when BRN 67182 present. */ 318 uint32_t rgnhdr_scratch_offset; 319 }; 320 321 /** 322 * \brief DM command for fragment processing phase of a render/3D operation. 323 * Represents the command data for a ROGUE_FWIF_CCB_CMD_TYPE_FRAG type client 324 * CCB command. 325 */ 326 struct rogue_fwif_cmd_3d { 327 /** 328 * This struct is shared between Client and Firmware. 329 * Kernel is unable to perform read/write operations on the command struct, 330 * the SHARED region is our only exception from that rule. 331 * This region must be the first member so Kernel can easily access it. 332 * For more info, see rogue_fwif_cmd_ta_3d_shared definition. 333 */ 334 alignas(8) struct rogue_fwif_cmd_ta_3d_shared cmd_shared; 335 336 alignas(8) struct rogue_fwif_3d_regs regs; 337 /** command control flags. */ 338 uint32_t flags; 339 /** Stride IN BYTES for Z-Buffer in case of RTAs. */ 340 uint32_t zls_stride; 341 /** Stride IN BYTES for S-Buffer in case of RTAs. */ 342 uint32_t sls_stride; 343 344 /* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */ 345 uint32_t execute_count; 346 347 uint32_t padding; 348 }; 349 350 static_assert( 351 offsetof(struct rogue_fwif_cmd_3d, cmd_shared) == 0U, 352 "rogue_fwif_cmd_ta_3d_shared must be the first member of rogue_fwif_cmd_3d"); 353 354 static_assert( 355 sizeof(struct rogue_fwif_cmd_3d) <= ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 356 "kernel expects command size be increased to match current 3D command size"); 357 358 struct rogue_fwif_transfer_regs { 359 /** 360 * All 32 bit values should be added in the top section. This then requires 361 * only a single alignas(8) to align all the 8 byte values in the second 362 * section. 363 */ 364 uint32_t isp_bgobjvals; 365 366 uint32_t usc_pixel_output_ctrl; 367 uint32_t usc_clear_register0; 368 uint32_t usc_clear_register1; 369 uint32_t usc_clear_register2; 370 uint32_t usc_clear_register3; 371 372 uint32_t isp_mtile_size; 373 uint32_t isp_render_origin; 374 uint32_t isp_ctl; 375 376 /* Only used when feature S7_TOP_INFRASTRUCTURE present. */ 377 uint32_t isp_xtp_pipe_enable; 378 uint32_t isp_aa; 379 380 uint32_t event_pixel_pds_info; 381 382 uint32_t event_pixel_pds_code; 383 uint32_t event_pixel_pds_data; 384 385 uint32_t isp_render; 386 uint32_t isp_rgn; 387 388 /* Only used when feature GPU_MULTICORE_SUPPORT present. */ 389 uint32_t frag_screen; 390 391 /** All values below the alignas(8) must be 64 bit. */ 392 alignas(8) uint64_t pds_bgnd0_base; 393 uint64_t pds_bgnd1_base; 394 uint64_t pds_bgnd3_sizeinfo; 395 396 uint64_t isp_mtile_base; 397 /* TQ_MAX_RENDER_TARGETS * PBE_STATE_SIZE */ 398 #define ROGUE_PBE_WORDS_REQUIRED_FOR_TQS 3 399 uint64_t pbe_wordx_mrty[PVR_TRANSFER_MAX_RENDER_TARGETS * 400 ROGUE_PBE_WORDS_REQUIRED_FOR_TQS]; 401 }; 402 403 /** 404 * \brief DM command for TQ/2D operation. Represents the command data for a 405 * ROGUE_FWIF_CCB_CMD_TYPE_TQ_3D type client CCB command. 406 */ 407 struct rogue_fwif_cmd_transfer { 408 alignas(8) struct rogue_fwif_cmd_common cmn; 409 alignas(8) struct rogue_fwif_transfer_regs regs; 410 411 uint32_t flags; 412 413 uint32_t padding; 414 }; 415 416 static_assert( 417 offsetof(struct rogue_fwif_cmd_transfer, cmn) == 0U, 418 "rogue_fwif_cmd_common must be the first member of rogue_fwif_cmd_transfer"); 419 420 static_assert( 421 sizeof(struct rogue_fwif_cmd_transfer) <= 422 ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 423 "kernel expects command size be increased to match current TRANSFER command size"); 424 425 struct rogue_fwif_2d_regs { 426 uint64_t tla_cmd_stream; 427 uint64_t deprecated_0; 428 uint64_t deprecated_1; 429 uint64_t deprecated_2; 430 uint64_t deprecated_3; 431 uint64_t brn57193_tla_cmd_stream; 432 }; 433 434 struct rogue_fwif_cmd_2d { 435 alignas(8) struct rogue_fwif_cmd_common cmn; 436 alignas(8) struct rogue_fwif_2d_regs regs; 437 438 uint32_t flags; 439 }; 440 441 static_assert( 442 offsetof(struct rogue_fwif_cmd_2d, cmn) == 0U, 443 "rogue_fwif_cmd_common must be the first member of rogue_fwif_cmd_2d"); 444 445 static_assert( 446 sizeof(struct rogue_fwif_cmd_2d) <= ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 447 "kernel expects command size be increased to match current 2D command size"); 448 449 /** Command to handle aborts. */ 450 struct rogue_fwif_cmd_abort { 451 alignas(8) struct rogue_fwif_cmd_ta_3d_shared cmd_shared; 452 }; 453 454 /*********************************************** 455 Host interface structures. 456 ***********************************************/ 457 458 /** 459 * Configuration registers which need to be loaded by the firmware before CDM 460 * can be started. 461 */ 462 struct rogue_fwif_cdm_regs { 463 uint64_t tpu_border_colour_table; 464 465 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 466 uint64_t cdm_cb_queue; 467 468 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 469 uint64_t cdm_cb_base; 470 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 471 uint64_t cdm_cb; 472 473 /* Only used when feature CDM_USER_MODE_QUEUE is not present. */ 474 uint64_t cdm_ctrl_stream_base; 475 476 uint64_t cdm_context_state_base_addr; 477 478 /* Only used when BRN 49927 is present. */ 479 uint32_t tpu; 480 481 uint32_t cdm_resume_pds1; 482 483 /* Only used when feature COMPUTE_MORTON_CAPABLE present. */ 484 uint32_t cdm_item; 485 486 /* Only used when feature CLUSTER_GROUPING present. */ 487 uint32_t compute_cluster; 488 489 /* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */ 490 uint32_t tpu_tag_cdm_ctrl; 491 492 uint32_t padding; 493 }; 494 495 /** 496 * \brief DM command for Compute operation. Represents the command data for a 497 * ROGUE_FWIF_CCB_CMD_TYPE_CDM type client CCB command. 498 * 499 * Rouge Compute command. 500 */ 501 struct rogue_fwif_cmd_compute { 502 alignas(8) struct rogue_fwif_cmd_common cmn; 503 alignas(8) struct rogue_fwif_cdm_regs regs; 504 alignas(8) uint32_t flags; 505 506 /* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */ 507 uint32_t num_temp_regions; 508 509 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 510 uint32_t stream_start_offset; 511 512 /* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */ 513 /* Only used when feature GPU_MULTICORE_SUPPORT present. */ 514 uint32_t execute_count; 515 }; 516 517 static_assert( 518 offsetof(struct rogue_fwif_cmd_compute, cmn) == 0U, 519 "rogue_fwif_cmd_common must be the first member of rogue_fwif_cmd_compute"); 520 521 static_assert( 522 sizeof(struct rogue_fwif_cmd_compute) <= 523 ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 524 "kernel expects command size be increased to match current COMPUTE command size"); 525 526 /* TODO: Rename the RGX_* macros in the comments once they are imported. */ 527 /* Applied to RGX_CR_VDM_SYNC_PDS_DATA_BASE. */ 528 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_VDM_SYNC_OFFSET_BYTES 0U 529 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_VDM_SYNC_MAX_SIZE_BYTES 128U 530 531 /** Applied to RGX_CR_EVENT_PIXEL_PDS_CODE. */ 532 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_EOT_OFFSET_BYTES 128U 533 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_EOT_MAX_SIZE_BYTES 128U 534 535 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_TOTAL_BYTES 4096U 536 537 /** Pointed to by PDS code at RGX_CR_VDM_SYNC_PDS_DATA_BASE. */ 538 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_USC_HEAP_VDM_SYNC_OFFSET_BYTES 0U 539 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_USC_HEAP_VDM_SYNC_MAX_SIZE_BYTES 128U 540 541 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_USC_HEAP_TOTAL_BYTES 4096U 542 543 /** 544 * Applied to RGX_CR_MCU_FENCE, and RGX_CR_PM_MTILE_ARRAY 545 * (defined(RGX_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT)). 546 */ 547 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_FENCE_OFFSET_BYTES 0U 548 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_FENCE_MAX_SIZE_BYTES 128U 549 550 /** Applied to RGX_CR_TPU_YUV_CSC_COEFFICIENTS. */ 551 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_YUV_CSC_OFFSET_BYTES 128U 552 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_YUV_CSC_MAX_SIZE_BYTES 1024U 553 554 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_TOTAL_BYTES 4096U 555 556 #endif /* PVR_ROGUE_FWIF_H */ 557