1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #include <type_support.h> 8 9 //CSI reveiver has 3 ports. 10 #define N_CSI_PORTS (3) 11 //AM: Use previous define for this. 12 13 //MIPI allows up to 4 channels. 14 #define N_CHANNELS (4) 15 // 12KB = 256bit x 384 words 16 #define IB_CAPACITY_IN_WORDS (384) 17 18 typedef enum { 19 MIPI_0LANE_CFG = 0, 20 MIPI_1LANE_CFG = 1, 21 MIPI_2LANE_CFG = 2, 22 MIPI_3LANE_CFG = 3, 23 MIPI_4LANE_CFG = 4 24 } mipi_lane_cfg_t; 25 26 typedef enum { 27 INPUT_SYSTEM_SOURCE_SENSOR = 0, 28 INPUT_SYSTEM_SOURCE_FIFO, 29 INPUT_SYSTEM_SOURCE_PRBS, 30 INPUT_SYSTEM_SOURCE_MEMORY, 31 N_INPUT_SYSTEM_SOURCE 32 } input_system_source_t; 33 34 /* internal routing configuration */ 35 typedef enum { 36 INPUT_SYSTEM_DISCARD_ALL = 0, 37 INPUT_SYSTEM_CSI_BACKEND = 1, 38 INPUT_SYSTEM_INPUT_BUFFER = 2, 39 INPUT_SYSTEM_MULTICAST = 3, 40 N_INPUT_SYSTEM_CONNECTION 41 } input_system_connection_t; 42 43 typedef enum { 44 INPUT_SYSTEM_MIPI_PORT0, 45 INPUT_SYSTEM_MIPI_PORT1, 46 INPUT_SYSTEM_MIPI_PORT2, 47 INPUT_SYSTEM_ACQUISITION_UNIT, 48 N_INPUT_SYSTEM_MULTIPLEX 49 } input_system_multiplex_t; 50 51 typedef enum { 52 INPUT_SYSTEM_SINK_MEMORY = 0, 53 INPUT_SYSTEM_SINK_ISP, 54 INPUT_SYSTEM_SINK_SP, 55 N_INPUT_SYSTEM_SINK 56 } input_system_sink_t; 57 58 typedef enum { 59 INPUT_SYSTEM_FIFO_CAPTURE = 0, 60 INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING, 61 INPUT_SYSTEM_SRAM_BUFFERING, 62 INPUT_SYSTEM_XMEM_BUFFERING, 63 INPUT_SYSTEM_XMEM_CAPTURE, 64 INPUT_SYSTEM_XMEM_ACQUIRE, 65 N_INPUT_SYSTEM_BUFFERING_MODE 66 } buffering_mode_t; 67 68 typedef struct isp2400_input_system_cfg_s input_system_cfg_t; 69 typedef struct sync_generator_cfg_s sync_generator_cfg_t; 70 typedef struct tpg_cfg_s tpg_cfg_t; 71 typedef struct prbs_cfg_s prbs_cfg_t; 72 73 /* MW: uint16_t should be sufficient */ 74 struct isp2400_input_system_cfg_s { 75 u32 no_side_band; 76 u32 fmt_type; 77 u32 ch_id; 78 u32 input_mode; 79 }; 80 81 struct sync_generator_cfg_s { 82 u32 width; 83 u32 height; 84 u32 hblank_cycles; 85 u32 vblank_cycles; 86 }; 87 88 /* MW: tpg & prbs are exclusive */ 89 struct tpg_cfg_s { 90 u32 x_mask; 91 u32 y_mask; 92 u32 x_delta; 93 u32 y_delta; 94 u32 xy_mask; 95 sync_generator_cfg_t sync_gen_cfg; 96 }; 97 98 struct prbs_cfg_s { 99 u32 seed; 100 sync_generator_cfg_t sync_gen_cfg; 101 }; 102 103 struct gpfifo_cfg_s { 104 // TBD. 105 sync_generator_cfg_t sync_gen_cfg; 106 }; 107 108 typedef struct gpfifo_cfg_s gpfifo_cfg_t; 109 110 //ALX:Commented out to pass the compilation. 111 //typedef struct isp2400_input_system_cfg_s input_system_cfg_t; 112 113 struct ib_buffer_s { 114 u32 mem_reg_size; 115 u32 nof_mem_regs; 116 u32 mem_reg_addr; 117 }; 118 119 typedef struct ib_buffer_s isp2400_ib_buffer_t; 120 121 struct csi_cfg_s { 122 u32 csi_port; 123 buffering_mode_t buffering_mode; 124 isp2400_ib_buffer_t csi_buffer; 125 isp2400_ib_buffer_t acquisition_buffer; 126 u32 nof_xmem_buffers; 127 }; 128 129 typedef struct csi_cfg_s csi_cfg_t; 130 131 typedef enum { 132 INPUT_SYSTEM_CFG_FLAG_RESET = 0, 133 INPUT_SYSTEM_CFG_FLAG_SET = 1U << 0, 134 INPUT_SYSTEM_CFG_FLAG_BLOCKED = 1U << 1, 135 INPUT_SYSTEM_CFG_FLAG_REQUIRED = 1U << 2, 136 INPUT_SYSTEM_CFG_FLAG_CONFLICT = 1U << 3 // To mark a conflicting configuration. 137 } isp2400_input_system_cfg_flag_t; 138 139 typedef u32 input_system_config_flags_t; 140