1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <[email protected]>
25 *
26 */
27
28 #ifndef BRW_FS_H
29 #define BRW_FS_H
30
31 #include "brw_cfg.h"
32 #include "brw_compiler.h"
33 #include "brw_ir_allocator.h"
34 #include "brw_ir_fs.h"
35 #include "brw_fs_live_variables.h"
36 #include "brw_ir_performance.h"
37 #include "compiler/nir/nir.h"
38
39 struct bblock_t;
40 namespace {
41 struct acp_entry;
42 }
43
44 struct fs_visitor;
45
46 namespace brw {
47 /**
48 * Register pressure analysis of a shader. Estimates how many registers
49 * are live at any point of the program in GRF units.
50 */
51 struct register_pressure {
52 register_pressure(const fs_visitor *v);
53 ~register_pressure();
54
55 analysis_dependency_class
dependency_classregister_pressure56 dependency_class() const
57 {
58 return (DEPENDENCY_INSTRUCTION_IDENTITY |
59 DEPENDENCY_INSTRUCTION_DATA_FLOW |
60 DEPENDENCY_VARIABLES);
61 }
62
63 bool
validateregister_pressure64 validate(const fs_visitor *) const
65 {
66 /* FINISHME */
67 return true;
68 }
69
70 unsigned *regs_live_at_ip;
71 };
72
73 class def_analysis {
74 public:
75 def_analysis(const fs_visitor *v);
76 ~def_analysis();
77
78 fs_inst *
get(const brw_reg & reg)79 get(const brw_reg ®) const
80 {
81 return reg.file == VGRF && reg.nr < def_count ?
82 def_insts[reg.nr] : NULL;
83 }
84
85 bblock_t *
get_block(const brw_reg & reg)86 get_block(const brw_reg ®) const
87 {
88 return reg.file == VGRF && reg.nr < def_count ?
89 def_blocks[reg.nr] : NULL;
90 }
91
92 uint32_t
get_use_count(const brw_reg & reg)93 get_use_count(const brw_reg ®) const
94 {
95 return reg.file == VGRF && reg.nr < def_count ?
96 def_use_counts[reg.nr] : 0;
97 }
98
count()99 unsigned count() const { return def_count; }
100
101 void print_stats(const fs_visitor *) const;
102
103 analysis_dependency_class
dependency_class()104 dependency_class() const
105 {
106 return DEPENDENCY_INSTRUCTION_IDENTITY |
107 DEPENDENCY_INSTRUCTION_DATA_FLOW |
108 DEPENDENCY_VARIABLES |
109 DEPENDENCY_BLOCKS;
110 }
111
112 bool validate(const fs_visitor *) const;
113
114 private:
115 void mark_invalid(int);
116 bool fully_defines(const fs_visitor *v, fs_inst *);
117 void update_for_reads(const idom_tree &idom, bblock_t *block, fs_inst *);
118 void update_for_write(const fs_visitor *v, bblock_t *block, fs_inst *);
119
120 fs_inst **def_insts;
121 bblock_t **def_blocks;
122 uint32_t *def_use_counts;
123 unsigned def_count;
124 };
125 }
126
127 #define UBO_START ((1 << 16) - 4)
128
129 /**
130 * Scratch data used when compiling a GLSL geometry shader.
131 */
132 struct brw_gs_compile
133 {
134 struct brw_gs_prog_key key;
135 struct intel_vue_map input_vue_map;
136
137 unsigned control_data_bits_per_vertex;
138 unsigned control_data_header_size_bits;
139 };
140
141 namespace brw {
142 class fs_builder;
143 }
144
145 struct shader_stats {
146 const char *scheduler_mode;
147 unsigned promoted_constants;
148 unsigned spill_count;
149 unsigned fill_count;
150 unsigned max_register_pressure;
151 };
152
153 /** Register numbers for thread payload fields. */
154 struct thread_payload {
155 /** The number of thread payload registers the hardware will supply. */
156 uint8_t num_regs;
157
158 virtual ~thread_payload() = default;
159
160 protected:
thread_payloadthread_payload161 thread_payload() : num_regs() {}
162 };
163
164 struct vs_thread_payload : public thread_payload {
165 vs_thread_payload(const fs_visitor &v);
166
167 brw_reg urb_handles;
168 };
169
170 struct tcs_thread_payload : public thread_payload {
171 tcs_thread_payload(const fs_visitor &v);
172
173 brw_reg patch_urb_output;
174 brw_reg primitive_id;
175 brw_reg icp_handle_start;
176 };
177
178 struct tes_thread_payload : public thread_payload {
179 tes_thread_payload(const fs_visitor &v);
180
181 brw_reg patch_urb_input;
182 brw_reg primitive_id;
183 brw_reg coords[3];
184 brw_reg urb_output;
185 };
186
187 struct gs_thread_payload : public thread_payload {
188 gs_thread_payload(fs_visitor &v);
189
190 brw_reg urb_handles;
191 brw_reg primitive_id;
192 brw_reg instance_id;
193 brw_reg icp_handle_start;
194 };
195
196 struct fs_thread_payload : public thread_payload {
197 fs_thread_payload(const fs_visitor &v,
198 bool &source_depth_to_render_target);
199
200 uint8_t subspan_coord_reg[2];
201 uint8_t source_depth_reg[2];
202 uint8_t source_w_reg[2];
203 uint8_t aa_dest_stencil_reg[2];
204 uint8_t dest_depth_reg[2];
205 uint8_t sample_pos_reg[2];
206 uint8_t sample_mask_in_reg[2];
207 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
208
209 uint8_t depth_w_coef_reg;
210 uint8_t pc_bary_coef_reg;
211 uint8_t npc_bary_coef_reg;
212 uint8_t sample_offsets_reg;
213 };
214
215 struct cs_thread_payload : public thread_payload {
216 cs_thread_payload(const fs_visitor &v);
217
218 void load_subgroup_id(const brw::fs_builder &bld, brw_reg &dest) const;
219
220 brw_reg local_invocation_id[3];
221
222 protected:
223 brw_reg subgroup_id_;
224 };
225
226 struct task_mesh_thread_payload : public cs_thread_payload {
227 task_mesh_thread_payload(fs_visitor &v);
228
229 brw_reg extended_parameter_0;
230 brw_reg local_index;
231 brw_reg inline_parameter;
232
233 brw_reg urb_output;
234
235 /* URB to read Task memory inputs. Only valid for MESH stage. */
236 brw_reg task_urb_input;
237 };
238
239 struct bs_thread_payload : public thread_payload {
240 bs_thread_payload(const fs_visitor &v);
241
242 brw_reg global_arg_ptr;
243 brw_reg local_arg_ptr;
244
245 void load_shader_type(const brw::fs_builder &bld, brw_reg &dest) const;
246 };
247
248 enum instruction_scheduler_mode {
249 SCHEDULE_PRE,
250 SCHEDULE_PRE_NON_LIFO,
251 SCHEDULE_PRE_LIFO,
252 SCHEDULE_POST,
253 SCHEDULE_NONE,
254 };
255
256 class instruction_scheduler;
257
258 /**
259 * The fragment shader front-end.
260 *
261 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
262 */
263 struct fs_visitor
264 {
265 public:
266 fs_visitor(const struct brw_compiler *compiler,
267 const struct brw_compile_params *params,
268 const brw_base_prog_key *key,
269 struct brw_stage_prog_data *prog_data,
270 const nir_shader *shader,
271 unsigned dispatch_width,
272 bool needs_register_pressure,
273 bool debug_enabled);
274 fs_visitor(const struct brw_compiler *compiler,
275 const struct brw_compile_params *params,
276 const brw_wm_prog_key *key,
277 struct brw_wm_prog_data *prog_data,
278 const nir_shader *shader,
279 unsigned dispatch_width,
280 unsigned num_polygons,
281 bool needs_register_pressure,
282 bool debug_enabled);
283 fs_visitor(const struct brw_compiler *compiler,
284 const struct brw_compile_params *params,
285 struct brw_gs_compile *gs_compile,
286 struct brw_gs_prog_data *prog_data,
287 const nir_shader *shader,
288 bool needs_register_pressure,
289 bool debug_enabled);
290 void init();
291 ~fs_visitor();
292
293 void import_uniforms(fs_visitor *v);
294
295 void assign_curb_setup();
296 void convert_attr_sources_to_hw_regs(fs_inst *inst);
297 void calculate_payload_ranges(bool allow_spilling,
298 unsigned payload_node_count,
299 int *payload_last_use_ip) const;
300 void assign_constant_locations();
301 bool get_pull_locs(const brw_reg &src, unsigned *out_surf_index,
302 unsigned *out_pull_index);
303 void invalidate_analysis(brw::analysis_dependency_class c);
304
305 void vfail(const char *msg, va_list args);
306 void fail(const char *msg, ...);
307 void limit_dispatch_width(unsigned n, const char *msg);
308
309 void emit_urb_writes(const brw_reg &gs_vertex_count = brw_reg());
310 void emit_gs_control_data_bits(const brw_reg &vertex_count);
311 brw_reg gs_urb_channel_mask(const brw_reg &dword_index);
312 brw_reg gs_urb_per_slot_dword_index(const brw_reg &vertex_count);
313 bool mark_last_urb_write_with_eot();
314 void emit_cs_terminate();
315
316 const struct brw_compiler *compiler;
317 void *log_data; /* Passed to compiler->*_log functions */
318
319 const struct intel_device_info * const devinfo;
320 const nir_shader *nir;
321
322 /** ralloc context for temporary data used during compile */
323 void *mem_ctx;
324
325 /** List of fs_inst. */
326 exec_list instructions;
327
328 cfg_t *cfg;
329
330 gl_shader_stage stage;
331 bool debug_enabled;
332
333 brw::simple_allocator alloc;
334
335 const brw_base_prog_key *const key;
336
337 struct brw_gs_compile *gs_compile;
338
339 struct brw_stage_prog_data *prog_data;
340
341 brw_analysis<brw::fs_live_variables, fs_visitor> live_analysis;
342 brw_analysis<brw::register_pressure, fs_visitor> regpressure_analysis;
343 brw_analysis<brw::performance, fs_visitor> performance_analysis;
344 brw_analysis<brw::idom_tree, fs_visitor> idom_analysis;
345 brw_analysis<brw::def_analysis, fs_visitor> def_analysis;
346
347 /** Number of uniform variable components visited. */
348 unsigned uniforms;
349
350 /** Byte-offset for the next available spot in the scratch space buffer. */
351 unsigned last_scratch;
352
353 /**
354 * Array mapping UNIFORM register numbers to the push parameter index,
355 * or -1 if this uniform register isn't being uploaded as a push constant.
356 */
357 int *push_constant_loc;
358
359 brw_reg frag_depth;
360 brw_reg frag_stencil;
361 brw_reg sample_mask;
362 brw_reg outputs[VARYING_SLOT_MAX];
363 brw_reg dual_src_output;
364 int first_non_payload_grf;
365
366 bool failed;
367 char *fail_msg;
368
369 thread_payload *payload_;
370
payloadfs_visitor371 thread_payload &payload() {
372 return *this->payload_;
373 }
374
vs_payloadfs_visitor375 vs_thread_payload &vs_payload() {
376 assert(stage == MESA_SHADER_VERTEX);
377 return *static_cast<vs_thread_payload *>(this->payload_);
378 }
379
tcs_payloadfs_visitor380 tcs_thread_payload &tcs_payload() {
381 assert(stage == MESA_SHADER_TESS_CTRL);
382 return *static_cast<tcs_thread_payload *>(this->payload_);
383 }
384
tes_payloadfs_visitor385 tes_thread_payload &tes_payload() {
386 assert(stage == MESA_SHADER_TESS_EVAL);
387 return *static_cast<tes_thread_payload *>(this->payload_);
388 }
389
gs_payloadfs_visitor390 gs_thread_payload &gs_payload() {
391 assert(stage == MESA_SHADER_GEOMETRY);
392 return *static_cast<gs_thread_payload *>(this->payload_);
393 }
394
fs_payloadfs_visitor395 fs_thread_payload &fs_payload() {
396 assert(stage == MESA_SHADER_FRAGMENT);
397 return *static_cast<fs_thread_payload *>(this->payload_);
398 };
399
fs_payloadfs_visitor400 const fs_thread_payload &fs_payload() const {
401 assert(stage == MESA_SHADER_FRAGMENT);
402 return *static_cast<const fs_thread_payload *>(this->payload_);
403 };
404
cs_payloadfs_visitor405 cs_thread_payload &cs_payload() {
406 assert(gl_shader_stage_uses_workgroup(stage));
407 return *static_cast<cs_thread_payload *>(this->payload_);
408 }
409
task_mesh_payloadfs_visitor410 task_mesh_thread_payload &task_mesh_payload() {
411 assert(stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH);
412 return *static_cast<task_mesh_thread_payload *>(this->payload_);
413 }
414
bs_payloadfs_visitor415 bs_thread_payload &bs_payload() {
416 assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
417 return *static_cast<bs_thread_payload *>(this->payload_);
418 }
419
420 bool source_depth_to_render_target;
421
422 brw_reg pixel_x;
423 brw_reg pixel_y;
424 brw_reg pixel_z;
425 brw_reg wpos_w;
426 brw_reg pixel_w;
427 brw_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
428 brw_reg final_gs_vertex_count;
429 brw_reg control_data_bits;
430 brw_reg invocation_id;
431
432 unsigned grf_used;
433 bool spilled_any_registers;
434 bool needs_register_pressure;
435
436 const unsigned dispatch_width; /**< 8, 16 or 32 */
437 const unsigned max_polygons;
438 unsigned max_dispatch_width;
439
440 /* The API selected subgroup size */
441 unsigned api_subgroup_size; /**< 0, 8, 16, 32 */
442
443 struct shader_stats shader_stats;
444
445 void debug_optimizer(const nir_shader *nir,
446 const char *pass_name,
447 int iteration, int pass_num) const;
448 };
449
450 void brw_print_instruction_to_file(const fs_visitor &s, const fs_inst *inst, FILE *file, const brw::def_analysis *defs);
451 void brw_print_instructions_to_file(const fs_visitor &s, FILE *file);
452
453 /* Convenience functions based on the above. */
454 inline void brw_print_instruction(const fs_visitor &s, const fs_inst *inst, FILE *file = stderr, const brw::def_analysis *defs = nullptr) {
455 brw_print_instruction_to_file(s, inst, file, defs);
456 }
457 void brw_print_instructions(const fs_visitor &s, const char *name = nullptr);
458
459 void brw_print_swsb(FILE *f, const struct intel_device_info *devinfo, const tgl_swsb swsb);
460
461 /**
462 * Return the flag register used in fragment shaders to keep track of live
463 * samples. On Gfx7+ we use f1.0-f1.1 to allow discard jumps in SIMD32
464 * dispatch mode.
465 */
466 static inline unsigned
sample_mask_flag_subreg(const fs_visitor & s)467 sample_mask_flag_subreg(const fs_visitor &s)
468 {
469 assert(s.stage == MESA_SHADER_FRAGMENT);
470 return 2;
471 }
472
473 /**
474 * The fragment shader code generator.
475 *
476 * Translates FS IR to actual i965 assembly code.
477 */
478 class fs_generator
479 {
480 public:
481 fs_generator(const struct brw_compiler *compiler,
482 const struct brw_compile_params *params,
483 struct brw_stage_prog_data *prog_data,
484 gl_shader_stage stage);
485 ~fs_generator();
486
487 void enable_debug(const char *shader_name);
488 int generate_code(const cfg_t *cfg, int dispatch_width,
489 struct shader_stats shader_stats,
490 const brw::performance &perf,
491 struct brw_compile_stats *stats,
492 unsigned max_polygons = 0);
493 void add_const_data(void *data, unsigned size);
494 void add_resume_sbt(unsigned num_resume_shaders, uint64_t *sbt);
495 const unsigned *get_assembly();
496
497 private:
498 void generate_send(fs_inst *inst,
499 struct brw_reg dst,
500 struct brw_reg desc,
501 struct brw_reg ex_desc,
502 struct brw_reg payload,
503 struct brw_reg payload2);
504 void generate_barrier(fs_inst *inst, struct brw_reg src);
505 void generate_ddx(const fs_inst *inst,
506 struct brw_reg dst, struct brw_reg src);
507 void generate_ddy(const fs_inst *inst,
508 struct brw_reg dst, struct brw_reg src);
509 void generate_scratch_header(fs_inst *inst,
510 struct brw_reg dst, struct brw_reg src);
511
512 void generate_halt(fs_inst *inst);
513
514 void generate_mov_indirect(fs_inst *inst,
515 struct brw_reg dst,
516 struct brw_reg reg,
517 struct brw_reg indirect_byte_offset);
518
519 void generate_shuffle(fs_inst *inst,
520 struct brw_reg dst,
521 struct brw_reg src,
522 struct brw_reg idx);
523
524 void generate_quad_swizzle(const fs_inst *inst,
525 struct brw_reg dst, struct brw_reg src,
526 unsigned swiz);
527
528 bool patch_halt_jumps();
529
530 const struct brw_compiler *compiler;
531 const struct brw_compile_params *params;
532
533 const struct intel_device_info *devinfo;
534
535 struct brw_codegen *p;
536 struct brw_stage_prog_data * const prog_data;
537
538 unsigned dispatch_width; /**< 8, 16 or 32 */
539
540 exec_list discard_halt_patches;
541 bool debug_flag;
542 const char *shader_name;
543 gl_shader_stage stage;
544 void *mem_ctx;
545 };
546
547 namespace brw {
548 brw_reg
549 fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
550 brw_reg_type type = BRW_TYPE_F,
551 unsigned n = 1);
552
553 brw_reg
554 fetch_barycentric_reg(const brw::fs_builder &bld, uint8_t regs[2]);
555
556 inline brw_reg
dynamic_msaa_flags(const struct brw_wm_prog_data * wm_prog_data)557 dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data)
558 {
559 return brw_uniform_reg(wm_prog_data->msaa_flags_param, BRW_TYPE_UD);
560 }
561
562 void
563 check_dynamic_msaa_flag(const fs_builder &bld,
564 const struct brw_wm_prog_data *wm_prog_data,
565 enum intel_msaa_flags flag);
566
567 bool
568 lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
569 }
570
571 void shuffle_from_32bit_read(const brw::fs_builder &bld,
572 const brw_reg &dst,
573 const brw_reg &src,
574 uint32_t first_component,
575 uint32_t components);
576
577 enum brw_barycentric_mode brw_barycentric_mode(const struct brw_wm_prog_key *key,
578 nir_intrinsic_instr *intr);
579
580 uint32_t brw_fb_write_msg_control(const fs_inst *inst,
581 const struct brw_wm_prog_data *prog_data);
582
583 void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data);
584
585 bool brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width);
586
587 brw_reg brw_sample_mask_reg(const brw::fs_builder &bld);
588 void brw_emit_predicate_on_sample_mask(const brw::fs_builder &bld, fs_inst *inst);
589
590 int brw_get_subgroup_id_param_index(const intel_device_info *devinfo,
591 const brw_stage_prog_data *prog_data);
592
593 void nir_to_brw(fs_visitor *s);
594
595 #ifndef NDEBUG
596 void brw_fs_validate(const fs_visitor &s);
597 #else
brw_fs_validate(const fs_visitor & s)598 static inline void brw_fs_validate(const fs_visitor &s) {}
599 #endif
600
601 void brw_calculate_cfg(fs_visitor &s);
602
603 void brw_fs_optimize(fs_visitor &s);
604
605 instruction_scheduler *brw_prepare_scheduler(fs_visitor &s, void *mem_ctx);
606 void brw_schedule_instructions_pre_ra(fs_visitor &s, instruction_scheduler *sched,
607 instruction_scheduler_mode mode);
608 void brw_schedule_instructions_post_ra(fs_visitor &s);
609
610 void brw_allocate_registers(fs_visitor &s, bool allow_spilling);
611 bool brw_assign_regs(fs_visitor &s, bool allow_spilling, bool spill_all);
612 void brw_assign_regs_trivial(fs_visitor &s);
613
614 bool brw_fs_lower_3src_null_dest(fs_visitor &s);
615 bool brw_fs_lower_alu_restrictions(fs_visitor &s);
616 bool brw_fs_lower_barycentrics(fs_visitor &s);
617 bool brw_fs_lower_constant_loads(fs_visitor &s);
618 bool brw_fs_lower_derivatives(fs_visitor &s);
619 bool brw_fs_lower_dpas(fs_visitor &s);
620 bool brw_fs_lower_find_live_channel(fs_visitor &s);
621 bool brw_fs_lower_integer_multiplication(fs_visitor &s);
622 bool brw_fs_lower_load_subgroup_invocation(fs_visitor &s);
623 bool brw_fs_lower_indirect_mov(fs_visitor &s);
624 bool brw_fs_lower_logical_sends(fs_visitor &s);
625 bool brw_fs_lower_pack(fs_visitor &s);
626 bool brw_fs_lower_load_payload(fs_visitor &s);
627 bool brw_fs_lower_regioning(fs_visitor &s);
628 bool brw_fs_lower_scoreboard(fs_visitor &s);
629 bool brw_fs_lower_sends_overlapping_payload(fs_visitor &s);
630 bool brw_fs_lower_simd_width(fs_visitor &s);
631 bool brw_fs_lower_csel(fs_visitor &s);
632 bool brw_fs_lower_sub_sat(fs_visitor &s);
633 bool brw_fs_lower_uniform_pull_constant_loads(fs_visitor &s);
634 void brw_fs_lower_vgrfs_to_fixed_grfs(fs_visitor &s);
635
636 bool brw_fs_opt_algebraic(fs_visitor &s);
637 bool brw_fs_opt_bank_conflicts(fs_visitor &s);
638 bool brw_fs_opt_cmod_propagation(fs_visitor &s);
639 bool brw_fs_opt_combine_constants(fs_visitor &s);
640 bool brw_fs_opt_compact_virtual_grfs(fs_visitor &s);
641 bool brw_fs_opt_copy_propagation(fs_visitor &s);
642 bool brw_fs_opt_copy_propagation_defs(fs_visitor &s);
643 bool brw_fs_opt_cse_defs(fs_visitor &s);
644 bool brw_fs_opt_dead_code_eliminate(fs_visitor &s);
645 bool brw_fs_opt_eliminate_find_live_channel(fs_visitor &s);
646 bool brw_fs_opt_register_coalesce(fs_visitor &s);
647 bool brw_fs_opt_remove_extra_rounding_modes(fs_visitor &s);
648 bool brw_fs_opt_remove_redundant_halts(fs_visitor &s);
649 bool brw_fs_opt_saturate_propagation(fs_visitor &s);
650 bool brw_fs_opt_split_sends(fs_visitor &s);
651 bool brw_fs_opt_split_virtual_grfs(fs_visitor &s);
652 bool brw_fs_opt_zero_samples(fs_visitor &s);
653
654 bool brw_fs_workaround_emit_dummy_mov_instruction(fs_visitor &s);
655 bool brw_fs_workaround_memory_fence_before_eot(fs_visitor &s);
656 bool brw_fs_workaround_nomask_control_flow(fs_visitor &s);
657
658 /* Helpers. */
659 unsigned brw_fs_get_lowered_simd_width(const fs_visitor *shader,
660 const fs_inst *inst);
661
662 #endif /* BRW_FS_H */
663