1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3
4 #ifndef __SOUNDWIRE_H
5 #define __SOUNDWIRE_H
6
7 #include <linux/bitfield.h>
8 #include <linux/bug.h>
9 #include <linux/completion.h>
10 #include <linux/device.h>
11 #include <linux/irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/lockdep_types.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/mutex.h>
16 #include <linux/types.h>
17 #include <sound/sdca.h>
18
19 struct dentry;
20 struct fwnode_handle;
21
22 struct sdw_bus;
23 struct sdw_slave;
24
25 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
26
27 /* SDW Broadcast Device Number */
28 #define SDW_BROADCAST_DEV_NUM 15
29
30 /* SDW Enumeration Device Number */
31 #define SDW_ENUM_DEV_NUM 0
32
33 /* SDW Group Device Numbers */
34 #define SDW_GROUP12_DEV_NUM 12
35 #define SDW_GROUP13_DEV_NUM 13
36
37 /* SDW Master Device Number, not supported yet */
38 #define SDW_MASTER_DEV_NUM 14
39
40 #define SDW_NUM_DEV_ID_REGISTERS 6
41 /* frame shape defines */
42
43 /*
44 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
45 * fill hole with 0, one more dummy entry is added
46 */
47 #define SDW_FRAME_ROWS 24
48 #define SDW_FRAME_COLS 8
49 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
50
51 #define SDW_FRAME_CTRL_BITS 48
52 #define SDW_MAX_DEVICES 11
53
54 #define SDW_MAX_PORTS 15
55 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1)
56
57 #define SDW_MAX_LANES 8
58
59 enum {
60 SDW_PORT_DIRN_SINK = 0,
61 SDW_PORT_DIRN_SOURCE,
62 SDW_PORT_DIRN_MAX,
63 };
64
65 /*
66 * constants for flow control, ports and transport
67 *
68 * these are bit masks as devices can have multiple capabilities
69 */
70
71 /*
72 * flow modes for SDW port. These can be isochronous, tx controlled,
73 * rx controlled or async
74 */
75 #define SDW_PORT_FLOW_MODE_ISOCH 0
76 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
77 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
78 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
79
80 /* sample packaging for block. It can be per port or per channel */
81 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
82 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
83
84 /**
85 * enum sdw_slave_status - Slave status
86 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
87 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
88 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
89 * @SDW_SLAVE_RESERVED: Reserved for future use
90 */
91 enum sdw_slave_status {
92 SDW_SLAVE_UNATTACHED = 0,
93 SDW_SLAVE_ATTACHED = 1,
94 SDW_SLAVE_ALERT = 2,
95 SDW_SLAVE_RESERVED = 3,
96 };
97
98 /**
99 * enum sdw_clk_stop_type: clock stop operations
100 *
101 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
102 * @SDW_CLK_POST_PREPARE: post clock stop prepare
103 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
104 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
105 */
106 enum sdw_clk_stop_type {
107 SDW_CLK_PRE_PREPARE = 0,
108 SDW_CLK_POST_PREPARE,
109 SDW_CLK_PRE_DEPREPARE,
110 SDW_CLK_POST_DEPREPARE,
111 };
112
113 /**
114 * enum sdw_command_response - Command response as defined by SDW spec
115 * @SDW_CMD_OK: cmd was successful
116 * @SDW_CMD_IGNORED: cmd was ignored
117 * @SDW_CMD_FAIL: cmd was NACKed
118 * @SDW_CMD_TIMEOUT: cmd timedout
119 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
120 *
121 * NOTE: The enum is different than actual Spec as response in the Spec is
122 * combination of ACK/NAK bits
123 *
124 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
125 */
126 enum sdw_command_response {
127 SDW_CMD_OK = 0,
128 SDW_CMD_IGNORED = 1,
129 SDW_CMD_FAIL = 2,
130 SDW_CMD_TIMEOUT = 3,
131 SDW_CMD_FAIL_OTHER = 4,
132 };
133
134 /* block group count enum */
135 enum sdw_dpn_grouping {
136 SDW_BLK_GRP_CNT_1 = 0,
137 SDW_BLK_GRP_CNT_2 = 1,
138 SDW_BLK_GRP_CNT_3 = 2,
139 SDW_BLK_GRP_CNT_4 = 3,
140 };
141
142 /* block packing mode enum */
143 enum sdw_dpn_pkg_mode {
144 SDW_BLK_PKG_PER_PORT = 0,
145 SDW_BLK_PKG_PER_CHANNEL = 1
146 };
147
148 /**
149 * enum sdw_stream_type: data stream type
150 *
151 * @SDW_STREAM_PCM: PCM data stream
152 * @SDW_STREAM_PDM: PDM data stream
153 *
154 * spec doesn't define this, but is used in implementation
155 */
156 enum sdw_stream_type {
157 SDW_STREAM_PCM = 0,
158 SDW_STREAM_PDM = 1,
159 };
160
161 /**
162 * enum sdw_data_direction: Data direction
163 *
164 * @SDW_DATA_DIR_RX: Data into Port
165 * @SDW_DATA_DIR_TX: Data out of Port
166 */
167 enum sdw_data_direction {
168 SDW_DATA_DIR_RX = 0,
169 SDW_DATA_DIR_TX = 1,
170 };
171
172 /**
173 * enum sdw_port_data_mode: Data Port mode
174 *
175 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
176 * and transmitted.
177 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
178 * a pseudo random data pattern that is transferred
179 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
180 * logic 0. The encoding will result in no signal transitions
181 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
182 * logic 1. The encoding will result in signal transitions at every bitslot
183 * owned by this Port
184 */
185 enum sdw_port_data_mode {
186 SDW_PORT_DATA_MODE_NORMAL = 0,
187 SDW_PORT_DATA_MODE_PRBS = 1,
188 SDW_PORT_DATA_MODE_STATIC_0 = 2,
189 SDW_PORT_DATA_MODE_STATIC_1 = 3,
190 };
191
192 /*
193 * SDW properties, defined in MIPI DisCo spec v1.0
194 */
195 enum sdw_clk_stop_reset_behave {
196 SDW_CLK_STOP_KEEP_STATUS = 1,
197 };
198
199 /**
200 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
201 * read
202 * @SDW_P15_READ_IGNORED: Read is ignored
203 * @SDW_P15_CMD_OK: Command is ok
204 */
205 enum sdw_p15_behave {
206 SDW_P15_READ_IGNORED = 0,
207 SDW_P15_CMD_OK = 1,
208 };
209
210 /**
211 * enum sdw_dpn_type - Data port types
212 * @SDW_DPN_FULL: Full Data Port is supported
213 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
214 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
215 * are not implemented.
216 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
217 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
218 */
219 enum sdw_dpn_type {
220 SDW_DPN_FULL = 0,
221 SDW_DPN_SIMPLE = 1,
222 SDW_DPN_REDUCED = 2,
223 };
224
225 /**
226 * enum sdw_clk_stop_mode - Clock Stop modes
227 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
228 * restart
229 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
230 * not capable of continuing operation seamlessly when the clock restarts
231 */
232 enum sdw_clk_stop_mode {
233 SDW_CLK_STOP_MODE0 = 0,
234 SDW_CLK_STOP_MODE1 = 1,
235 };
236
237 /**
238 * struct sdw_dp0_prop - DP0 properties
239 * @words: wordlengths supported
240 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
241 * (inclusive)
242 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
243 * (inclusive)
244 * @num_words: number of wordlengths supported
245 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
246 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
247 * response
248 * @simple_ch_prep_sm: If channel prepare sequence is required
249 * @imp_def_interrupts: If set, each bit corresponds to support for
250 * implementation-defined interrupts
251 * @num_lanes: array size of @lane_list
252 * @lane_list: indicates which Lanes can be used by DP0
253 *
254 * The wordlengths are specified by Spec as max, min AND number of
255 * discrete values, implementation can define based on the wordlengths they
256 * support
257 */
258 struct sdw_dp0_prop {
259 u32 *words;
260 u32 max_word;
261 u32 min_word;
262 u32 num_words;
263 u32 ch_prep_timeout;
264 bool BRA_flow_controlled;
265 bool simple_ch_prep_sm;
266 bool imp_def_interrupts;
267 int num_lanes;
268 u32 *lane_list;
269 };
270
271 /**
272 * struct sdw_dpn_prop - Data Port DPn properties
273 * @num: port number
274 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
275 * (inclusive)
276 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
277 * (inclusive)
278 * @num_words: Number of discrete supported wordlengths
279 * @words: Discrete supported wordlength
280 * @type: Data port type. Full, Simplified or Reduced
281 * @max_grouping: Maximum number of samples that can be grouped together for
282 * a full data port
283 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
284 * @imp_def_interrupts: If set, each bit corresponds to support for
285 * implementation-defined interrupts
286 * @max_ch: Maximum channels supported
287 * @min_ch: Minimum channels supported
288 * @num_channels: Number of discrete channels supported
289 * @num_ch_combinations: Number of channel combinations supported
290 * @channels: Discrete channels supported
291 * @ch_combinations: Channel combinations supported
292 * @lane_list: indicates which Lanes can be used by DPn
293 * @num_lanes: array size of @lane_list
294 * @modes: SDW mode supported
295 * @max_async_buffer: Number of samples that this port can buffer in
296 * asynchronous modes
297 * @port_encoding: Payload Channel Sample encoding schemes supported
298 * @block_pack_mode: Type of block port mode supported
299 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register
300 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
301 * machine
302 */
303 struct sdw_dpn_prop {
304 u32 num;
305 u32 max_word;
306 u32 min_word;
307 u32 num_words;
308 u32 *words;
309 enum sdw_dpn_type type;
310 u32 max_grouping;
311 u32 ch_prep_timeout;
312 u32 imp_def_interrupts;
313 u32 max_ch;
314 u32 min_ch;
315 u32 num_channels;
316 u32 num_ch_combinations;
317 u32 *channels;
318 u32 *ch_combinations;
319 u32 *lane_list;
320 int num_lanes;
321 u32 modes;
322 u32 max_async_buffer;
323 u32 port_encoding;
324 bool block_pack_mode;
325 bool read_only_wordlength;
326 bool simple_ch_prep_sm;
327 };
328
329 /**
330 * struct sdw_slave_prop - SoundWire Slave properties
331 * @dp0_prop: Data Port 0 properties
332 * @src_dpn_prop: Source Data Port N properties
333 * @sink_dpn_prop: Sink Data Port N properties
334 * @mipi_revision: Spec version of the implementation
335 * @wake_capable: Wake-up events are supported
336 * @test_mode_capable: If test mode is supported
337 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
338 * @simple_clk_stop_capable: Simple clock mode is supported
339 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
340 * Machine transitions, in milliseconds
341 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
342 * transitions, in milliseconds
343 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
344 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
345 * @high_PHY_capable: Slave is HighPHY capable
346 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
347 * SCP_AddrPage2
348 * @bank_delay_support: Slave implements bank delay/bridge support registers
349 * SCP_BankDelay and SCP_NextFrame
350 * @lane_control_support: Slave supports lane control
351 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
352 * alias
353 * @master_count: Number of Masters present on this Slave
354 * @source_ports: Bitmap identifying source ports
355 * @sink_ports: Bitmap identifying sink ports
356 * @quirks: bitmask identifying deltas from the MIPI specification
357 * @sdca_interrupt_register_list: indicates which sets of SDCA interrupt status
358 * and masks are supported
359 * @commit_register_supported: is PCP_Commit register supported
360 * @scp_int1_mask: SCP_INT1_MASK desired settings
361 * @lane_maps: Lane mapping for the slave, only valid if lane_control_support is set
362 * @clock_reg_supported: the Peripheral implements the clock base and scale
363 * registers introduced with the SoundWire 1.2 specification. SDCA devices
364 * do not need to set this boolean property as the registers are required.
365 * @use_domain_irq: call actual IRQ handler on slave, as well as callback
366 */
367 struct sdw_slave_prop {
368 struct sdw_dp0_prop *dp0_prop;
369 struct sdw_dpn_prop *src_dpn_prop;
370 struct sdw_dpn_prop *sink_dpn_prop;
371 u32 mipi_revision;
372 bool wake_capable;
373 bool test_mode_capable;
374 bool clk_stop_mode1;
375 bool simple_clk_stop_capable;
376 u32 clk_stop_timeout;
377 u32 ch_prep_timeout;
378 enum sdw_clk_stop_reset_behave reset_behave;
379 bool high_PHY_capable;
380 bool paging_support;
381 bool bank_delay_support;
382 bool lane_control_support;
383 enum sdw_p15_behave p15_behave;
384 u32 master_count;
385 u32 source_ports;
386 u32 sink_ports;
387 u32 quirks;
388 u32 sdca_interrupt_register_list;
389 u8 commit_register_supported;
390 u8 scp_int1_mask;
391 u8 lane_maps[SDW_MAX_LANES];
392 bool clock_reg_supported;
393 bool use_domain_irq;
394 };
395
396 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0)
397
398 /**
399 * struct sdw_master_prop - Master properties
400 * @clk_gears: Clock gears supported
401 * @clk_freq: Clock frequencies supported, in Hz
402 * @quirks: bitmask identifying optional behavior beyond the scope of the MIPI specification
403 * @revision: MIPI spec version of the implementation
404 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
405 * @max_clk_freq: Maximum Bus clock frequency, in Hz
406 * @num_clk_gears: Number of clock gears supported
407 * @num_clk_freq: Number of clock frequencies supported, in Hz
408 * @default_frame_rate: Controller default Frame rate, in Hz
409 * @default_row: Number of rows
410 * @default_col: Number of columns
411 * @dynamic_frame: Dynamic frame shape supported
412 * @err_threshold: Number of times that software may retry sending a single
413 * command
414 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
415 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
416 */
417 struct sdw_master_prop {
418 u32 *clk_gears;
419 u32 *clk_freq;
420 u64 quirks;
421 u32 revision;
422 u32 clk_stop_modes;
423 u32 max_clk_freq;
424 u32 num_clk_gears;
425 u32 num_clk_freq;
426 u32 default_frame_rate;
427 u32 default_row;
428 u32 default_col;
429 u32 err_threshold;
430 u32 mclk_freq;
431 bool dynamic_frame;
432 bool hw_disabled;
433 };
434
435 /* Definitions for Master quirks */
436
437 /*
438 * In a number of platforms bus clashes are reported after a hardware
439 * reset but without any explanations or evidence of a real problem.
440 * The following quirk will discard all initial bus clash interrupts
441 * but will leave the detection on should real bus clashes happen
442 */
443 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH BIT(0)
444
445 /*
446 * Some Slave devices have known issues with incorrect parity errors
447 * reported after a hardware reset. However during integration unexplained
448 * parity errors can be reported by Slave devices, possibly due to electrical
449 * issues at the Master level.
450 * The following quirk will discard all initial parity errors but will leave
451 * the detection on should real parity errors happen.
452 */
453 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1)
454
455 int sdw_master_read_prop(struct sdw_bus *bus);
456 int sdw_slave_read_prop(struct sdw_slave *slave);
457 int sdw_slave_read_lane_mapping(struct sdw_slave *slave);
458
459 /*
460 * SDW Slave Structures and APIs
461 */
462
463 #define SDW_IGNORED_UNIQUE_ID 0xFF
464
465 /**
466 * struct sdw_slave_id - Slave ID
467 * @mfg_id: MIPI Manufacturer ID
468 * @part_id: Device Part ID
469 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec)
470 * @unique_id: Device unique ID
471 * @sdw_version: SDW version implemented
472 *
473 * The order of the IDs here does not follow the DisCo spec definitions
474 */
475 struct sdw_slave_id {
476 __u16 mfg_id;
477 __u16 part_id;
478 __u8 class_id;
479 __u8 unique_id;
480 __u8 sdw_version:4;
481 };
482
483 struct sdw_peripherals {
484 int num_peripherals;
485 struct sdw_slave *array[];
486 };
487
488 /*
489 * Helper macros to extract the MIPI-defined IDs
490 *
491 * Spec definition
492 * Register Bit Contents
493 * DevId_0 [7:4] 47:44 sdw_version
494 * DevId_0 [3:0] 43:40 unique_id
495 * DevId_1 39:32 mfg_id [15:8]
496 * DevId_2 31:24 mfg_id [7:0]
497 * DevId_3 23:16 part_id [15:8]
498 * DevId_4 15:08 part_id [7:0]
499 * DevId_5 07:00 class_id
500 *
501 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48
502 */
503 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48)
504 #define SDW_VERSION_MASK GENMASK_ULL(47, 44)
505 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40)
506 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24)
507 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8)
508 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0)
509
510 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr)
511 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr)
512 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr)
513 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr)
514 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr)
515 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr)
516
517 /**
518 * struct sdw_slave_intr_status - Slave interrupt status
519 * @sdca_cascade: set if the Slave device reports an SDCA interrupt
520 * @control_port: control port status
521 * @port: data port status
522 */
523 struct sdw_slave_intr_status {
524 bool sdca_cascade;
525 u8 control_port;
526 u8 port[15];
527 };
528
529 /**
530 * sdw_reg_bank - SoundWire register banks
531 * @SDW_BANK0: Soundwire register bank 0
532 * @SDW_BANK1: Soundwire register bank 1
533 */
534 enum sdw_reg_bank {
535 SDW_BANK0,
536 SDW_BANK1,
537 };
538
539 /**
540 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
541 *
542 * @num: Port number
543 * @ch_mask: Active channel mask
544 * @prepare: Prepare (true) /de-prepare (false) channel
545 * @bank: Register bank, which bank Slave/Master driver should program for
546 * implementation defined registers. This is always updated to next_bank
547 * value read from bus params.
548 *
549 */
550 struct sdw_prepare_ch {
551 unsigned int num;
552 unsigned int ch_mask;
553 bool prepare;
554 unsigned int bank;
555 };
556
557 /**
558 * enum sdw_port_prep_ops: Prepare operations for Data Port
559 *
560 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
561 * @SDW_OPS_PORT_PRE_DEPREP: Pre deprepare operation for the Port
562 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
563 * @SDW_OPS_PORT_POST_DEPREP: Post deprepare operation for the Port
564 */
565 enum sdw_port_prep_ops {
566 SDW_OPS_PORT_PRE_PREP = 0,
567 SDW_OPS_PORT_PRE_DEPREP,
568 SDW_OPS_PORT_POST_PREP,
569 SDW_OPS_PORT_POST_DEPREP,
570 };
571
572 /**
573 * struct sdw_bus_params: Structure holding bus configuration
574 *
575 * @curr_bank: Current bank in use (BANK0/BANK1)
576 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
577 * set to !curr_bank
578 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
579 * @curr_dr_freq: Current double rate clock frequency, in Hz
580 * @bandwidth: Current bandwidth
581 * @col: Active columns
582 * @row: Active rows
583 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports
584 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
585 * should be the same to detect transmission issues, but can be different to
586 * test the interrupt reports
587 */
588 struct sdw_bus_params {
589 enum sdw_reg_bank curr_bank;
590 enum sdw_reg_bank next_bank;
591 unsigned int max_dr_freq;
592 unsigned int curr_dr_freq;
593 unsigned int bandwidth;
594 unsigned int col;
595 unsigned int row;
596 int s_data_mode;
597 int m_data_mode;
598 };
599
600 /**
601 * struct sdw_slave_ops: Slave driver callback ops
602 *
603 * @read_prop: Read Slave properties
604 * @interrupt_callback: Device interrupt notification (invoked in thread
605 * context)
606 * @update_status: Update Slave status
607 * @bus_config: Update the bus config for Slave
608 * @port_prep: Prepare the port with parameters
609 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare
610 */
611 struct sdw_slave_ops {
612 int (*read_prop)(struct sdw_slave *sdw);
613 int (*interrupt_callback)(struct sdw_slave *slave,
614 struct sdw_slave_intr_status *status);
615 int (*update_status)(struct sdw_slave *slave,
616 enum sdw_slave_status status);
617 int (*bus_config)(struct sdw_slave *slave,
618 struct sdw_bus_params *params);
619 int (*port_prep)(struct sdw_slave *slave,
620 struct sdw_prepare_ch *prepare_ch,
621 enum sdw_port_prep_ops pre_ops);
622 int (*clk_stop)(struct sdw_slave *slave,
623 enum sdw_clk_stop_mode mode,
624 enum sdw_clk_stop_type type);
625 };
626
627 /**
628 * struct sdw_slave - SoundWire Slave
629 * @id: MIPI device ID
630 * @dev: Linux device
631 * @irq: IRQ number
632 * @status: Status reported by the Slave
633 * @bus: Bus handle
634 * @prop: Slave properties
635 * @debugfs: Slave debugfs
636 * @node: node for bus list
637 * @port_ready: Port ready completion flag for each Slave port
638 * @m_port_map: static Master port map for each Slave port
639 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky
640 * @dev_num_sticky: one-time static Device Number assigned by Bus
641 * @probed: boolean tracking driver state
642 * @enumeration_complete: completion utility to control potential races
643 * on startup between device enumeration and read/write access to the
644 * Slave device
645 * @initialization_complete: completion utility to control potential races
646 * on startup between device enumeration and settings being restored
647 * @unattach_request: mask field to keep track why the Slave re-attached and
648 * was re-initialized. This is useful to deal with potential race conditions
649 * between the Master suspending and the codec resuming, and make sure that
650 * when the Master triggered a reset the Slave is properly enumerated and
651 * initialized
652 * @first_interrupt_done: status flag tracking if the interrupt handling
653 * for a Slave happens for the first time after enumeration
654 * @is_mockup_device: status flag used to squelch errors in the command/control
655 * protocol for SoundWire mockup devices
656 * @sdw_dev_lock: mutex used to protect callbacks/remove races
657 * @sdca_data: structure containing all device data for SDCA helpers
658 */
659 struct sdw_slave {
660 struct sdw_slave_id id;
661 struct device dev;
662 int irq;
663 enum sdw_slave_status status;
664 struct sdw_bus *bus;
665 struct sdw_slave_prop prop;
666 #ifdef CONFIG_DEBUG_FS
667 struct dentry *debugfs;
668 #endif
669 struct list_head node;
670 struct completion port_ready[SDW_MAX_PORTS];
671 unsigned int m_port_map[SDW_MAX_PORTS];
672 u16 dev_num;
673 u16 dev_num_sticky;
674 bool probed;
675 struct completion enumeration_complete;
676 struct completion initialization_complete;
677 u32 unattach_request;
678 bool first_interrupt_done;
679 bool is_mockup_device;
680 struct mutex sdw_dev_lock; /* protect callbacks/remove races */
681 struct sdca_device_data sdca_data;
682 };
683
684 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
685
686 /**
687 * struct sdw_master_device - SoundWire 'Master Device' representation
688 * @dev: Linux device for this Master
689 * @bus: Bus handle shortcut
690 */
691 struct sdw_master_device {
692 struct device dev;
693 struct sdw_bus *bus;
694 };
695
696 #define dev_to_sdw_master_device(d) \
697 container_of(d, struct sdw_master_device, dev)
698
699 struct sdw_driver {
700 int (*probe)(struct sdw_slave *sdw, const struct sdw_device_id *id);
701 int (*remove)(struct sdw_slave *sdw);
702 void (*shutdown)(struct sdw_slave *sdw);
703
704 const struct sdw_device_id *id_table;
705 const struct sdw_slave_ops *ops;
706
707 struct device_driver driver;
708 };
709
710 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \
711 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
712 .sdw_version = (_version), .class_id = (_c_id), \
713 .driver_data = (unsigned long)(_drv_data) }
714
715 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
716 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data))
717
718 int sdw_handle_slave_status(struct sdw_bus *bus,
719 enum sdw_slave_status status[]);
720
721 /*
722 * SDW master structures and APIs
723 */
724
725 /**
726 * struct sdw_port_params: Data Port parameters
727 *
728 * @num: Port number
729 * @bps: Word length of the Port
730 * @flow_mode: Port Data flow mode
731 * @data_mode: Test modes or normal mode
732 *
733 * This is used to program the Data Port based on Data Port stream
734 * parameters.
735 */
736 struct sdw_port_params {
737 unsigned int num;
738 unsigned int bps;
739 unsigned int flow_mode;
740 unsigned int data_mode;
741 };
742
743 /**
744 * struct sdw_transport_params: Data Port Transport Parameters
745 *
746 * @blk_grp_ctrl_valid: Port implements block group control
747 * @num: Port number
748 * @blk_grp_ctrl: Block group control value
749 * @sample_interval: Sample interval
750 * @offset1: Blockoffset of the payload data
751 * @offset2: Blockoffset of the payload data
752 * @hstart: Horizontal start of the payload data
753 * @hstop: Horizontal stop of the payload data
754 * @blk_pkg_mode: Block per channel or block per port
755 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
756 * data lane is supported in bus
757 *
758 * This is used to program the Data Port based on Data Port transport
759 * parameters. All these parameters are banked and can be modified
760 * during a bank switch without any artifacts in audio stream.
761 */
762 struct sdw_transport_params {
763 bool blk_grp_ctrl_valid;
764 unsigned int port_num;
765 unsigned int blk_grp_ctrl;
766 unsigned int sample_interval;
767 unsigned int offset1;
768 unsigned int offset2;
769 unsigned int hstart;
770 unsigned int hstop;
771 unsigned int blk_pkg_mode;
772 unsigned int lane_ctrl;
773 };
774
775 /**
776 * struct sdw_enable_ch: Enable/disable Data Port channel
777 *
778 * @num: Port number
779 * @ch_mask: Active channel mask
780 * @enable: Enable (true) /disable (false) channel
781 */
782 struct sdw_enable_ch {
783 unsigned int port_num;
784 unsigned int ch_mask;
785 bool enable;
786 };
787
788 /**
789 * struct sdw_master_port_ops: Callback functions from bus to Master
790 * driver to set Master Data ports.
791 *
792 * @dpn_set_port_params: Set the Port parameters for the Master Port.
793 * Mandatory callback
794 * @dpn_set_port_transport_params: Set transport parameters for the Master
795 * Port. Mandatory callback
796 * @dpn_port_prep: Port prepare operations for the Master Data Port.
797 * @dpn_port_enable_ch: Enable the channels of Master Port.
798 */
799 struct sdw_master_port_ops {
800 int (*dpn_set_port_params)(struct sdw_bus *bus,
801 struct sdw_port_params *port_params,
802 unsigned int bank);
803 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
804 struct sdw_transport_params *transport_params,
805 enum sdw_reg_bank bank);
806 int (*dpn_port_prep)(struct sdw_bus *bus, struct sdw_prepare_ch *prepare_ch);
807 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
808 struct sdw_enable_ch *enable_ch, unsigned int bank);
809 };
810
811 struct sdw_msg;
812
813 /**
814 * struct sdw_defer - SDW deferred message
815 * @complete: message completion
816 * @msg: SDW message
817 * @length: message length
818 */
819 struct sdw_defer {
820 struct sdw_msg *msg;
821 int length;
822 struct completion complete;
823 };
824
825 /**
826 * struct sdw_master_ops - Master driver ops
827 * @read_prop: Read Master properties
828 * @override_adr: Override value read from firmware (quirk for buggy firmware)
829 * @xfer_msg: Transfer message callback
830 * @xfer_msg_defer: Defer version of transfer message callback. The message is handled with the
831 * bus struct @sdw_defer
832 * @set_bus_conf: Set the bus configuration
833 * @pre_bank_switch: Callback for pre bank switch
834 * @post_bank_switch: Callback for post bank switch
835 * @read_ping_status: Read status from PING frames, reported with two bits per Device.
836 * Bits 31:24 are reserved.
837 * @get_device_num: Callback for vendor-specific device_number allocation
838 * @put_device_num: Callback for vendor-specific device_number release
839 * @new_peripheral_assigned: Callback to handle enumeration of new peripheral.
840 */
841 struct sdw_master_ops {
842 int (*read_prop)(struct sdw_bus *bus);
843 u64 (*override_adr)(struct sdw_bus *bus, u64 addr);
844 enum sdw_command_response (*xfer_msg)(struct sdw_bus *bus, struct sdw_msg *msg);
845 enum sdw_command_response (*xfer_msg_defer)(struct sdw_bus *bus);
846 int (*set_bus_conf)(struct sdw_bus *bus,
847 struct sdw_bus_params *params);
848 int (*pre_bank_switch)(struct sdw_bus *bus);
849 int (*post_bank_switch)(struct sdw_bus *bus);
850 u32 (*read_ping_status)(struct sdw_bus *bus);
851 int (*get_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
852 void (*put_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
853 void (*new_peripheral_assigned)(struct sdw_bus *bus,
854 struct sdw_slave *slave,
855 int dev_num);
856 };
857
858 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
859 struct fwnode_handle *fwnode);
860 void sdw_bus_master_delete(struct sdw_bus *bus);
861
862 void sdw_show_ping_status(struct sdw_bus *bus, bool sync_delay);
863
864 /**
865 * sdw_port_config: Master or Slave Port configuration
866 *
867 * @num: Port number
868 * @ch_mask: channels mask for port
869 */
870 struct sdw_port_config {
871 unsigned int num;
872 unsigned int ch_mask;
873 };
874
875 /**
876 * sdw_stream_config: Master or Slave stream configuration
877 *
878 * @frame_rate: Audio frame rate of the stream, in Hz
879 * @ch_count: Channel count of the stream
880 * @bps: Number of bits per audio sample
881 * @direction: Data direction
882 * @type: Stream type PCM or PDM
883 */
884 struct sdw_stream_config {
885 unsigned int frame_rate;
886 unsigned int ch_count;
887 unsigned int bps;
888 enum sdw_data_direction direction;
889 enum sdw_stream_type type;
890 };
891
892 /**
893 * sdw_stream_state: Stream states
894 *
895 * @SDW_STREAM_ALLOCATED: New stream allocated.
896 * @SDW_STREAM_CONFIGURED: Stream configured
897 * @SDW_STREAM_PREPARED: Stream prepared
898 * @SDW_STREAM_ENABLED: Stream enabled
899 * @SDW_STREAM_DISABLED: Stream disabled
900 * @SDW_STREAM_DEPREPARED: Stream de-prepared
901 * @SDW_STREAM_RELEASED: Stream released
902 */
903 enum sdw_stream_state {
904 SDW_STREAM_ALLOCATED = 0,
905 SDW_STREAM_CONFIGURED = 1,
906 SDW_STREAM_PREPARED = 2,
907 SDW_STREAM_ENABLED = 3,
908 SDW_STREAM_DISABLED = 4,
909 SDW_STREAM_DEPREPARED = 5,
910 SDW_STREAM_RELEASED = 6,
911 };
912
913 /**
914 * sdw_stream_params: Stream parameters
915 *
916 * @rate: Sampling frequency, in Hz
917 * @ch_count: Number of channels
918 * @bps: bits per channel sample
919 */
920 struct sdw_stream_params {
921 unsigned int rate;
922 unsigned int ch_count;
923 unsigned int bps;
924 };
925
926 /**
927 * sdw_stream_runtime: Runtime stream parameters
928 *
929 * @name: SoundWire stream name
930 * @params: Stream parameters
931 * @state: Current state of the stream
932 * @type: Stream type PCM or PDM
933 * @m_rt_count: Count of Master runtime(s) in this stream
934 * @master_list: List of Master runtime(s) in this stream.
935 * master_list can contain only one m_rt per Master instance
936 * for a stream
937 */
938 struct sdw_stream_runtime {
939 const char *name;
940 struct sdw_stream_params params;
941 enum sdw_stream_state state;
942 enum sdw_stream_type type;
943 int m_rt_count;
944 struct list_head master_list;
945 };
946
947 /**
948 * struct sdw_bus - SoundWire bus
949 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
950 * @md: Master device
951 * @bus_lock_key: bus lock key associated to @bus_lock
952 * @bus_lock: bus lock
953 * @slaves: list of Slaves on this bus
954 * @msg_lock_key: message lock key associated to @msg_lock
955 * @msg_lock: message lock
956 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
957 * is used to compute and program bus bandwidth, clock, frame shape,
958 * transport and port parameters
959 * @defer_msg: Defer message
960 * @params: Current bus parameters
961 * @stream_refcount: number of streams currently using this bus
962 * @ops: Master callback ops
963 * @port_ops: Master port callback ops
964 * @prop: Master properties
965 * @vendor_specific_prop: pointer to non-standard properties
966 * @hw_sync_min_links: Number of links used by a stream above which
967 * hardware-based synchronization is required. This value is only
968 * meaningful if multi_link is set. If set to 1, hardware-based
969 * synchronization will be used even if a stream only uses a single
970 * SoundWire segment.
971 * @controller_id: system-unique controller ID. If set to -1, the bus @id will be used.
972 * @link_id: Link id number, can be 0 to N, unique for each Controller
973 * @id: bus system-wide unique id
974 * @compute_params: points to Bus resource management implementation
975 * @assigned: Bitmap for Slave device numbers.
976 * Bit set implies used number, bit clear implies unused number.
977 * @clk_stop_timeout: Clock stop timeout computed
978 * @bank_switch_timeout: Bank switch timeout computed
979 * @domain: IRQ domain
980 * @irq_chip: IRQ chip
981 * @debugfs: Bus debugfs (optional)
982 * @multi_link: Store bus property that indicates if multi links
983 * are supported. This flag is populated by drivers after reading
984 * appropriate firmware (ACPI/DT).
985 * @lane_used_bandwidth: how much bandwidth in bits per second is used by each lane
986 */
987 struct sdw_bus {
988 struct device *dev;
989 struct sdw_master_device *md;
990 struct lock_class_key bus_lock_key;
991 struct mutex bus_lock;
992 struct list_head slaves;
993 struct lock_class_key msg_lock_key;
994 struct mutex msg_lock;
995 struct list_head m_rt_list;
996 struct sdw_defer defer_msg;
997 struct sdw_bus_params params;
998 int stream_refcount;
999 const struct sdw_master_ops *ops;
1000 const struct sdw_master_port_ops *port_ops;
1001 struct sdw_master_prop prop;
1002 void *vendor_specific_prop;
1003 int hw_sync_min_links;
1004 int controller_id;
1005 unsigned int link_id;
1006 int id;
1007 int (*compute_params)(struct sdw_bus *bus, struct sdw_stream_runtime *stream);
1008 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
1009 unsigned int clk_stop_timeout;
1010 u32 bank_switch_timeout;
1011 struct irq_chip irq_chip;
1012 struct irq_domain *domain;
1013 #ifdef CONFIG_DEBUG_FS
1014 struct dentry *debugfs;
1015 #endif
1016 bool multi_link;
1017 unsigned int lane_used_bandwidth[SDW_MAX_LANES];
1018 };
1019
1020 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
1021 void sdw_release_stream(struct sdw_stream_runtime *stream);
1022
1023 int sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream);
1024
1025 int sdw_stream_add_master(struct sdw_bus *bus,
1026 struct sdw_stream_config *stream_config,
1027 const struct sdw_port_config *port_config,
1028 unsigned int num_ports,
1029 struct sdw_stream_runtime *stream);
1030 int sdw_stream_remove_master(struct sdw_bus *bus,
1031 struct sdw_stream_runtime *stream);
1032 int sdw_startup_stream(void *sdw_substream);
1033 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
1034 int sdw_enable_stream(struct sdw_stream_runtime *stream);
1035 int sdw_disable_stream(struct sdw_stream_runtime *stream);
1036 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
1037 void sdw_shutdown_stream(void *sdw_substream);
1038 int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
1039 int sdw_bus_clk_stop(struct sdw_bus *bus);
1040 int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
1041
1042 int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id);
1043 void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id);
1044 bool is_clock_scaling_supported_by_slave(struct sdw_slave *slave);
1045
1046 #if IS_ENABLED(CONFIG_SOUNDWIRE)
1047
1048 int sdw_stream_add_slave(struct sdw_slave *slave,
1049 struct sdw_stream_config *stream_config,
1050 const struct sdw_port_config *port_config,
1051 unsigned int num_ports,
1052 struct sdw_stream_runtime *stream);
1053 int sdw_stream_remove_slave(struct sdw_slave *slave,
1054 struct sdw_stream_runtime *stream);
1055
1056 int sdw_slave_get_scale_index(struct sdw_slave *slave, u8 *base);
1057
1058 /* messaging and data APIs */
1059 int sdw_read(struct sdw_slave *slave, u32 addr);
1060 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
1061 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value);
1062 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr);
1063 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1064 int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1065 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1066 int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1067 int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1068 int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1069
1070 #else
1071
sdw_stream_add_slave(struct sdw_slave * slave,struct sdw_stream_config * stream_config,const struct sdw_port_config * port_config,unsigned int num_ports,struct sdw_stream_runtime * stream)1072 static inline int sdw_stream_add_slave(struct sdw_slave *slave,
1073 struct sdw_stream_config *stream_config,
1074 const struct sdw_port_config *port_config,
1075 unsigned int num_ports,
1076 struct sdw_stream_runtime *stream)
1077 {
1078 WARN_ONCE(1, "SoundWire API is disabled");
1079 return -EINVAL;
1080 }
1081
sdw_stream_remove_slave(struct sdw_slave * slave,struct sdw_stream_runtime * stream)1082 static inline int sdw_stream_remove_slave(struct sdw_slave *slave,
1083 struct sdw_stream_runtime *stream)
1084 {
1085 WARN_ONCE(1, "SoundWire API is disabled");
1086 return -EINVAL;
1087 }
1088
1089 /* messaging and data APIs */
sdw_read(struct sdw_slave * slave,u32 addr)1090 static inline int sdw_read(struct sdw_slave *slave, u32 addr)
1091 {
1092 WARN_ONCE(1, "SoundWire API is disabled");
1093 return -EINVAL;
1094 }
1095
sdw_write(struct sdw_slave * slave,u32 addr,u8 value)1096 static inline int sdw_write(struct sdw_slave *slave, u32 addr, u8 value)
1097 {
1098 WARN_ONCE(1, "SoundWire API is disabled");
1099 return -EINVAL;
1100 }
1101
sdw_write_no_pm(struct sdw_slave * slave,u32 addr,u8 value)1102 static inline int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value)
1103 {
1104 WARN_ONCE(1, "SoundWire API is disabled");
1105 return -EINVAL;
1106 }
1107
sdw_read_no_pm(struct sdw_slave * slave,u32 addr)1108 static inline int sdw_read_no_pm(struct sdw_slave *slave, u32 addr)
1109 {
1110 WARN_ONCE(1, "SoundWire API is disabled");
1111 return -EINVAL;
1112 }
1113
sdw_nread(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1114 static inline int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1115 {
1116 WARN_ONCE(1, "SoundWire API is disabled");
1117 return -EINVAL;
1118 }
1119
sdw_nread_no_pm(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1120 static inline int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1121 {
1122 WARN_ONCE(1, "SoundWire API is disabled");
1123 return -EINVAL;
1124 }
1125
sdw_nwrite(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1126 static inline int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1127 {
1128 WARN_ONCE(1, "SoundWire API is disabled");
1129 return -EINVAL;
1130 }
1131
sdw_nwrite_no_pm(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1132 static inline int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1133 {
1134 WARN_ONCE(1, "SoundWire API is disabled");
1135 return -EINVAL;
1136 }
1137
sdw_update(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1138 static inline int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1139 {
1140 WARN_ONCE(1, "SoundWire API is disabled");
1141 return -EINVAL;
1142 }
1143
sdw_update_no_pm(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1144 static inline int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1145 {
1146 WARN_ONCE(1, "SoundWire API is disabled");
1147 return -EINVAL;
1148 }
1149
1150 #endif /* CONFIG_SOUNDWIRE */
1151
1152 #endif /* __SOUNDWIRE_H */
1153