1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/io.h>
4 #include <pc80/i8259.h>
5 #include <console/console.h>
6 #include <stdint.h>
7
8 /* Read the current PIC IRQ mask */
pic_read_irq_mask(void)9 u16 pic_read_irq_mask(void)
10 {
11 u16 mask;
12 int i;
13
14 mask = inb(MASTER_PIC_OCW1) | (inb(SLAVE_PIC_OCW1) << 8);
15
16 printk(BIOS_DEBUG, "8259 PIC: OCW1 IRQ Mask: 0x%x\n", mask);
17 printk(BIOS_SPEW, "\tEnabled IRQs (0 = Unmasked, 1 = Masked off):\n"
18 "\t\tMaster\t\tSlave\n");
19 for (i = 0; i <= 7; i++) {
20 printk(BIOS_SPEW, "\t\tIRQ%X: %x\t\tIRQ%X: %x\n",
21 i, (mask >> i) & 1, i + 8, (mask >> (i + 8)) & 1);
22 }
23 return mask;
24 }
25
26 /*
27 * Write an IRQ mask to the PIC:
28 * IRQA is bit 0xA in the 16 bit bitmask (OCW1)
29 */
pic_write_irq_mask(u16 mask)30 void pic_write_irq_mask(u16 mask)
31 {
32 outb(mask, MASTER_PIC_OCW1);
33 outb(mask >> 8, SLAVE_PIC_OCW1);
34 }
35
36 /*
37 * The PIC IRQs default to masked off
38 * Allow specific IRQs to be enabled (1)
39 * or disabled by (0) the user
40 */
pic_irq_enable(u8 int_num,u8 mask)41 void pic_irq_enable(u8 int_num, u8 mask)
42 {
43 pic_write_irq_mask(pic_read_irq_mask() & ~(mask << int_num));
44 pic_read_irq_mask();
45 }
46
setup_i8259(void)47 void setup_i8259(void)
48 {
49 /* A write to ICW1 starts the Interrupt Controller Initialization
50 * Sequence. This implicitly causes the following to happen:
51 * - Interrupt Mask register is cleared
52 * - Priority 7 is assigned to IRQ7 input
53 * - Slave mode address is set to 7
54 * - Special mask mode is cleared
55 *
56 * We send the initialization sequence to both the master and
57 * slave i8259 controller.
58 */
59 outb(ICW_SELECT|IC4, MASTER_PIC_ICW1);
60 outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1);
61
62 /* Now the interrupt controller expects us to write to ICW2. */
63 outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2);
64 outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2);
65
66 /* Now the interrupt controller expects us to write to ICW3.
67 *
68 * The normal scenario is to set up cascading on IRQ2 on the master
69 * i8259 and assign the slave ID 2 to the slave i8259.
70 */
71 outb(CASCADED_PIC, MASTER_PIC_ICW3);
72 outb(SLAVE_ID, SLAVE_PIC_ICW3);
73
74 /* Now the interrupt controller expects us to write to ICW4.
75 *
76 * We switch both i8259 to microprocessor mode because they're
77 * operating as part of an x86 architecture based chipset
78 */
79 outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2);
80 outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2);
81
82 /* Now clear the interrupts through OCW1.
83 * First we mask off all interrupts on the slave interrupt controller
84 * then we mask off all interrupts but interrupt 2 on the master
85 * controller. This way the cascading stays alive.
86 */
87 outb(ALL_IRQS, SLAVE_PIC_OCW1);
88 outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
89 }
90
91 /**
92 * @brief Configure IRQ triggering in the i8259 compatible Interrupt Controller.
93 *
94 * Switch a certain interrupt to be level / edge triggered.
95 *
96 * @param int_num legacy interrupt number (3-7, 9-15)
97 * @param is_level_triggered 1 for level triggered interrupt, 0 for edge
98 * triggered interrupt
99 */
i8259_configure_irq_trigger(int int_num,int is_level_triggered)100 void i8259_configure_irq_trigger(int int_num, int is_level_triggered)
101 {
102 u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
103
104 if (is_level_triggered)
105 int_bits |= (1 << int_num);
106 else
107 int_bits &= ~(1 << int_num);
108
109 /* Write new values */
110 outb((u8)(int_bits & 0xff), ELCR1);
111 outb((u8)(int_bits >> 8), ELCR2);
112 }
113