1 /* 2 * Copyright © 2009 Corbin Simpson 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef RADEON_DRM_WINSYS_H 8 #define RADEON_DRM_WINSYS_H 9 10 #include "winsys/radeon_winsys.h" 11 #include "pipebuffer/pb_cache.h" 12 #include "pipebuffer/pb_slab.h" 13 #include "util/u_queue.h" 14 #include "util/list.h" 15 #include <radeon_drm.h> 16 17 struct radeon_drm_cs; 18 19 enum radeon_generation { 20 DRV_R300, 21 DRV_R600, 22 DRV_SI 23 }; 24 25 #define RADEON_SLAB_MIN_SIZE_LOG2 9 26 #define RADEON_SLAB_MAX_SIZE_LOG2 14 27 28 struct radeon_vm_heap { 29 mtx_t mutex; 30 uint64_t start; 31 uint64_t end; 32 struct list_head holes; 33 }; 34 35 struct radeon_drm_winsys { 36 struct radeon_winsys base; 37 struct pipe_reference reference; 38 struct pb_cache bo_cache; 39 struct pb_slabs bo_slabs; 40 41 int fd; /* DRM file descriptor */ 42 int num_cs; /* The number of command streams created. */ 43 uint64_t allocated_vram; 44 uint64_t allocated_gtt; 45 uint64_t mapped_vram; 46 uint64_t mapped_gtt; 47 uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */ 48 uint64_t num_gfx_IBs; 49 uint64_t num_sdma_IBs; 50 uint64_t num_mapped_buffers; 51 uint32_t next_bo_hash; 52 53 enum radeon_generation gen; 54 struct radeon_info info; 55 uint32_t va_start; 56 uint32_t va_unmap_working; 57 uint32_t accel_working2; 58 59 /* List of buffer GEM names. Protected by bo_handles_mutex. */ 60 struct hash_table *bo_names; 61 /* List of buffer handles. Protected by bo_handles_mutex. */ 62 struct hash_table *bo_handles; 63 /* List of buffer virtual memory ranges. Protected by bo_handles_mutex. */ 64 struct hash_table_u64 *bo_vas; 65 mtx_t bo_handles_mutex; 66 mtx_t bo_fence_lock; 67 68 struct radeon_vm_heap vm32; 69 struct radeon_vm_heap vm64; 70 71 bool check_vm; 72 bool noop_cs; 73 74 struct radeon_surface_manager *surf_man; 75 76 uint32_t num_cpus; /* Number of CPUs. */ 77 78 struct radeon_drm_cs *hyperz_owner; 79 mtx_t hyperz_owner_mutex; 80 struct radeon_drm_cs *cmask_owner; 81 mtx_t cmask_owner_mutex; 82 83 /* multithreaded command submission */ 84 struct util_queue cs_queue; 85 }; 86 radeon_drm_winsys(struct radeon_winsys * base)87static inline struct radeon_drm_winsys *radeon_drm_winsys(struct radeon_winsys *base) 88 { 89 return (struct radeon_drm_winsys*)base; 90 } 91 92 uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws); 93 void radeon_surface_init_functions(struct radeon_drm_winsys *ws); 94 95 #endif 96