1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <device/pci_ops.h>
4 #include <southbridge/intel/lynxpoint/hsio/hsio.h>
5 #include <southbridge/intel/lynxpoint/pch.h>
6 #include <types.h>
7
8 /**
9 * FIXME: Ask Intel whether all lanes need to be programmed as specified
10 * in the PCH BWG. If not, make separate tables and only check this once.
11 */
hsio_sata_shared_update(const uint32_t addr,const uint32_t and,const uint32_t or)12 void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
13 {
14 const uint8_t lane_owner = pci_read_config8(PCH_PCIE_DEV(0), 0x410);
15
16 if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4)))
17 return;
18
19 if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5)))
20 return;
21
22 if (CONFIG(INTEL_LYNXPOINT_LP)) {
23 if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6)))
24 return;
25
26 if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7)))
27 return;
28 }
29 hsio_update(addr, and, or);
30 }
31
hsio_xhci_shared_update(const uint32_t addr,const uint32_t and,const uint32_t or)32 void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
33 {
34 const uint8_t lane_owner = pci_read_config8(PCH_PCIE_DEV(0), 0x410);
35 if (CONFIG(INTEL_LYNXPOINT_LP)) {
36 if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2)
37 return;
38
39 if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2)
40 return;
41 } else {
42 if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2)
43 return;
44
45 if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2)
46 return;
47 }
48 hsio_update(addr, and, or);
49 }
50