1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ 8 #define _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ 9 10 /* 11 * These are the indices of each interrupt in the interrupt 12 * controller's registers. these can be used as the irq_id 13 * argument to the hrt functions irq_controller.h. 14 * 15 * The definitions are taken from <system>_defs.h 16 */ 17 typedef enum hrt_isp_css_irq { 18 hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID, 19 hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID, 20 hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID, 21 hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID, 22 hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID, 23 hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID, 24 hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID, 25 hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID, 26 hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID, 27 hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID, 28 hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID, 29 hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID, 30 hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID, 31 hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID, 32 hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID, 33 hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID, 34 hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID, 35 hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID, 36 hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID, 37 hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID, 38 hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID, 39 hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID, 40 hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID, 41 hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID, 42 hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID, 43 hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID, 44 hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID, 45 hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID, 46 hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID, 47 hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID, 48 hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID, 49 hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID, 50 /* this must (obviously) be the last on in the enum */ 51 hrt_isp_css_irq_num_irqs 52 } hrt_isp_css_irq_t; 53 54 typedef enum hrt_isp_css_irq_status { 55 hrt_isp_css_irq_status_error, 56 hrt_isp_css_irq_status_more_irqs, 57 hrt_isp_css_irq_status_success 58 } hrt_isp_css_irq_status_t; 59 60 #endif /* _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ */ 61