1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_DISPLAY_DSI_PHY_H 4 #define _SOC_DISPLAY_DSI_PHY_H 5 6 #include <stdint.h> 7 #include <soc/display/dsi_phy_pll.h> 8 9 #define MAX_REGULATOR_CONFIG 7 10 #define MAX_BIST_CONFIG 6 11 #define MAX_TIMING_CONFIG 40 12 #define MAX_LANE_CONFIG 45 13 #define MAX_STRENGTH_CONFIG 10 14 #define MAX_CTRL_CONFIG 4 15 #define DMA_TPG_FIFO_LEN 64 16 17 struct msm_panel_info; 18 struct mipi_dsi_phy_ctrl { 19 uint32_t regulator[5]; 20 uint32_t timing[12]; 21 uint32_t ctrl[4]; 22 uint32_t strength[4]; 23 uint32_t pll[21]; 24 }; 25 26 enum dsi_reg_mode { 27 DSI_PHY_REGULATOR_DCDC_MODE, 28 DSI_PHY_REGULATOR_LDO_MODE, 29 }; 30 31 enum { 32 DSI_PLL_TYPE_10NM, 33 DSI_PLL_TYPE_MAX, 34 }; 35 36 struct msm_dsi_phy_ctrl { 37 uint32_t clk_pre; 38 uint32_t clk_post; 39 uint32_t clk_zero; 40 uint32_t clk_trail; 41 uint32_t clk_prepare; 42 uint32_t hs_exit; 43 uint32_t hs_zero; 44 uint32_t hs_prepare; 45 uint32_t hs_trail; 46 uint32_t hs_rqst; 47 uint32_t ta_go; 48 uint32_t ta_sure; 49 uint32_t ta_get; 50 uint32_t half_byte_clk_en; 51 bool clk_pre_inc_by_2; 52 }; 53 54 struct mdss_dsi_phy_ctrl { 55 uint32_t regulator[MAX_REGULATOR_CONFIG]; 56 uint32_t timing[MAX_TIMING_CONFIG]; 57 uint32_t ctrl[MAX_CTRL_CONFIG]; 58 uint32_t strength[MAX_STRENGTH_CONFIG]; 59 char bistCtrl[MAX_BIST_CONFIG]; 60 char laneCfg[MAX_LANE_CONFIG]; 61 enum dsi_reg_mode regulator_mode; 62 int pll_type; 63 }; 64 65 enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp); 66 67 #endif 68