xref: /aosp_15_r20/external/coreboot/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __SOC_COMMON_QCOM_QUP_SE_H__
4 #define __SOC_COMMON_QCOM_QUP_SE_H__
5 
6 #include <device/mmio.h>
7 #include <gpio.h>
8 #include <soc/addressmap.h>
9 #include <timer.h>
10 #include <types.h>
11 
12 #define QC_GENMASK(h, l)	(BIT(h + 1) - BIT(l))
13 
14 /* GENI_OUTPUT_CTRL fields */
15 #define DEFAULT_IO_OUTPUT_CTRL_MSK	QC_GENMASK(6, 0)
16 
17 /* GENI_FORCE_DEFAULT_REG fields */
18 #define FORCE_DEFAULT	BIT(0)
19 
20 #define GENI_FW_REVISION_RO_PROTOCOL_MASK	0x0000FF00
21 #define GENI_FW_REVISION_RO_PROTOCOL_SHIFT	0x00000008
22 
23 /* GENI_CGC_CTRL fields */
24 #define CFG_AHB_CLK_CGC_ON		BIT(0)
25 #define CFG_AHB_WR_ACLK_CGC_ON		BIT(1)
26 #define DATA_AHB_CLK_CGC_ON		BIT(2)
27 #define SCLK_CGC_ON			BIT(3)
28 #define TX_CLK_CGC_ON			BIT(4)
29 #define RX_CLK_CGC_ON			BIT(5)
30 #define EXT_CLK_CGC_ON			BIT(6)
31 #define PROG_RAM_HCLK_OFF		BIT(8)
32 #define PROG_RAM_SCLK_OFF		BIT(9)
33 #define DEFAULT_CGC_EN		(CFG_AHB_CLK_CGC_ON | CFG_AHB_WR_ACLK_CGC_ON \
34 			| DATA_AHB_CLK_CGC_ON | SCLK_CGC_ON \
35 			| TX_CLK_CGC_ON | RX_CLK_CGC_ON | EXT_CLK_CGC_ON)
36 
37 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
38 #define SER_CLK_EN			BIT(0)
39 #define CLK_DIV_SHFT			4
40 #define CLK_DIV_MSK			(0xFFF << CLK_DIV_SHFT)
41 
42 /* FIFO_IF_DISABLE_RO fields */
43 #define FIFO_IF_DISABLE			BIT(0)
44 
45 /* FW_REVISION_RO fields */
46 #define FW_REV_PROTOCOL_MSK	QC_GENMASK(15, 8)
47 #define FW_REV_PROTOCOL_SHFT	8
48 #define FW_REV_VERSION_SHFT		0
49 
50 /* GENI_CLK_SEL fields */
51 #define CLK_SEL_MSK		QC_GENMASK(2, 0)
52 
53 /* SE_GENI_DMA_MODE_EN */
54 #define GENI_DMA_MODE_EN	BIT(0)
55 
56 /* GENI_M_CMD0 fields */
57 #define M_OPCODE_MSK		QC_GENMASK(31, 27)
58 #define M_OPCODE_SHFT		27
59 #define M_PARAMS_MSK		QC_GENMASK(26, 0)
60 
61 /* GENI_M_CMD_CTRL_REG */
62 #define M_GENI_CMD_CANCEL	BIT(2)
63 #define M_GENI_CMD_ABORT	BIT(1)
64 #define M_GENI_DISABLE		BIT(0)
65 
66 /* GENI_S_CMD0 fields */
67 #define S_OPCODE_MSK		QC_GENMASK(31, 27)
68 #define S_OPCODE_SHFT		27
69 #define S_PARAMS_MSK		QC_GENMASK(26, 0)
70 
71 /* GENI_S_CMD_CTRL_REG */
72 #define S_GENI_CMD_CANCEL	BIT(2)
73 #define S_GENI_CMD_ABORT	BIT(1)
74 #define S_GENI_DISABLE		BIT(0)
75 
76 /* GENI_M_IRQ_EN fields */
77 #define M_CMD_DONE_EN		BIT(0)
78 #define M_CMD_OVERRUN_EN	BIT(1)
79 #define M_ILLEGAL_CMD_EN	BIT(2)
80 #define M_CMD_FAILURE_EN	BIT(3)
81 #define M_CMD_CANCEL_EN		BIT(4)
82 #define M_CMD_ABORT_EN		BIT(5)
83 #define M_TIMESTAMP_EN		BIT(6)
84 #define M_RX_IRQ_EN		BIT(7)
85 #define M_GP_SYNC_IRQ_0_EN	BIT(8)
86 #define M_GP_IRQ_0_EN		BIT(9)
87 #define M_GP_IRQ_1_EN		BIT(10)
88 #define M_GP_IRQ_2_EN		BIT(11)
89 #define M_GP_IRQ_3_EN		BIT(12)
90 #define M_GP_IRQ_4_EN		BIT(13)
91 #define M_GP_IRQ_5_EN		BIT(14)
92 #define M_IO_DATA_DEASSERT_EN	BIT(22)
93 #define M_IO_DATA_ASSERT_EN	BIT(23)
94 #define M_RX_FIFO_RD_ERR_EN	BIT(24)
95 #define M_RX_FIFO_WR_ERR_EN	BIT(25)
96 #define M_RX_FIFO_WATERMARK_EN	BIT(26)
97 #define M_RX_FIFO_LAST_EN	BIT(27)
98 #define M_TX_FIFO_RD_ERR_EN	BIT(28)
99 #define M_TX_FIFO_WR_ERR_EN	BIT(29)
100 #define M_TX_FIFO_WATERMARK_EN	BIT(30)
101 #define M_SEC_IRQ_EN		BIT(31)
102 #define M_COMMON_GENI_M_IRQ_EN	(QC_GENMASK(6, 1) | \
103 				M_IO_DATA_DEASSERT_EN | \
104 				M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
105 				M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
106 				M_TX_FIFO_WR_ERR_EN)
107 
108 /* GENI_S_IRQ_EN fields */
109 #define S_CMD_DONE_EN		BIT(0)
110 #define S_CMD_OVERRUN_EN	BIT(1)
111 #define S_ILLEGAL_CMD_EN	BIT(2)
112 #define S_CMD_FAILURE_EN	BIT(3)
113 #define S_CMD_CANCEL_EN		BIT(4)
114 #define S_CMD_ABORT_EN		BIT(5)
115 #define S_GP_SYNC_IRQ_0_EN	BIT(8)
116 #define S_GP_IRQ_0_EN		BIT(9)
117 #define S_GP_IRQ_1_EN		BIT(10)
118 #define S_GP_IRQ_2_EN		BIT(11)
119 #define S_GP_IRQ_3_EN		BIT(12)
120 #define S_GP_IRQ_4_EN		BIT(13)
121 #define S_GP_IRQ_5_EN		BIT(14)
122 #define S_IO_DATA_DEASSERT_EN	BIT(22)
123 #define S_IO_DATA_ASSERT_EN	BIT(23)
124 #define S_RX_FIFO_RD_ERR_EN	BIT(24)
125 #define S_RX_FIFO_WR_ERR_EN	BIT(25)
126 #define S_RX_FIFO_WATERMARK_EN	BIT(26)
127 #define S_RX_FIFO_LAST_EN	BIT(27)
128 #define S_COMMON_GENI_S_IRQ_EN	(QC_GENMASK(5, 1) | QC_GENMASK(13, 9) | \
129 				 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
130 
131 /*  GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
132 #define WATERMARK_MSK		QC_GENMASK(5, 0)
133 
134 /* GENI_TX_FIFO_STATUS fields */
135 #define TX_FIFO_WC		QC_GENMASK(27, 0)
136 
137 /*  GENI_RX_FIFO_STATUS fields */
138 #define RX_LAST			BIT(31)
139 #define RX_LAST_BYTE_VALID_MSK	QC_GENMASK(30, 28)
140 #define RX_LAST_BYTE_VALID_SHFT	28
141 #define RX_FIFO_WC_MSK		QC_GENMASK(24, 0)
142 
143 /* SE_IRQ_EN fields */
144 #define DMA_RX_IRQ_EN		BIT(0)
145 #define DMA_TX_IRQ_EN		BIT(1)
146 #define GENI_M_IRQ_EN		BIT(2)
147 #define GENI_S_IRQ_EN		BIT(3)
148 
149 /* SE_DMA_GENERAL_CFG */
150 #define DMA_RX_CLK_CGC_ON	BIT(0)
151 #define DMA_TX_CLK_CGC_ON	BIT(1)
152 #define DMA_AHB_SLV_CFG_ON	BIT(2)
153 #define AHB_SEC_SLV_CLK_CGC_ON	BIT(3)
154 #define DUMMY_RX_NON_BUFFERABLE	BIT(4)
155 #define RX_DMA_ZERO_PADDING_EN	BIT(5)
156 #define RX_DMA_IRQ_DELAY_MSK	QC_GENMASK(8, 6)
157 #define RX_DMA_IRQ_DELAY_SHFT	6
158 
159 #define DEFAULT_SE_CLK		(19200 * KHz)
160 #define GENI_DFS_IF_CFG_DFS_IF_EN_BMSK			BIT(0)
161 
162 /* FIFO BUFFER PARAMETERS */
163 #define BYTES_PER_FIFO_WORD	4
164 #define FIFO_WIDTH		32
165 #define FIFO_DEPTH		16
166 #define BITS_PER_WORD	8
167 #define TX_WATERMARK	1
168 
169 /* PACKING CONFIGURATION VECTOR */
170 
171 /* start_idx:x: Bit position to move
172  * direction:1: MSB to LSB
173  * len:7: Represents bits-per-word = 8
174  * stop:0: Till it's 1, FIFO bit shift continues
175  */
176 
177 /* Start_idx:7, direction:1, len:7, stop:0 */
178 #define PACK_VECTOR0	0x0FE
179 /* Start_idx:15, direction:1, len:7, stop:0 */
180 #define PACK_VECTOR1	0x1FE
181 /* Start_idx:23, direction:1, len:7, stop:0 */
182 #define PACK_VECTOR2	0x2FE
183 /* Start_idx:31, direction:1, len:7, stop:1 */
184 #define PACK_VECTOR3	0x3FF
185 
186 enum se_protocol {
187 	SE_PROTOCOL_SPI  = 1,
188 	SE_PROTOCOL_UART = 2,
189 	SE_PROTOCOL_I2C  = 3,
190 	SE_PROTOCOL_I3C  = 4,
191 	SE_PROTOCOL_MAX  = 5
192 };
193 
194 enum se_mode {
195 	NONE,
196 	GSI,
197 	FIFO,
198 	CPU_DMA,
199 	MIXED
200 };
201 
202 struct qup_regs {
203 	u32 geni_init_cfg_revision;
204 	u32 geni_s_init_cfg_revision;
205 	u8  _reserved1[0x10 - 0x08];
206 	u32 geni_general_cfg;
207 	u32 geni_rx_fifo_ctrl;
208 	u8  _reserved2[0x20 - 0x18];
209 	u32 geni_force_default_reg;
210 	u32 geni_output_ctrl;
211 	u32 geni_cgc_ctrl;
212 	u32 geni_char_cfg;
213 	u32 geni_char_data_n;
214 	u8  _reserved3[0x40 - 0x34];
215 	u32 geni_status;
216 	u32 geni_test_bus_ctrl;
217 	u32 geni_ser_m_clk_cfg;
218 	u32 geni_ser_s_clk_cfg;
219 	u32 geni_prog_rom_ctrl_reg;
220 	u8  _reserved4[0x60 - 0x54];
221 	u32 geni_clk_ctrl_ro;
222 	u32 fifo_if_disable_ro;
223 	u32 geni_fw_revision_ro;
224 	u32 geni_s_fw_revision_ro;
225 	u32 geni_fw_multilock_protns_ro;
226 	u32 geni_fw_multilock_msa_ro;
227 	u32 geni_fw_multilock_sp_ro;
228 	u32 geni_clk_sel;
229 	u32 geni_dfs_if_cfg;
230 	u8 _reserved5[0x100 - 0x084];
231 	u32 geni_cfg_reg0;
232 	u32 geni_cfg_reg1;
233 	u32 geni_cfg_reg2;
234 	u32 geni_cfg_reg3;
235 	u32 geni_cfg_reg4;
236 	u32 geni_cfg_reg5;
237 	u32 geni_cfg_reg6;
238 	u32 geni_cfg_reg7;
239 	u32 geni_cfg_reg8;
240 	u32 geni_cfg_reg9;
241 	u32 geni_cfg_reg10;
242 	u32 geni_cfg_reg11;
243 	u32 geni_cfg_reg12;
244 	u32 geni_cfg_reg13;
245 	u32 geni_cfg_reg14;
246 	u32 geni_cfg_reg15;
247 	u32 geni_cfg_reg16;
248 	u32 geni_cfg_reg17;
249 	u32 geni_cfg_reg18;
250 	u8  _reserved6[0x200 - 0x14C];
251 	u32 geni_cfg_reg64;
252 	u32 geni_cfg_reg65;
253 	u32 geni_cfg_reg66;
254 	u32 geni_cfg_reg67;
255 	u32 geni_cfg_reg68;
256 	u32 geni_cfg_reg69;
257 	u32 geni_cfg_reg70;
258 	u32 geni_cfg_reg71;
259 	u32 geni_cfg_reg72;
260 	u32 spi_cpha;
261 	u32 geni_cfg_reg74;
262 	u32 proto_loopback_cfg;
263 	u32 spi_cpol;
264 	u32 i2c_noise_cancellation_ctl;
265 	u32 i2c_monitor_ctl;
266 	u32 geni_cfg_reg79;
267 	u32 geni_cfg_reg80;
268 	u32 geni_cfg_reg81;
269 	u32 geni_cfg_reg82;
270 	u32 spi_demux_output_inv;
271 	u32 spi_demux_sel;
272 	u32 geni_byte_granularity;
273 	u32 geni_dma_mode_en;
274 	u32 uart_tx_trans_cfg_reg;
275 	u32 geni_tx_packing_cfg0;
276 	u32 geni_tx_packing_cfg1;
277 	union {
278 		u32 uart_tx_word_len;
279 		u32 spi_word_len;
280 	};
281 	union {
282 		u32 uart_tx_stop_bit_len;
283 		u32 i2c_tx_trans_len;
284 		u32 spi_tx_trans_len;
285 	};
286 	union {
287 		u32 uart_tx_trans_len;
288 		u32 i2c_rx_trans_len;
289 		u32 spi_rx_trans_len;
290 	};
291 	u32 spi_pre_post_cmd_dly;
292 	u32 i2c_scl_counters;
293 	u32 geni_cfg_reg95;
294 	u32 uart_rx_trans_cfg;
295 	u32 geni_rx_packing_cfg0;
296 	u32 geni_rx_packing_cfg1;
297 	u32 uart_rx_word_len;
298 	u32 geni_cfg_reg100;
299 	u32 uart_rx_stale_cnt;
300 	u32 geni_cfg_reg102;
301 	u32 geni_cfg_reg103;
302 	u32 geni_cfg_reg104;
303 	u32 uart_tx_parity_cfg;
304 	u32 uart_rx_parity_cfg;
305 	u32 uart_manual_rfr;
306 	u32 geni_cfg_reg108;
307 	u32 geni_cfg_reg109;
308 	u32 geni_cfg_reg110;
309 	u8 _reserved7[0x600 - 0x2BC];
310 	u32 geni_m_cmd0;
311 	u32 geni_m_cmd_ctrl_reg;
312 	u8  _reserved8[0x10 - 0x08];
313 	u32 geni_m_irq_status;
314 	u32 geni_m_irq_enable;
315 	u32 geni_m_irq_clear;
316 	u32 geni_m_irq_en_set;
317 	u32 geni_m_irq_en_clear;
318 	u32 geni_m_cmd_err_status;
319 	u32 geni_m_fw_err_status;
320 	u8  _reserved9[0x30 - 0x2C];
321 	u32 geni_s_cmd0;
322 	u32 geni_s_cmd_ctrl_reg;
323 	u8  _reserved10[0x40 - 0x38];
324 	u32 geni_s_irq_status;
325 	u32 geni_s_irq_enable;
326 	u32 geni_s_irq_clear;
327 	u32 geni_s_irq_en_set;
328 	u32 geni_s_irq_en_clear;
329 	u8  _reserved11[0x700 - 0x654];
330 	u32 geni_tx_fifon;
331 	u8  _reserved12[0x780 - 0x704];
332 	u32 geni_rx_fifon;
333 	u8  _reserved13[0x800 - 0x784];
334 	u32 geni_tx_fifo_status;
335 	u32 geni_rx_fifo_status;
336 	u32 geni_tx_fifo_threshold;
337 	u32 geni_tx_watermark_reg;
338 	u32 geni_rx_watermark_reg;
339 	u32 geni_rx_rfr_watermark_reg;
340 	u8  _reserved14[0x900 - 0x818];
341 	u32 geni_gp_output_reg;
342 	u8  _reserved15[0x908 - 0x904];
343 	u32 geni_ios;
344 	u32 geni_timestamp;
345 	u32 geni_m_gp_length;
346 	u32 geni_s_gp_length;
347 	u8  _reserved16[0x920 - 0x918];
348 	u32 geni_hw_irq_en;
349 	u32 geni_hw_irq_ignore_on_active;
350 	u8  _reserved17[0x930 - 0x928];
351 	u32 geni_hw_irq_cmd_param_0;
352 	u8  _reserved18[0xA00 - 0x934];
353 	u32 geni_i3c_ibi_cfg_tablen;
354 	u8  _reserved19[0xA80 - 0xA04];
355 	u32 geni_i3c_ibi_status;
356 	u32 geni_i3c_ibi_rd_data;
357 	u32 geni_i3c_ibi_search_pattern;
358 	u32 geni_i3c_ibi_search_data;
359 	u32 geni_i3c_sw_ibi_en;
360 	u32 geni_i3c_sw_ibi_en_recover;
361 	u8 _reserved20[0xC30 - 0xA98];
362 	u32 dma_tx_ptr_l;
363 	u32 dma_tx_ptr_h;
364 	u32 dma_tx_attr;
365 	u32 dma_tx_length;
366 	u32 dma_tx_irq_stat;
367 	u32 dma_tx_irq_clr;
368 	u32 dma_tx_irq_en;
369 	u32 dma_tx_irq_en_set;
370 	u32 dma_tx_irq_en_clr;
371 	u32 dma_tx_length_in;
372 	u32 dma_tx_fsm_rst;
373 	u32 dma_tx_max_burst_size;
374 	u8  _reserved21[0xD30 - 0xC60];
375 	u32 dma_rx_ptr_l;
376 	u32 dma_rx_ptr_h;
377 	u32 dma_rx_attr;
378 	u32 dma_rx_length;
379 	u32 dma_rx_irq_stat;
380 	u32 dma_rx_irq_clr;
381 	u32 dma_rx_irq_en;
382 	u32 dma_rx_irq_en_set;
383 	u32 dma_rx_irq_en_clr;
384 	u32 dma_rx_length_in;
385 	u32 dma_rx_fsm_rst;
386 	u32 dma_rx_max_burst_size;
387 	u32 dma_rx_flush;
388 	u8  _reserved22[0xE14 - 0xD64];
389 	u32 se_irq_high_priority;
390 	u32 se_gsi_event_en;
391 	u32 se_irq_en;
392 	u32 dma_if_en_ro;
393 	u32 se_hw_param_0;
394 	u32 se_hw_param_1;
395 	u32 se_hw_param_2;
396 	u32 dma_general_cfg;
397 	u8  _reserved23[0x40 - 0x34];
398 	u32 dma_debug_reg0;
399 	u32 dma_test_bus_ctrl;
400 	u32 se_top_test_bus_ctrl;
401 	u8 _reserved24[0x1000 - 0x0E4C];
402 	u32 se_geni_fw_revision;
403 	u32 se_s_fw_revision;
404 	u8 _reserved25[0x10-0x08];
405 	u32 se_geni_cfg_ramn;
406 	u8 _reserved26[0x2000 - 0x1014];
407 	u32 se_geni_clk_ctrl;
408 	u32 se_dma_if_en;
409 	u32 se_fifo_if_disable;
410 	u32 se_geni_fw_multilock_protns;
411 	u32 se_geni_fw_multilock_msa;
412 	u32 se_geni_fw_multilock_sp;
413 };
414 
415 
416 check_member(qup_regs, geni_clk_sel, 0x7C);
417 check_member(qup_regs, geni_cfg_reg108, 0x2B0);
418 check_member(qup_regs, geni_dma_mode_en, 0x258);
419 check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84);
420 check_member(qup_regs, dma_test_bus_ctrl, 0xE44);
421 check_member(qup_regs, se_geni_cfg_ramn, 0x1010);
422 check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014);
423 
424 
425 struct gsi_regs {
426 	u32 gsi_cfg;
427 	u8  _reserved1[0x8 - 0x4];
428 	u32 gsi_manager_mcs_code_ver;
429 	u8  _reserved2[0x14 - 0x10];
430 	u32 gsi_zeros;
431 	u8  _reserved3[0x18 - 0x14];
432 	u32 gsi_periph_base_lsb;
433 	u32 gsi_periph_base_msb;
434 	u8  _reserved4[0x60 - 0x20];
435 	u32 gsi_cgc_ctrl;
436 	u8  _reserved5[0x80 - 0x64];
437 	u32 gsi_msi_cacheattr;
438 	u8  _reserved6[0xB000 - 0x84];
439 	u32 gsi_mcs_cfg;
440 	u8  _reserved7[0xF018 - 0xB004];
441 	u32 ee_n_gsi_ee_generic_cmd;
442 	u8  _reserved8[0xF400 - 0xF01C];
443 	u32 gsi_ee_n_scratch_0_addr;
444 	u32 gsi_ee_n_scratch_1_addr;
445 	u8  _reserved9[0x4C000 - 0xF408];
446 	u32 gsi_inst_ramn;
447 	u8  _reserved10[0x4000];
448 };
449 
450 check_member(gsi_regs, gsi_manager_mcs_code_ver, 0x8);
451 check_member(gsi_regs, gsi_zeros, 0x10);
452 check_member(gsi_regs, gsi_periph_base_lsb, 0x18);
453 check_member(gsi_regs, gsi_cgc_ctrl, 0x60);
454 check_member(gsi_regs, ee_n_gsi_ee_generic_cmd, 0xF018);
455 check_member(gsi_regs, gsi_ee_n_scratch_0_addr, 0xF400);
456 check_member(gsi_regs, gsi_ee_n_scratch_1_addr, 0xF404);
457 check_member(gsi_regs, gsi_inst_ramn, 0x4C000);
458 
459 
460 u32 qup_wait_for_m_irq(unsigned int bus);
461 u32 qup_wait_for_s_irq(unsigned int bus);
462 void qup_m_cancel_and_abort(unsigned int bus);
463 void qup_s_cancel_and_abort(unsigned int bus);
464 int qup_handle_transfer(unsigned int bus, const void *dout, void *din,
465 	int size, struct stopwatch *timeout);
466 
467 #endif /* __SOC_COMMON_QCOM_QUP_SE_H__ */
468