1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
3
4 #ifndef _IXGBE_H_
5 #define _IXGBE_H_
6
7 #include <linux/bitops.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/netdevice.h>
11 #include <linux/cpumask.h>
12 #include <linux/if_vlan.h>
13 #include <linux/jiffies.h>
14 #include <linux/phy.h>
15
16 #include <linux/timecounter.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/ptp_clock_kernel.h>
19
20 #include "ixgbe_type.h"
21 #include "ixgbe_common.h"
22 #include "ixgbe_dcb.h"
23 #include "ixgbe_e610.h"
24 #if IS_ENABLED(CONFIG_FCOE)
25 #define IXGBE_FCOE
26 #include "ixgbe_fcoe.h"
27 #endif /* IS_ENABLED(CONFIG_FCOE) */
28 #ifdef CONFIG_IXGBE_DCA
29 #include <linux/dca.h>
30 #endif
31 #include "ixgbe_ipsec.h"
32
33 #include <net/xdp.h>
34
35 /* common prefix used by pr_<> macros */
36 #undef pr_fmt
37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38
39 /* TX/RX descriptor defines */
40 #define IXGBE_DEFAULT_TXD 512
41 #define IXGBE_DEFAULT_TX_WORK 256
42 #define IXGBE_MAX_TXD_82598 4096
43 #define IXGBE_MAX_TXD_82599 8192
44 #define IXGBE_MAX_TXD_X540 8192
45 #define IXGBE_MAX_TXD_X550 32768
46 #define IXGBE_MIN_TXD 64
47
48 #if (PAGE_SIZE < 8192)
49 #define IXGBE_DEFAULT_RXD 512
50 #else
51 #define IXGBE_DEFAULT_RXD 128
52 #endif
53 #define IXGBE_MAX_RXD_82598 4096
54 #define IXGBE_MAX_RXD_82599 8192
55 #define IXGBE_MAX_RXD_X540 8192
56 #define IXGBE_MAX_RXD_X550 32768
57 #define IXGBE_MIN_RXD 64
58
59 /* flow control */
60 #define IXGBE_MIN_FCRTL 0x40
61 #define IXGBE_MAX_FCRTL 0x7FF80
62 #define IXGBE_MIN_FCRTH 0x600
63 #define IXGBE_MAX_FCRTH 0x7FFF0
64 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
65 #define IXGBE_MIN_FCPAUSE 0
66 #define IXGBE_MAX_FCPAUSE 0xFFFF
67
68 /* Supported Rx Buffer Sizes */
69 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
70 #define IXGBE_RXBUFFER_1536 1536
71 #define IXGBE_RXBUFFER_2K 2048
72 #define IXGBE_RXBUFFER_3K 3072
73 #define IXGBE_RXBUFFER_4K 4096
74 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
75
76 #define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
77
78 /* Attempt to maximize the headroom available for incoming frames. We
79 * use a 2K buffer for receives and need 1536/1534 to store the data for
80 * the frame. This leaves us with 512 bytes of room. From that we need
81 * to deduct the space needed for the shared info and the padding needed
82 * to IP align the frame.
83 *
84 * Note: For cache line sizes 256 or larger this value is going to end
85 * up negative. In these cases we should fall back to the 3K
86 * buffers.
87 */
88 #if (PAGE_SIZE < 8192)
89 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN)
90 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \
91 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K))
92
ixgbe_compute_pad(int rx_buf_len)93 static inline int ixgbe_compute_pad(int rx_buf_len)
94 {
95 int page_size, pad_size;
96
97 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
98 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
99
100 return pad_size;
101 }
102
ixgbe_skb_pad(void)103 static inline int ixgbe_skb_pad(void)
104 {
105 int rx_buf_len;
106
107 /* If a 2K buffer cannot handle a standard Ethernet frame then
108 * optimize padding for a 3K buffer instead of a 1.5K buffer.
109 *
110 * For a 3K buffer we need to add enough padding to allow for
111 * tailroom due to NET_IP_ALIGN possibly shifting us out of
112 * cache-line alignment.
113 */
114 if (IXGBE_2K_TOO_SMALL_WITH_PADDING)
115 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN);
116 else
117 rx_buf_len = IXGBE_RXBUFFER_1536;
118
119 /* if needed make room for NET_IP_ALIGN */
120 rx_buf_len -= NET_IP_ALIGN;
121
122 return ixgbe_compute_pad(rx_buf_len);
123 }
124
125 #define IXGBE_SKB_PAD ixgbe_skb_pad()
126 #else
127 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
128 #endif
129
130 /*
131 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
132 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
133 * this adds up to 448 bytes of extra data.
134 *
135 * Since netdev_alloc_skb now allocates a page fragment we can use a value
136 * of 256 and the resultant skb will have a truesize of 960 or less.
137 */
138 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
139
140 /* How many Rx Buffers do we bundle into one write to the hardware ? */
141 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
142
143 #define IXGBE_RX_DMA_ATTR \
144 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
145
146 enum ixgbe_tx_flags {
147 /* cmd_type flags */
148 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
149 IXGBE_TX_FLAGS_TSO = 0x02,
150 IXGBE_TX_FLAGS_TSTAMP = 0x04,
151
152 /* olinfo flags */
153 IXGBE_TX_FLAGS_CC = 0x08,
154 IXGBE_TX_FLAGS_IPV4 = 0x10,
155 IXGBE_TX_FLAGS_CSUM = 0x20,
156 IXGBE_TX_FLAGS_IPSEC = 0x40,
157
158 /* software defined flags */
159 IXGBE_TX_FLAGS_SW_VLAN = 0x80,
160 IXGBE_TX_FLAGS_FCOE = 0x100,
161 };
162
163 /* VLAN info */
164 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
165 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
166 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
167 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
168
169 #define IXGBE_MAX_VF_MC_ENTRIES 30
170 #define IXGBE_MAX_VF_FUNCTIONS 64
171 #define IXGBE_MAX_VFTA_ENTRIES 128
172 #define MAX_EMULATION_MAC_ADDRS 16
173 #define IXGBE_MAX_PF_MACVLANS 15
174 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
175 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
176 #define IXGBE_X540_VF_DEVICE_ID 0x1515
177 #define IXGBE_E610_VF_DEVICE_ID 0x57AD
178
179 #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
180 { \
181 u32 current_counter = IXGBE_READ_REG(hw, reg); \
182 if (current_counter < last_counter) \
183 counter += 0x100000000LL; \
184 last_counter = current_counter; \
185 counter &= 0xFFFFFFFF00000000LL; \
186 counter |= current_counter; \
187 }
188
189 #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
190 { \
191 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
192 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
193 u64 current_counter = (current_counter_msb << 32) | \
194 current_counter_lsb; \
195 if (current_counter < last_counter) \
196 counter += 0x1000000000LL; \
197 last_counter = current_counter; \
198 counter &= 0xFFFFFFF000000000LL; \
199 counter |= current_counter; \
200 }
201
202 struct vf_stats {
203 u64 gprc;
204 u64 gorc;
205 u64 gptc;
206 u64 gotc;
207 u64 mprc;
208 };
209
210 struct vf_data_storage {
211 struct pci_dev *vfdev;
212 unsigned char vf_mac_addresses[ETH_ALEN];
213 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
214 u16 num_vf_mc_hashes;
215 bool clear_to_send;
216 struct vf_stats vfstats;
217 struct vf_stats last_vfstats;
218 struct vf_stats saved_rst_vfstats;
219 bool pf_set_mac;
220 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
221 u16 pf_qos;
222 u16 tx_rate;
223 int link_enable;
224 int link_state;
225 u8 spoofchk_enabled;
226 bool rss_query_enabled;
227 u8 trusted;
228 int xcast_mode;
229 unsigned int vf_api;
230 u8 primary_abort_count;
231 };
232
233 enum ixgbevf_xcast_modes {
234 IXGBEVF_XCAST_MODE_NONE = 0,
235 IXGBEVF_XCAST_MODE_MULTI,
236 IXGBEVF_XCAST_MODE_ALLMULTI,
237 IXGBEVF_XCAST_MODE_PROMISC,
238 };
239
240 struct vf_macvlans {
241 struct list_head l;
242 int vf;
243 bool free;
244 bool is_macvlan;
245 u8 vf_macvlan[ETH_ALEN];
246 };
247
248 #define IXGBE_MAX_TXD_PWR 14
249 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
250
251 /* Tx Descriptors needed, worst case */
252 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
253 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
254
255 /* wrapper around a pointer to a socket buffer,
256 * so a DMA handle can be stored along with the buffer */
257 struct ixgbe_tx_buffer {
258 union ixgbe_adv_tx_desc *next_to_watch;
259 unsigned long time_stamp;
260 union {
261 struct sk_buff *skb;
262 struct xdp_frame *xdpf;
263 };
264 unsigned int bytecount;
265 unsigned short gso_segs;
266 __be16 protocol;
267 DEFINE_DMA_UNMAP_ADDR(dma);
268 DEFINE_DMA_UNMAP_LEN(len);
269 u32 tx_flags;
270 };
271
272 struct ixgbe_rx_buffer {
273 union {
274 struct {
275 struct sk_buff *skb;
276 dma_addr_t dma;
277 struct page *page;
278 __u32 page_offset;
279 __u16 pagecnt_bias;
280 };
281 struct {
282 bool discard;
283 struct xdp_buff *xdp;
284 };
285 };
286 };
287
288 struct ixgbe_queue_stats {
289 u64 packets;
290 u64 bytes;
291 };
292
293 struct ixgbe_tx_queue_stats {
294 u64 restart_queue;
295 u64 tx_busy;
296 u64 tx_done_old;
297 };
298
299 struct ixgbe_rx_queue_stats {
300 u64 rsc_count;
301 u64 rsc_flush;
302 u64 non_eop_descs;
303 u64 alloc_rx_page;
304 u64 alloc_rx_page_failed;
305 u64 alloc_rx_buff_failed;
306 u64 csum_err;
307 };
308
309 #define IXGBE_TS_HDR_LEN 8
310
311 enum ixgbe_ring_state_t {
312 __IXGBE_RX_3K_BUFFER,
313 __IXGBE_RX_BUILD_SKB_ENABLED,
314 __IXGBE_RX_RSC_ENABLED,
315 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
316 __IXGBE_RX_FCOE,
317 __IXGBE_TX_FDIR_INIT_DONE,
318 __IXGBE_TX_XPS_INIT_DONE,
319 __IXGBE_TX_DETECT_HANG,
320 __IXGBE_HANG_CHECK_ARMED,
321 __IXGBE_TX_XDP_RING,
322 __IXGBE_TX_DISABLED,
323 };
324
325 #define ring_uses_build_skb(ring) \
326 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state)
327
328 struct ixgbe_fwd_adapter {
329 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
330 struct net_device *netdev;
331 unsigned int tx_base_queue;
332 unsigned int rx_base_queue;
333 int pool;
334 };
335
336 #define check_for_tx_hang(ring) \
337 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
338 #define set_check_for_tx_hang(ring) \
339 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
340 #define clear_check_for_tx_hang(ring) \
341 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
342 #define ring_is_rsc_enabled(ring) \
343 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
344 #define set_ring_rsc_enabled(ring) \
345 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
346 #define clear_ring_rsc_enabled(ring) \
347 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
348 #define ring_is_xdp(ring) \
349 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
350 #define set_ring_xdp(ring) \
351 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
352 #define clear_ring_xdp(ring) \
353 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
354 struct ixgbe_ring {
355 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
356 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
357 struct net_device *netdev; /* netdev ring belongs to */
358 struct bpf_prog *xdp_prog;
359 struct device *dev; /* device for DMA mapping */
360 void *desc; /* descriptor ring memory */
361 union {
362 struct ixgbe_tx_buffer *tx_buffer_info;
363 struct ixgbe_rx_buffer *rx_buffer_info;
364 };
365 unsigned long state;
366 u8 __iomem *tail;
367 dma_addr_t dma; /* phys. address of descriptor ring */
368 unsigned int size; /* length in bytes */
369
370 u16 count; /* amount of descriptors */
371
372 u8 queue_index; /* needed for multiqueue queue management */
373 u8 reg_idx; /* holds the special value that gets
374 * the hardware register offset
375 * associated with this ring, which is
376 * different for DCB and RSS modes
377 */
378 u16 next_to_use;
379 u16 next_to_clean;
380
381 unsigned long last_rx_timestamp;
382
383 union {
384 u16 next_to_alloc;
385 struct {
386 u8 atr_sample_rate;
387 u8 atr_count;
388 };
389 };
390
391 u8 dcb_tc;
392 struct ixgbe_queue_stats stats;
393 struct u64_stats_sync syncp;
394 union {
395 struct ixgbe_tx_queue_stats tx_stats;
396 struct ixgbe_rx_queue_stats rx_stats;
397 };
398 u16 rx_offset;
399 struct xdp_rxq_info xdp_rxq;
400 spinlock_t tx_lock; /* used in XDP mode */
401 struct xsk_buff_pool *xsk_pool;
402 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */
403 u16 rx_buf_len;
404 } ____cacheline_internodealigned_in_smp;
405
406 enum ixgbe_ring_f_enum {
407 RING_F_NONE = 0,
408 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
409 RING_F_RSS,
410 RING_F_FDIR,
411 #ifdef IXGBE_FCOE
412 RING_F_FCOE,
413 #endif /* IXGBE_FCOE */
414
415 RING_F_ARRAY_SIZE /* must be last in enum set */
416 };
417
418 #define IXGBE_MAX_RSS_INDICES 16
419 #define IXGBE_MAX_RSS_INDICES_X550 63
420 #define IXGBE_MAX_VMDQ_INDICES 64
421 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
422 #define IXGBE_MAX_FCOE_INDICES 8
423 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
424 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
425 #define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1)
426 #define IXGBE_MAX_L2A_QUEUES 4
427 #define IXGBE_BAD_L2A_QUEUE 3
428 #define IXGBE_MAX_MACVLANS 63
429
430 DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key);
431
432 struct ixgbe_ring_feature {
433 u16 limit; /* upper limit on feature indices */
434 u16 indices; /* current value of indices */
435 u16 mask; /* Mask used for feature to ring mapping */
436 u16 offset; /* offset to start of feature */
437 } ____cacheline_internodealigned_in_smp;
438
439 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
440 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
441 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
442
443 /*
444 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
445 * this is twice the size of a half page we need to double the page order
446 * for FCoE enabled Rx queues.
447 */
ixgbe_rx_bufsz(struct ixgbe_ring * ring)448 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
449 {
450 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
451 return IXGBE_RXBUFFER_3K;
452 #if (PAGE_SIZE < 8192)
453 if (ring_uses_build_skb(ring))
454 return IXGBE_MAX_2K_FRAME_BUILD_SKB;
455 #endif
456 return IXGBE_RXBUFFER_2K;
457 }
458
ixgbe_rx_pg_order(struct ixgbe_ring * ring)459 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
460 {
461 #if (PAGE_SIZE < 8192)
462 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
463 return 1;
464 #endif
465 return 0;
466 }
467 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
468
469 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2
470 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10
471 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126
472 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80
473 #define IXGBE_ITR_ADAPTIVE_BULK 0x00
474
475 struct ixgbe_ring_container {
476 struct ixgbe_ring *ring; /* pointer to linked list of rings */
477 unsigned long next_update; /* jiffies value of last update */
478 unsigned int total_bytes; /* total bytes processed this int */
479 unsigned int total_packets; /* total packets processed this int */
480 u16 work_limit; /* total work allowed per interrupt */
481 u8 count; /* total number of rings in vector */
482 u8 itr; /* current ITR setting for ring */
483 };
484
485 /* iterator for handling rings in ring container */
486 #define ixgbe_for_each_ring(pos, head) \
487 for (pos = (head).ring; pos != NULL; pos = pos->next)
488
489 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
490 ? 8 : 1)
491 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
492
493 /* MAX_Q_VECTORS of these are allocated,
494 * but we only use one per queue-specific vector.
495 */
496 struct ixgbe_q_vector {
497 struct ixgbe_adapter *adapter;
498 #ifdef CONFIG_IXGBE_DCA
499 int cpu; /* CPU for DCA */
500 #endif
501 u16 v_idx; /* index of q_vector within array, also used for
502 * finding the bit in EICR and friends that
503 * represents the vector for this ring */
504 u16 itr; /* Interrupt throttle rate written to EITR */
505 struct ixgbe_ring_container rx, tx;
506
507 struct napi_struct napi;
508 cpumask_t affinity_mask;
509 int numa_node;
510 struct rcu_head rcu; /* to avoid race with update stats on free */
511 char name[IFNAMSIZ + 9];
512
513 /* for dynamic allocation of rings associated with this q_vector */
514 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp;
515 };
516
517 #ifdef CONFIG_IXGBE_HWMON
518
519 #define IXGBE_HWMON_TYPE_LOC 0
520 #define IXGBE_HWMON_TYPE_TEMP 1
521 #define IXGBE_HWMON_TYPE_CAUTION 2
522 #define IXGBE_HWMON_TYPE_MAX 3
523
524 struct hwmon_attr {
525 struct device_attribute dev_attr;
526 struct ixgbe_hw *hw;
527 struct ixgbe_thermal_diode_data *sensor;
528 char name[12];
529 };
530
531 struct hwmon_buff {
532 struct attribute_group group;
533 const struct attribute_group *groups[2];
534 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
535 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
536 unsigned int n_hwmon;
537 };
538 #endif /* CONFIG_IXGBE_HWMON */
539
540 /*
541 * microsecond values for various ITR rates shifted by 2 to fit itr register
542 * with the first 3 bits reserved 0
543 */
544 #define IXGBE_MIN_RSC_ITR 24
545 #define IXGBE_100K_ITR 40
546 #define IXGBE_20K_ITR 200
547 #define IXGBE_12K_ITR 336
548
549 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
ixgbe_test_staterr(union ixgbe_adv_rx_desc * rx_desc,const u32 stat_err_bits)550 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
551 const u32 stat_err_bits)
552 {
553 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
554 }
555
ixgbe_desc_unused(struct ixgbe_ring * ring)556 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
557 {
558 u16 ntc = ring->next_to_clean;
559 u16 ntu = ring->next_to_use;
560
561 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
562 }
563
564 #define IXGBE_RX_DESC(R, i) \
565 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
566 #define IXGBE_TX_DESC(R, i) \
567 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
568 #define IXGBE_TX_CTXTDESC(R, i) \
569 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
570
571 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
572 #ifdef IXGBE_FCOE
573 /* Use 3K as the baby jumbo frame size for FCoE */
574 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
575 #endif /* IXGBE_FCOE */
576
577 #define OTHER_VECTOR 1
578 #define NON_Q_VECTORS (OTHER_VECTOR)
579
580 #define MAX_MSIX_VECTORS_82599 64
581 #define MAX_Q_VECTORS_82599 64
582 #define MAX_MSIX_VECTORS_82598 18
583 #define MAX_Q_VECTORS_82598 16
584
585 struct ixgbe_mac_addr {
586 u8 addr[ETH_ALEN];
587 u16 pool;
588 u16 state; /* bitmask */
589 };
590
591 #define IXGBE_MAC_STATE_DEFAULT 0x1
592 #define IXGBE_MAC_STATE_MODIFIED 0x2
593 #define IXGBE_MAC_STATE_IN_USE 0x4
594
595 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
596 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
597
598 #define MIN_MSIX_Q_VECTORS 1
599 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
600
601 /* default to trying for four seconds */
602 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
603 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
604
605 #define IXGBE_PRIMARY_ABORT_LIMIT 5
606
607 /* board specific private data structure */
608 struct ixgbe_adapter {
609 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
610 /* OS defined structs */
611 struct net_device *netdev;
612 struct bpf_prog *xdp_prog;
613 struct pci_dev *pdev;
614 struct mii_bus *mii_bus;
615
616 unsigned long state;
617
618 /* Some features need tri-state capability,
619 * thus the additional *_CAPABLE flags.
620 */
621 u32 flags;
622 #define IXGBE_FLAG_MSI_ENABLED BIT(1)
623 #define IXGBE_FLAG_MSIX_ENABLED BIT(3)
624 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
625 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
626 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
627 #define IXGBE_FLAG_DCA_ENABLED BIT(8)
628 #define IXGBE_FLAG_DCA_CAPABLE BIT(9)
629 #define IXGBE_FLAG_IMIR_ENABLED BIT(10)
630 #define IXGBE_FLAG_MQ_CAPABLE BIT(11)
631 #define IXGBE_FLAG_DCB_ENABLED BIT(12)
632 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
633 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
634 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
635 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
636 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
637 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
638 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
639 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
640 #define IXGBE_FLAG_FCOE_ENABLED BIT(21)
641 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
642 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
643 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
644 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
645 #define IXGBE_FLAG_DCB_CAPABLE BIT(27)
646
647 u32 flags2;
648 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
649 #define IXGBE_FLAG2_RSC_ENABLED BIT(1)
650 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
651 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
652 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
653 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
654 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
655 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
656 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
657 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
658 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
659 #define IXGBE_FLAG2_FW_ASYNC_EVENT BIT(12)
660 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
661 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14)
662 #define IXGBE_FLAG2_EEE_ENABLED BIT(15)
663 #define IXGBE_FLAG2_RX_LEGACY BIT(16)
664 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17)
665 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18)
666 #define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19)
667 #define IXGBE_FLAG2_PHY_FW_LOAD_FAILED BIT(20)
668 #define IXGBE_FLAG2_NO_MEDIA BIT(21)
669 #define IXGBE_FLAG2_MOD_POWER_UNSUPPORTED BIT(22)
670
671 /* Tx fast path data */
672 int num_tx_queues;
673 u16 tx_itr_setting;
674 u16 tx_work_limit;
675 u64 tx_ipsec;
676
677 /* Rx fast path data */
678 int num_rx_queues;
679 u16 rx_itr_setting;
680 u64 rx_ipsec;
681
682 /* Port number used to identify VXLAN traffic */
683 __be16 vxlan_port;
684 __be16 geneve_port;
685
686 /* XDP */
687 int num_xdp_queues;
688 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS];
689 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */
690
691 /* TX */
692 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
693
694 u64 restart_queue;
695 u64 lsc_int;
696 u32 tx_timeout_count;
697
698 /* RX */
699 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
700 int num_rx_pools; /* == num_rx_queues in 82598 */
701 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
702 u64 hw_csum_rx_error;
703 u64 hw_rx_no_dma_resources;
704 u64 rsc_total_count;
705 u64 rsc_total_flush;
706 u64 non_eop_descs;
707 u32 alloc_rx_page;
708 u32 alloc_rx_page_failed;
709 u32 alloc_rx_buff_failed;
710
711 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
712
713 /* DCB parameters */
714 struct ieee_pfc *ixgbe_ieee_pfc;
715 struct ieee_ets *ixgbe_ieee_ets;
716 struct ixgbe_dcb_config dcb_cfg;
717 struct ixgbe_dcb_config temp_dcb_cfg;
718 u8 hw_tcs;
719 u8 dcb_set_bitmap;
720 u8 dcbx_cap;
721 enum ixgbe_fc_mode last_lfc_mode;
722
723 int num_q_vectors; /* current number of q_vectors for device */
724 int max_q_vectors; /* true count of q_vectors for device */
725 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
726 struct msix_entry *msix_entries;
727
728 u32 test_icr;
729 struct ixgbe_ring test_tx_ring;
730 struct ixgbe_ring test_rx_ring;
731
732 /* structs defined in ixgbe_hw.h */
733 struct ixgbe_hw hw;
734 u16 msg_enable;
735 struct ixgbe_hw_stats stats;
736
737 u64 tx_busy;
738 unsigned int tx_ring_count;
739 unsigned int xdp_ring_count;
740 unsigned int rx_ring_count;
741
742 u32 link_speed;
743 bool link_up;
744 unsigned long sfp_poll_time;
745 unsigned long link_check_timeout;
746
747 struct timer_list service_timer;
748 struct work_struct service_task;
749
750 struct hlist_head fdir_filter_list;
751 unsigned long fdir_overflow; /* number of times ATR was backed off */
752 union ixgbe_atr_input fdir_mask;
753 int fdir_filter_count;
754 u32 fdir_pballoc;
755 u32 atr_sample_rate;
756 spinlock_t fdir_perfect_lock;
757
758 #ifdef IXGBE_FCOE
759 struct ixgbe_fcoe fcoe;
760 #endif /* IXGBE_FCOE */
761 u8 __iomem *io_addr; /* Mainly for iounmap use */
762 u32 wol;
763
764 u16 bridge_mode;
765
766 char eeprom_id[NVM_VER_SIZE];
767 u16 eeprom_cap;
768
769 u32 interrupt_event;
770 u32 led_reg;
771
772 struct ptp_clock *ptp_clock;
773 struct ptp_clock_info ptp_caps;
774 struct work_struct ptp_tx_work;
775 struct sk_buff *ptp_tx_skb;
776 struct hwtstamp_config tstamp_config;
777 unsigned long ptp_tx_start;
778 unsigned long last_overflow_check;
779 unsigned long last_rx_ptp_check;
780 unsigned long last_rx_timestamp;
781 spinlock_t tmreg_lock;
782 struct cyclecounter hw_cc;
783 struct timecounter hw_tc;
784 u32 base_incval;
785 u32 tx_hwtstamp_timeouts;
786 u32 tx_hwtstamp_skipped;
787 u32 rx_hwtstamp_cleared;
788 void (*ptp_setup_sdp)(struct ixgbe_adapter *);
789
790 /* SR-IOV */
791 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
792 unsigned int num_vfs;
793 struct vf_data_storage *vfinfo;
794 int vf_rate_link_speed;
795 struct vf_macvlans vf_mvs;
796 struct vf_macvlans *mv_list;
797
798 u32 timer_event_accumulator;
799 u32 vferr_refcount;
800 struct ixgbe_mac_addr *mac_table;
801 struct kobject *info_kobj;
802 u16 lse_mask;
803 #ifdef CONFIG_IXGBE_HWMON
804 struct hwmon_buff *ixgbe_hwmon_buff;
805 #endif /* CONFIG_IXGBE_HWMON */
806 #ifdef CONFIG_DEBUG_FS
807 struct dentry *ixgbe_dbg_adapter;
808 #endif /*CONFIG_DEBUG_FS*/
809
810 u8 default_up;
811 /* Bitmask indicating in use pools */
812 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1);
813
814 #define IXGBE_MAX_LINK_HANDLE 10
815 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
816 unsigned long tables;
817
818 /* maximum number of RETA entries among all devices supported by ixgbe
819 * driver: currently it's x550 device in non-SRIOV mode
820 */
821 #define IXGBE_MAX_RETA_ENTRIES 512
822 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
823
824 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
825 u32 *rss_key;
826
827 #ifdef CONFIG_IXGBE_IPSEC
828 struct ixgbe_ipsec *ipsec;
829 #endif /* CONFIG_IXGBE_IPSEC */
830 spinlock_t vfs_lock;
831 };
832
ixgbe_determine_xdp_q_idx(int cpu)833 static inline int ixgbe_determine_xdp_q_idx(int cpu)
834 {
835 if (static_key_enabled(&ixgbe_xdp_locking_key))
836 return cpu % IXGBE_MAX_XDP_QS;
837 else
838 return cpu;
839 }
840
841 static inline
ixgbe_determine_xdp_ring(struct ixgbe_adapter * adapter)842 struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter)
843 {
844 int index = ixgbe_determine_xdp_q_idx(smp_processor_id());
845
846 return adapter->xdp_ring[index];
847 }
848
ixgbe_max_rss_indices(struct ixgbe_adapter * adapter)849 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
850 {
851 switch (adapter->hw.mac.type) {
852 case ixgbe_mac_82598EB:
853 case ixgbe_mac_82599EB:
854 case ixgbe_mac_X540:
855 return IXGBE_MAX_RSS_INDICES;
856 case ixgbe_mac_X550:
857 case ixgbe_mac_X550EM_x:
858 case ixgbe_mac_x550em_a:
859 case ixgbe_mac_e610:
860 return IXGBE_MAX_RSS_INDICES_X550;
861 default:
862 return 0;
863 }
864 }
865
866 struct ixgbe_fdir_filter {
867 struct hlist_node fdir_node;
868 union ixgbe_atr_input filter;
869 u16 sw_idx;
870 u64 action;
871 };
872
873 enum ixgbe_state_t {
874 __IXGBE_TESTING,
875 __IXGBE_RESETTING,
876 __IXGBE_DOWN,
877 __IXGBE_DISABLED,
878 __IXGBE_REMOVING,
879 __IXGBE_SERVICE_SCHED,
880 __IXGBE_SERVICE_INITED,
881 __IXGBE_IN_SFP_INIT,
882 __IXGBE_PTP_RUNNING,
883 __IXGBE_PTP_TX_IN_PROGRESS,
884 __IXGBE_RESET_REQUESTED,
885 __IXGBE_PHY_INIT_COMPLETE,
886 };
887
888 struct ixgbe_cb {
889 union { /* Union defining head/tail partner */
890 struct sk_buff *head;
891 struct sk_buff *tail;
892 };
893 dma_addr_t dma;
894 u16 append_cnt;
895 bool page_released;
896 };
897 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
898
899 enum ixgbe_boards {
900 board_82598,
901 board_82599,
902 board_X540,
903 board_X550,
904 board_X550EM_x,
905 board_x550em_x_fw,
906 board_x550em_a,
907 board_x550em_a_fw,
908 board_e610,
909 };
910
911 extern const struct ixgbe_info ixgbe_82598_info;
912 extern const struct ixgbe_info ixgbe_82599_info;
913 extern const struct ixgbe_info ixgbe_X540_info;
914 extern const struct ixgbe_info ixgbe_X550_info;
915 extern const struct ixgbe_info ixgbe_X550EM_x_info;
916 extern const struct ixgbe_info ixgbe_x550em_x_fw_info;
917 extern const struct ixgbe_info ixgbe_x550em_a_info;
918 extern const struct ixgbe_info ixgbe_x550em_a_fw_info;
919 extern const struct ixgbe_info ixgbe_e610_info;
920 #ifdef CONFIG_IXGBE_DCB
921 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops;
922 #endif
923
924 extern char ixgbe_driver_name[];
925 #ifdef IXGBE_FCOE
926 extern char ixgbe_default_device_descr[];
927 #endif /* IXGBE_FCOE */
928
929 int ixgbe_open(struct net_device *netdev);
930 int ixgbe_close(struct net_device *netdev);
931 void ixgbe_up(struct ixgbe_adapter *adapter);
932 void ixgbe_down(struct ixgbe_adapter *adapter);
933 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
934 void ixgbe_reset(struct ixgbe_adapter *adapter);
935 void ixgbe_set_ethtool_ops(struct net_device *netdev);
936 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
937 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
938 void ixgbe_free_rx_resources(struct ixgbe_ring *);
939 void ixgbe_free_tx_resources(struct ixgbe_ring *);
940 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
941 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
942 void ixgbe_disable_rx(struct ixgbe_adapter *adapter);
943 void ixgbe_disable_tx(struct ixgbe_adapter *adapter);
944 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
945 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
946 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
947 u16 subdevice_id);
948 #ifdef CONFIG_PCI_IOV
949 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
950 #endif
951 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
952 const u8 *addr, u16 queue);
953 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
954 const u8 *addr, u16 queue);
955 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
956 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
957 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
958 struct ixgbe_ring *);
959 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
960 void ixgbe_write_eitr(struct ixgbe_q_vector *);
961 int ixgbe_poll(struct napi_struct *napi, int budget);
962 int ethtool_ioctl(struct ifreq *ifr);
963 int ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
964 int ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
965 int ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
966 int ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
967 union ixgbe_atr_hash_dword input,
968 union ixgbe_atr_hash_dword common,
969 u8 queue);
970 int ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
971 union ixgbe_atr_input *input_mask);
972 int ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
973 union ixgbe_atr_input *input,
974 u16 soft_id, u8 queue);
975 int ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
976 union ixgbe_atr_input *input,
977 u16 soft_id);
978 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
979 union ixgbe_atr_input *mask);
980 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
981 struct ixgbe_fdir_filter *input,
982 u16 sw_idx);
983 void ixgbe_set_rx_mode(struct net_device *netdev);
984 #ifdef CONFIG_IXGBE_DCB
985 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
986 #endif
987 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
988 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
989 void ixgbe_do_reset(struct net_device *netdev);
990 #ifdef CONFIG_IXGBE_HWMON
991 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
992 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
993 #endif /* CONFIG_IXGBE_HWMON */
994 #ifdef IXGBE_FCOE
995 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
996 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
997 u8 *hdr_len);
998 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
999 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
1000 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
1001 struct scatterlist *sgl, unsigned int sgc);
1002 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
1003 struct scatterlist *sgl, unsigned int sgc);
1004 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
1005 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
1006 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
1007 int ixgbe_fcoe_enable(struct net_device *netdev);
1008 int ixgbe_fcoe_disable(struct net_device *netdev);
1009 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
1010 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
1011 struct netdev_fcoe_hbainfo *info);
1012 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
1013 #endif /* IXGBE_FCOE */
1014 #ifdef CONFIG_DEBUG_FS
1015 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
1016 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
1017 void ixgbe_dbg_init(void);
1018 void ixgbe_dbg_exit(void);
1019 #else
ixgbe_dbg_adapter_init(struct ixgbe_adapter * adapter)1020 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_adapter_exit(struct ixgbe_adapter * adapter)1021 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_init(void)1022 static inline void ixgbe_dbg_init(void) {}
ixgbe_dbg_exit(void)1023 static inline void ixgbe_dbg_exit(void) {}
1024 #endif /* CONFIG_DEBUG_FS */
txring_txq(const struct ixgbe_ring * ring)1025 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
1026 {
1027 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
1028 }
1029
1030 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
1031 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
1032 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
1033 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
1034 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
1035 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter);
1036 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
1037 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1038 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
1039 union ixgbe_adv_rx_desc *rx_desc,
1040 struct sk_buff *skb)
1041 {
1042 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
1043 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
1044 return;
1045 }
1046
1047 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1048 return;
1049
1050 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
1051
1052 /* Update the last_rx_timestamp timer in order to enable watchdog check
1053 * for error case of latched timestamp on a dropped packet.
1054 */
1055 rx_ring->last_rx_timestamp = jiffies;
1056 }
1057
1058 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1059 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1060 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
1061 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
1062 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
1063 #ifdef CONFIG_PCI_IOV
1064 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
1065 #endif
1066
1067 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
1068 struct ixgbe_adapter *adapter,
1069 struct ixgbe_ring *tx_ring);
1070 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
1071 void ixgbe_store_key(struct ixgbe_adapter *adapter);
1072 void ixgbe_store_reta(struct ixgbe_adapter *adapter);
1073 int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1074 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
1075 #ifdef CONFIG_IXGBE_IPSEC
1076 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
1077 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter);
1078 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter);
1079 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1080 union ixgbe_adv_rx_desc *rx_desc,
1081 struct sk_buff *skb);
1082 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
1083 struct ixgbe_ipsec_tx_data *itd);
1084 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf);
1085 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1086 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1087 #else
ixgbe_init_ipsec_offload(struct ixgbe_adapter * adapter)1088 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { }
ixgbe_stop_ipsec_offload(struct ixgbe_adapter * adapter)1089 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { }
ixgbe_ipsec_restore(struct ixgbe_adapter * adapter)1090 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { }
ixgbe_ipsec_rx(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1091 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1092 union ixgbe_adv_rx_desc *rx_desc,
1093 struct sk_buff *skb) { }
ixgbe_ipsec_tx(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,struct ixgbe_ipsec_tx_data * itd)1094 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring,
1095 struct ixgbe_tx_buffer *first,
1096 struct ixgbe_ipsec_tx_data *itd) { return 0; }
ixgbe_ipsec_vf_clear(struct ixgbe_adapter * adapter,u32 vf)1097 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter,
1098 u32 vf) { }
ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter * adapter,u32 * mbuf,u32 vf)1099 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter,
1100 u32 *mbuf, u32 vf) { return -EACCES; }
ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter * adapter,u32 * mbuf,u32 vf)1101 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter,
1102 u32 *mbuf, u32 vf) { return -EACCES; }
1103 #endif /* CONFIG_IXGBE_IPSEC */
1104
ixgbe_enabled_xdp_adapter(struct ixgbe_adapter * adapter)1105 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter)
1106 {
1107 return !!adapter->xdp_prog;
1108 }
1109
1110 #endif /* _IXGBE_H_ */
1111