1 /*
2 * Copyright © 2016 Rob Clark <[email protected]>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <[email protected]>
7 */
8
9 #include "pipe/p_state.h"
10 #include "util/u_memory.h"
11 #include "util/u_prim.h"
12 #include "util/u_string.h"
13
14 #include "freedreno_resource.h"
15 #include "freedreno_state.h"
16
17 #include "fd5_context.h"
18 #include "fd5_draw.h"
19 #include "fd5_emit.h"
20 #include "fd5_format.h"
21 #include "fd5_program.h"
22 #include "fd5_zsa.h"
23
24 static void
draw_impl(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit,unsigned index_offset)25 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
26 struct fd5_emit *emit, unsigned index_offset) assert_dt
27 {
28 const struct pipe_draw_info *info = emit->info;
29 enum pc_di_primtype primtype = ctx->screen->primtypes[info->mode];
30
31 fd5_emit_state(ctx, ring, emit);
32
33 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
34 fd5_emit_vertex_bufs(ring, emit);
35
36 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
37 OUT_RING(ring, info->index_size ? emit->draw->index_bias
38 : emit->draw->start); /* VFD_INDEX_OFFSET */
39 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
40
41 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
42 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
43 info->restart_index
44 : 0xffffffff);
45
46 fd5_emit_render_cntl(ctx, false, emit->binning_pass);
47 fd5_draw_emit(ctx->batch, ring, primtype,
48 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, info,
49 emit->indirect, emit->draw, index_offset);
50 }
51
52 static bool
fd5_draw_vbo(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draw,unsigned index_offset)53 fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
54 unsigned drawid_offset,
55 const struct pipe_draw_indirect_info *indirect,
56 const struct pipe_draw_start_count_bias *draw,
57 unsigned index_offset) in_dt
58 {
59 struct fd5_emit emit = {
60 .debug = &ctx->debug,
61 .vtx = &ctx->vtx,
62 .info = info,
63 .drawid_offset = drawid_offset,
64 .indirect = indirect,
65 .draw = draw,
66 .key = {
67 .vs = ctx->prog.vs,
68 .fs = ctx->prog.fs,
69 .key = {
70 .rasterflat = ctx->rasterizer->flatshade,
71 },
72 .clip_plane_enable = ctx->rasterizer->clip_plane_enable,
73 },
74 .rasterflat = ctx->rasterizer->flatshade,
75 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
76 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
77 };
78
79 ir3_fixup_shader_state(&ctx->base, &emit.key.key);
80
81 unsigned dirty = ctx->dirty;
82
83 emit.prog = fd5_program_state(
84 ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
85
86 /* bail if compile failed: */
87 if (!emit.prog)
88 return false;
89
90 fd_blend_tracking(ctx);
91
92 const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
93 const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
94
95 ir3_update_max_tf_vtx(ctx, vp);
96
97 /* do regular pass first: */
98
99 if (unlikely(ctx->stats_users > 0)) {
100 ctx->stats.vs_regs += ir3_shader_halfregs(vp);
101 ctx->stats.fs_regs += ir3_shader_halfregs(fp);
102 }
103
104 /* figure out whether we need to disable LRZ write for binning
105 * pass using draw pass's fp:
106 */
107 emit.no_lrz_write = fp->writes_pos || fp->no_earlyz || fp->has_kill;
108
109 emit.binning_pass = false;
110 emit.dirty = dirty;
111
112 draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
113
114 /* and now binning pass: */
115 emit.binning_pass = true;
116 emit.dirty = dirty & ~(FD_DIRTY_BLEND);
117 emit.vs = NULL; /* we changed key so need to refetch vp */
118 emit.fs = NULL;
119 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
120
121 if (emit.streamout_mask) {
122 struct fd_ringbuffer *ring = ctx->batch->draw;
123
124 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
125 if (emit.streamout_mask & (1 << i)) {
126 fd5_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
127 }
128 }
129 }
130
131 fd_context_all_clean(ctx);
132
133 return true;
134 }
135
136 static void
fd5_draw_vbos(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,unsigned index_offset)137 fd5_draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
138 unsigned drawid_offset,
139 const struct pipe_draw_indirect_info *indirect,
140 const struct pipe_draw_start_count_bias *draws,
141 unsigned num_draws,
142 unsigned index_offset)
143 assert_dt
144 {
145 for (unsigned i = 0; i < num_draws; i++)
146 fd5_draw_vbo(ctx, info, drawid_offset, indirect, &draws[i], index_offset);
147 }
148
149 static void
fd5_clear_lrz(struct fd_batch * batch,struct fd_resource * zsbuf,double depth)150 fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
151 {
152 struct fd_ringbuffer *ring;
153 uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
154
155 ring = fd_batch_get_prologue(batch);
156
157 OUT_WFI5(ring);
158
159 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
160 OUT_RING(ring, 0x10000000);
161
162 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
163 OUT_RING(ring, 0x20fffff);
164
165 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
166 OUT_RING(ring,
167 A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0f) |
168 A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples > 1 ?
169 RECTANGULAR : BRESENHAM));
170
171 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
172 OUT_RING(ring, 0x00000000);
173
174 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
175 OUT_RING(ring, 0x00000181);
176
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
178 OUT_RING(ring, 0x00000000);
179
180 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
181 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
182 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
183 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
184 OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
185 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
186 OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
187
188 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
189 OUT_RING(ring, 0x00000000);
190
191 OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1);
192 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
193
194 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
195 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
196
197 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
198 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
199
200 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
201 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
202
203 OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2);
204 OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
205 A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
206 OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
207
208 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
209 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
210
211 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
212 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | A5XX_RB_RESOLVE_CNTL_1_Y(0));
213 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
214 A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
215
216 fd5_emit_blit(batch, ring);
217 }
218
219 static bool
fd5_clear(struct fd_context * ctx,enum fd_buffer_mask buffers,const union pipe_color_union * color,double depth,unsigned stencil)220 fd5_clear(struct fd_context *ctx, enum fd_buffer_mask buffers,
221 const union pipe_color_union *color, double depth,
222 unsigned stencil) assert_dt
223 {
224 struct fd_ringbuffer *ring = ctx->batch->draw;
225 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
226
227 if ((buffers & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) &&
228 is_z32(pfb->zsbuf->format))
229 return false;
230
231 fd5_emit_render_cntl(ctx, true, false);
232
233 if (buffers & FD_BUFFER_COLOR) {
234 for (int i = 0; i < pfb->nr_cbufs; i++) {
235 union util_color uc = {0};
236
237 if (!pfb->cbufs[i])
238 continue;
239
240 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
241 continue;
242
243 enum pipe_format pfmt = pfb->cbufs[i]->format;
244
245 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
246 union pipe_color_union swapped;
247 switch (fd5_pipe2swap(pfmt)) {
248 case WZYX:
249 swapped.ui[0] = color->ui[0];
250 swapped.ui[1] = color->ui[1];
251 swapped.ui[2] = color->ui[2];
252 swapped.ui[3] = color->ui[3];
253 break;
254 case WXYZ:
255 swapped.ui[2] = color->ui[0];
256 swapped.ui[1] = color->ui[1];
257 swapped.ui[0] = color->ui[2];
258 swapped.ui[3] = color->ui[3];
259 break;
260 case ZYXW:
261 swapped.ui[3] = color->ui[0];
262 swapped.ui[0] = color->ui[1];
263 swapped.ui[1] = color->ui[2];
264 swapped.ui[2] = color->ui[3];
265 break;
266 case XYZW:
267 swapped.ui[3] = color->ui[0];
268 swapped.ui[2] = color->ui[1];
269 swapped.ui[1] = color->ui[2];
270 swapped.ui[0] = color->ui[3];
271 break;
272 }
273
274 util_pack_color_union(pfmt, &uc, &swapped);
275
276 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
277 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
278
279 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
280 OUT_RING(ring,
281 A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
282
283 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
284 OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
285 OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
286 OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
287 OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */
288
289 fd5_emit_blit(ctx->batch, ring);
290 }
291 }
292
293 if (pfb->zsbuf && (buffers & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))) {
294 uint32_t clear = util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
295 uint32_t mask = 0;
296
297 if (buffers & FD_BUFFER_DEPTH)
298 mask |= 0x1;
299
300 if (buffers & FD_BUFFER_STENCIL)
301 mask |= 0x2;
302
303 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
304 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
305
306 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
307 OUT_RING(ring,
308 A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(mask));
309
310 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
311 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
312
313 fd5_emit_blit(ctx->batch, ring);
314
315 if (pfb->zsbuf && (buffers & FD_BUFFER_DEPTH)) {
316 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
317 if (zsbuf->lrz) {
318 zsbuf->lrz_valid = true;
319 fd5_clear_lrz(ctx->batch, zsbuf, depth);
320 }
321 }
322 }
323
324 /* disable fast clear to not interfere w/ gmem->mem, etc.. */
325 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
326 OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */
327
328 return true;
329 }
330
331 void
fd5_draw_init(struct pipe_context * pctx)332 fd5_draw_init(struct pipe_context *pctx) disable_thread_safety_analysis
333 {
334 struct fd_context *ctx = fd_context(pctx);
335 ctx->draw_vbos = fd5_draw_vbos;
336 ctx->clear = fd5_clear;
337 }
338