1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8183_SPM_H 4 #define SOC_MEDIATEK_MT8183_SPM_H 5 6 #include <soc/addressmap.h> 7 #include <soc/mtcmos.h> 8 #include <types.h> 9 10 /* SPM READ/WRITE CFG */ 11 #define SPM_PROJECT_CODE 0xb16 12 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 13 14 /* POWERON_CONFIG_EN (0x10006000+0x000) */ 15 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 16 #define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ 17 #define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ 18 #define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ 19 20 /* SPM_CLK_CON (0x10006000+0x00C) */ 21 #define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ 22 #define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ 23 #define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 24 #define EXT_SRCCLKEN_MASK (1U << 6) /* 1b */ 25 #define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ 26 #define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 27 #define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ 28 29 /* PCM_CON0 (0x10006000+0x018) */ 30 #define PCM_KICK_L_LSB (1U << 0) /* 1b */ 31 #define IM_KICK_L_LSB (1U << 1) /* 1b */ 32 #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 33 #define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 34 #define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ 35 #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 36 37 /* PCM_CON1 (0x10006000+0x01C) */ 38 #define IM_SLAVE_LSB (1U << 0) /* 1b */ 39 #define IM_SLEEP_LSB (1U << 1) /* 1b */ 40 #define MIF_APBEN_LSB (1U << 3) /* 1b */ 41 #define IM_PDN_LSB (1U << 4) /* 1b */ 42 #define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 43 #define IM_NONRP_EN_LSB (1U << 6) /* 1b */ 44 #define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 45 #define PCM_WDT_EN_LSB (1U << 8) /* 1b */ 46 #define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ 47 #define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ 48 #define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ 49 #define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ 50 #define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 51 #define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 52 53 /* SPM_IRQ_MASK (0x10006000+0x0B4) */ 54 #define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ 55 56 /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ 57 #define WAKEUP_EVENT_MASK_B_BIT0 (1U << 0) /* 1b */ 58 59 /* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ 60 #define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ 61 62 /* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ 63 #define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ 64 #define SPM_PC_TRACE_OFFSET (1U << 3) /* 1b */ 65 #define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ 66 67 /* SPM_SPARE_ACK_MASK (0x10006000+0x6F4) */ 68 #define SPARE_ACK_MASK_B_BIT0 (1U << 0) /* 1b */ 69 #define SPARE_ACK_MASK_B_BIT1 (1U << 1) /* 1b */ 70 71 /************************************** 72 * Config and Parameter 73 **************************************/ 74 #define CONN_DDR_EN_DBC_LEN (0x00000154 << 20) 75 #define IFR_SRAMROM_ROM_PDN (0x0000003f) 76 #define IM_STATE (0x4 << 7) 77 #define IM_STATE_MASK (0x7 << 7) 78 #define MD_DDR_EN_0_DBC_LEN (0x00000154) 79 #define MD_DDR_EN_1_DBC_LEN (0x00000154 << 10) 80 #define PCM_FSM_STA_DEF (0x00108490) 81 #define PCM_FSM_STA_MASK (0x7FFFFF) 82 #define POWER_ON_VAL1_DEF (0x00015800) 83 #define SPM_CORE_TIMEOUT (5000) 84 #define SPM_MAS_PAUSE_MASK_B_VAL (0xFFFFFFFF) 85 #define SPM_MAS_PAUSE2_MASK_B_VAL (0xFFFFFFFF) 86 #define SPM_PCM_REG1_DATA_CHECK (0x1) 87 #define SPM_PCM_REG15_DATA_CHECK (0x0) 88 #define SPM_WAKEUP_EVENT_MASK_DEF (0xF0F92218) 89 #define SYSCLK1_EN_CTRL (0x3 << 2) 90 #define SYSCLK1_SRC_MASK_B (0x10 << 23) 91 92 /************************************** 93 * Define and Declare 94 **************************************/ 95 /* SPM_IRQ_MASK */ 96 #define ISRM_TWAM (1U << 2) 97 #define ISRM_PCM_RETURN (1U << 3) 98 #define ISRM_RET_IRQ_AUX (0x3FF00) 99 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) 100 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) 101 102 /* SPM_IRQ_STA */ 103 #define ISRS_TWAM (1U << 2) 104 #define ISRS_PCM_RETURN (1U << 3) 105 #define ISRS_SW_INT0 (1U << 4) 106 #define ISRC_TWAM (ISRS_TWAM) 107 #define ISRC_ALL_EXC_TWAM (ISRS_PCM_RETURN) 108 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) 109 110 /* PCM_PWR_IO_EN */ 111 #define PCM_PWRIO_EN_R0 (1U << 0) 112 #define PCM_PWRIO_EN_R7 (1U << 7) 113 #define PCM_RF_SYNC_R0 (1U << 16) 114 #define PCM_RF_SYNC_R6 (1U << 22) 115 #define PCM_RF_SYNC_R7 (1U << 23) 116 117 /* SPM_SWINT */ 118 #define PCM_SW_INT_ALL (0x3FF) 119 120 enum { 121 DISP_PWR_STA_MASK = 0x1 << 3, 122 DISP_SRAM_PDN_MASK = 0x1 << 8, 123 DISP_SRAM_ACK_MASK = 0x1 << 12, 124 AUDIO_PWR_STA_MASK = 0x1 << 24, 125 AUDIO_SRAM_PDN_MASK = 0xf << 8, 126 AUDIO_SRAM_ACK_MASK = 0xf << 12, 127 }; 128 129 #define PCM_EVENT_VECTOR_NUM 16 130 131 struct mtk_spm_regs { 132 u32 poweron_config_set; 133 u32 spm_power_on_val0; 134 u32 spm_power_on_val1; 135 u32 spm_clk_con; 136 u32 spm_clk_settle; 137 u32 spm_ap_standby_con; 138 u32 pcm_con0; 139 u32 pcm_con1; 140 u32 pcm_im_ptr; 141 u32 pcm_im_len; 142 u32 pcm_reg_data_ini; 143 u32 pcm_pwr_io_en; 144 u32 pcm_timer_val; 145 u32 pcm_wdt_val; 146 u32 pcm_im_host_rw_ptr; 147 u32 pcm_im_host_rw_dat; 148 u32 pcm_event_vector[PCM_EVENT_VECTOR_NUM]; 149 u32 pcm_event_vector_en; 150 u32 reserved1[1]; 151 u32 spm_sram_rsv_con; 152 u32 spm_swint; 153 u32 spm_swint_set; 154 u32 spm_swint_clr; 155 u32 spm_scp_mailbox; 156 u32 scp_spm_mailbox; 157 u32 spm_twam_con; 158 u32 spm_twam_window_len; 159 u32 spm_twam_idle_sel; 160 u32 spm_scp_irq; 161 u32 spm_cpu_wakeup_event; 162 u32 spm_irq_mask; 163 u32 spm_src_req; 164 u32 spm_src_mask; 165 u32 spm_src2_mask; 166 u32 spm_wakeup_event_mask; 167 u32 spm_wakeup_event_ext_mask; 168 u32 spm_twam_event_clear; 169 u32 scp_clk_con; 170 u32 pcm_debug_con; 171 u32 ddr_en_dbc_len; 172 u32 ahb_bus_con; 173 u32 spm_src3_mask; 174 u32 ddr_en_emi_dbc_con; 175 u32 md32_clk_con; 176 u32 reserved2[5]; 177 u32 pcm_reg0_data; 178 u32 pcm_reg1_data; 179 u32 pcm_reg2_data; 180 u32 pcm_reg3_data; 181 u32 pcm_reg4_data; 182 u32 pcm_reg5_data; 183 u32 pcm_reg6_data; 184 u32 pcm_reg7_data; 185 u32 pcm_reg8_data; 186 u32 pcm_reg9_data; 187 u32 pcm_reg10_data; 188 u32 pcm_reg11_data; 189 u32 pcm_reg12_data; 190 u32 pcm_reg13_data; 191 u32 pcm_reg14_data; 192 u32 pcm_reg15_data; 193 u32 pcm_reg12_mask_b_sta; 194 u32 pcm_reg12_ext_data; 195 u32 pcm_reg12_ext_mask_b_sta; 196 u32 pcm_event_reg_sta; 197 u32 pcm_timer_out; 198 u32 pcm_wdt_out; 199 u32 spm_irq_sta; 200 u32 spm_wakeup_sta; 201 u32 spm_wakeup_ext_sta; 202 u32 spm_wakeup_misc; 203 u32 bus_protect_rdy; 204 u32 bus_protect2_rdy; 205 u32 subsys_idle_sta; 206 u32 cpu_idle_sta; 207 u32 pcm_fsm_sta; 208 u32 src_req_sta; 209 u32 pwr_status; 210 u32 pwr_status_2nd; 211 u32 cpu_pwr_status; 212 u32 cpu_pwr_status_2nd; 213 u32 misc_sta; 214 u32 spm_src_rdy_sta; 215 u32 reserved3[1]; 216 u32 dramc_dbg_latch; 217 u32 spm_twam_last_sta0; 218 u32 spm_twam_last_sta1; 219 u32 spm_twam_last_sta2; 220 u32 spm_twam_last_sta3; 221 u32 spm_twam_curr_sta0; 222 u32 spm_twam_curr_sta1; 223 u32 spm_twam_curr_sta2; 224 u32 spm_twam_curr_sta3; 225 u32 spm_twam_timer_out; 226 u32 reserved4[1]; 227 u32 spm_dvfs_sta; 228 u32 bus_protect3_rdy; 229 u32 reserved5[4]; 230 u32 src_ddren_sta; 231 u32 reserved6[7]; 232 u32 mcu_pwr_con; 233 u32 mp0_cputop_pwr_con; 234 u32 mp0_cpu0_pwr_con; 235 u32 mp0_cpu1_pwr_con; 236 u32 mp0_cpu2_pwr_con; 237 u32 mp0_cpu3_pwr_con; 238 u32 mp1_cputop_pwr_con; 239 u32 mp1_cpu0_pwr_con; 240 u32 mp1_cpu1_pwr_con; 241 u32 mp1_cpu2_pwr_con; 242 u32 mp1_cpu3_pwr_con; 243 u32 reserved7[5]; 244 u32 mp0_cputop_l2_pdn; 245 u32 mp0_cputop_l2_sleep_b; 246 u32 mp0_cpu0_l1_pdn; 247 u32 mp0_cpu1_l1_pdn; 248 u32 mp0_cpu2_l1_pdn; 249 u32 mp0_cpu3_l1_pdn; 250 u32 mp1_cputop_l2_pdn; 251 u32 mp1_cputop_l2_sleep_b; 252 u32 mp1_cpu0_l1_pdn; 253 u32 mp1_cpu1_l1_pdn; 254 u32 mp1_cpu2_l1_pdn; 255 u32 mp1_cpu3_l1_pdn; 256 u32 reserved8[8]; 257 u32 cpu_ext_buck_iso; 258 u32 reserved9[7]; 259 u32 dummy1_pwr_con; 260 u32 bypass_spmc; 261 u32 spmc_dormant_enable; 262 u32 armpll_clk_con; 263 u32 spmc_in_ret; 264 u32 reserved10[15]; 265 u32 vde_pwr_con; 266 u32 ven_pwr_con; 267 u32 isp_pwr_con; 268 u32 dis_pwr_con; 269 u32 mfg_core1_pwr_con; 270 u32 audio_pwr_con; 271 u32 ifr_pwr_con; 272 u32 dpy_pwr_con; 273 u32 md1_pwr_con; 274 u32 vpu_top_pwr_con; 275 u32 reserved11[1]; 276 u32 conn_pwr_con; 277 u32 vpu_core2_pwr_con; 278 u32 mfg_async_pwr_con; 279 u32 mfg_pwr_con; 280 u32 vpu_core0_pwr_con; 281 u32 vpu_core1_pwr_con; 282 u32 cam_pwr_con; 283 u32 mfg_2d_pwr_con; 284 u32 mfg_core0_pwr_con; 285 u32 sysram_con; 286 u32 sysrom_con; 287 u32 sspm_sram_con; 288 u32 scp_sram_con; 289 u32 reserved12[3]; 290 u32 ufs_sram_con; 291 u32 reserved13[4]; 292 u32 dummy_sram_con; 293 u32 reserved14[3]; 294 u32 md_ext_buck_iso_con; 295 u32 md_sram_iso_con; 296 u32 md_extra_pwr_con; 297 u32 reserved15[1]; 298 u32 ext_buck_con; 299 u32 reserved16[11]; 300 u32 mbist_efuse_repair_ack_sta; 301 u32 reserved17[11]; 302 u32 spm_dvfs_con; 303 u32 spm_mdbsi_con; 304 u32 spm_mas_pause_mask_b; 305 u32 spm_mas_pause2_mask_b; 306 u32 spm_bsi_gen; 307 u32 spm_bsi_en_sr; 308 u32 spm_bsi_clk_sr; 309 u32 spm_bsi_d0_sr; 310 u32 spm_bsi_d1_sr; 311 u32 spm_bsi_d2_sr; 312 u32 spm_ap_sema; 313 u32 spm_spm_sema; 314 u32 ap_mdsrc_req; 315 u32 reserved18[1]; 316 u32 spm2md_dvfs_con; 317 u32 md2spm_dvfs_con; 318 u32 dramc_dpy_clk_sw_con_rsv; 319 u32 dpy_lp_con; 320 u32 cpu_dvfs_req; 321 u32 spm_pll_con; 322 u32 spm_emi_bw_mode; 323 u32 ap2md_peer_wakeup; 324 u32 ulposc_con; 325 u32 spm2mm_con; 326 u32 dramc_dpy_clk_sw_con_sel; 327 u32 dramc_dpy_clk_sw_con; 328 u32 spm_s1_mode_ch; 329 u32 emi_self_refresh_ch_sta; 330 u32 dramc_dpy_clk_sw_con_sel2; 331 u32 dramc_dpy_clk_sw_con2; 332 u32 dramc_dmyrd_con; 333 u32 spm_drs_con; 334 u32 spm_sema_m0; 335 u32 spm_sema_m1; 336 u32 spm_sema_m2; 337 u32 spm_sema_m3; 338 u32 spm_sema_m4; 339 u32 spm_sema_m5; 340 u32 spm_sema_m6; 341 u32 spm_sema_m7; 342 u32 spm_mas_pause_mm_mask_b; 343 u32 spm_mas_pause_mcu_mask_b; 344 u32 reserved19[1]; 345 u32 sram_dreq_ack; 346 u32 sram_dreq_con; 347 u32 sram_dreq_con_set; 348 u32 sram_dreq_con_clr; 349 u32 spm2emi_enter_ulpm; 350 u32 spm_md32_irq; 351 u32 spm2pmcu_int; 352 u32 spm2pmcu_int_set; 353 u32 spm2pmcu_int_clr; 354 u32 spm2pmcu_mailbox_0; 355 u32 spm2pmcu_mailbox_1; 356 u32 spm2pmcu_mailbox_2; 357 u32 spm2pmcu_mailbox_3; 358 u32 pmcu2spm_int; 359 u32 pmcu2spm_int_set; 360 u32 pmcu2spm_int_clr; 361 u32 pmcu2spm_mailbox_0; 362 u32 pmcu2spm_mailbox_1; 363 u32 pmcu2spm_mailbox_2; 364 u32 pmcu2spm_mailbox_3; 365 u32 pmcu2spm_cfg; 366 u32 mp0_cpu0_irq_mask; 367 u32 mp0_cpu1_irq_mask; 368 u32 mp0_cpu2_irq_mask; 369 u32 mp0_cpu3_irq_mask; 370 u32 mp1_cpu0_irq_mask; 371 u32 mp1_cpu1_irq_mask; 372 u32 mp1_cpu2_irq_mask; 373 u32 mp1_cpu3_irq_mask; 374 u32 reserved20[4]; 375 u32 mp0_cpu0_wfi_en; 376 u32 mp0_cpu1_wfi_en; 377 u32 mp0_cpu2_wfi_en; 378 u32 mp0_cpu3_wfi_en; 379 u32 mp1_cpu0_wfi_en; 380 u32 mp1_cpu1_wfi_en; 381 u32 mp1_cpu2_wfi_en; 382 u32 mp1_cpu3_wfi_en; 383 u32 reserved21[1]; 384 u32 mp0_l2cflush; 385 u32 mp1_l2cflush; 386 u32 reserved22[1]; 387 u32 cpu_ptpod2_con; 388 u32 reserved23[3]; 389 u32 root_cputop_addr; 390 u32 root_core_addr; 391 u32 reserved24[2]; 392 u32 cpu_spare_con; 393 u32 cpu_spare_con_set; 394 u32 cpu_spare_con_clr; 395 u32 reserved25[17]; 396 u32 spm2sw_mailbox_0; 397 u32 spm2sw_mailbox_1; 398 u32 spm2sw_mailbox_2; 399 u32 spm2sw_mailbox_3; 400 u32 sw2spm_int; 401 u32 sw2spm_int_set; 402 u32 sw2spm_int_clr; 403 u32 sw2spm_mailbox_0; 404 u32 sw2spm_mailbox_1; 405 u32 sw2spm_mailbox_2; 406 u32 sw2spm_mailbox_3; 407 u32 sw2spm_cfg; 408 u32 spm_sw_flag; 409 u32 spm_sw_debug; 410 u32 spm_sw_rsv_0; 411 u32 spm_sw_rsv_1; 412 u32 spm_sw_rsv_2; 413 u32 spm_sw_rsv_3; 414 u32 spm_sw_rsv_4; 415 u32 spm_sw_rsv_5; 416 u32 spm_rsv_con; 417 u32 spm_rsv_sta; 418 u32 spm_rsv_con1; 419 u32 spm_rsv_sta1; 420 u32 spm_pasr_dpd_0; 421 u32 spm_pasr_dpd_1; 422 u32 spm_pasr_dpd_2; 423 u32 spm_pasr_dpd_3; 424 u32 spm_spare_con; 425 u32 spm_spare_con_set; 426 u32 spm_spare_con_clr; 427 u32 spm_sw_rsv_6; 428 u32 spm_sw_rsv_7; 429 u32 spm_sw_rsv_8; 430 u32 spm_sw_rsv_9; 431 u32 spm_sw_rsv_10; 432 u32 reserved26[7]; 433 u32 spm_sw_rsv_18; 434 u32 spm_sw_rsv_19; 435 u32 reserved27[3]; 436 u32 dvfsrc_event_mask_con; 437 u32 dvfsrc_event_force_on; 438 u32 dvfsrc_event_sel; 439 u32 spm_dvfs_event_sta; 440 u32 spm_dvfs_event_sta1; 441 u32 spm_dvfs_level; 442 u32 dvfs_abort_sta; 443 u32 dvfs_abort_others_mask; 444 u32 spm_dfs_level; 445 u32 spm_dvs_level; 446 u32 spm_dvfs_misc; 447 u32 reserved28[1]; 448 u32 spare_src_req_mask; 449 u32 scp_vcore_level; 450 u32 sc_mm_ck_sel_con; 451 u32 reserved29[9]; 452 u32 spare_ack_sta; 453 u32 spare_ack_mask; 454 u32 reserved30[2]; 455 u32 spm_dvfs_con1; 456 u32 spm_dvfs_con1_sta; 457 u32 reserved31[2]; 458 u32 spm_dvfs_cmd0; 459 u32 spm_dvfs_cmd1; 460 u32 spm_dvfs_cmd2; 461 u32 spm_dvfs_cmd3; 462 u32 spm_dvfs_cmd4; 463 u32 spm_dvfs_cmd5; 464 u32 spm_dvfs_cmd6; 465 u32 spm_dvfs_cmd7; 466 u32 spm_dvfs_cmd8; 467 u32 spm_dvfs_cmd9; 468 u32 spm_dvfs_cmd10; 469 u32 spm_dvfs_cmd11; 470 u32 spm_dvfs_cmd12; 471 u32 spm_dvfs_cmd13; 472 u32 spm_dvfs_cmd14; 473 u32 spm_dvfs_cmd15; 474 u32 reserved32[12]; 475 u32 wdt_latch_spare0_fix; 476 u32 wdt_latch_spare1_fix; 477 u32 wdt_latch_spare2_fix; 478 u32 wdt_latch_spare3_fix; 479 u32 spare_ack_in_fix; 480 u32 dcha_latch_rsv0_fix; 481 u32 dchb_latch_rsv0_fix; 482 u32 reserved33[25]; 483 u32 pcm_wdt_latch_0; 484 u32 pcm_wdt_latch_1; 485 u32 pcm_wdt_latch_2; 486 u32 pcm_wdt_latch_3; 487 u32 pcm_wdt_latch_4; 488 u32 pcm_wdt_latch_5; 489 u32 pcm_wdt_latch_6; 490 u32 pcm_wdt_latch_7; 491 u32 pcm_wdt_latch_8; 492 u32 pcm_wdt_latch_9; 493 u32 wdt_latch_spare0; 494 u32 wdt_latch_spare1; 495 u32 wdt_latch_spare2; 496 u32 wdt_latch_spare3; 497 u32 pcm_wdt_latch_10; 498 u32 pcm_wdt_latch_11; 499 u32 dcha_gating_latch_0; 500 u32 dcha_gating_latch_1; 501 u32 dcha_gating_latch_2; 502 u32 dcha_gating_latch_3; 503 u32 dcha_gating_latch_4; 504 u32 dcha_gating_latch_5; 505 u32 dcha_gating_latch_6; 506 u32 dcha_gating_latch_7; 507 u32 dchb_gating_latch_0; 508 u32 dchb_gating_latch_1; 509 u32 dchb_gating_latch_2; 510 u32 dchb_gating_latch_3; 511 u32 dchb_gating_latch_4; 512 u32 dchb_gating_latch_5; 513 u32 dchb_gating_latch_6; 514 u32 dchb_gating_latch_7; 515 u32 dcha_latch_rsv0; 516 u32 dchb_latch_rsv0; 517 u32 pcm_wdt_latch_12; 518 u32 pcm_wdt_latch_13; 519 u32 reserved34[12]; 520 u32 spm_pc_trace_con; 521 u32 spm_pc_trace_g0; 522 u32 spm_pc_trace_g1; 523 u32 spm_pc_trace_g2; 524 u32 spm_pc_trace_g3; 525 u32 spm_pc_trace_g4; 526 u32 spm_pc_trace_g5; 527 u32 spm_pc_trace_g6; 528 u32 spm_pc_trace_g7; 529 u32 reserved35[7]; 530 u32 spm_ack_chk_con; 531 u32 spm_ack_chk_pc; 532 u32 spm_ack_chk_sel; 533 u32 spm_ack_chk_timer; 534 u32 spm_ack_chk_sta; 535 u32 spm_ack_chk_latch; 536 u32 reserved36[2]; 537 u32 spm_ack_chk_con2; 538 u32 spm_ack_chk_pc2; 539 u32 spm_ack_chk_sel2; 540 u32 spm_ack_chk_timer2; 541 u32 spm_ack_chk_sta2; 542 u32 spm_ack_chk_latch2; 543 u32 reserved37[2]; 544 u32 spm_ack_chk_con3; 545 u32 spm_ack_chk_pc3; 546 u32 spm_ack_chk_sel3; 547 u32 spm_ack_chk_timer3; 548 u32 spm_ack_chk_sta3; 549 u32 spm_ack_chk_latch3; 550 u32 reserved38[2]; 551 u32 spm_ack_chk_con4; 552 u32 spm_ack_chk_pc4; 553 u32 spm_ack_chk_sel4; 554 u32 spm_ack_chk_timer4; 555 u32 spm_ack_chk_sta4; 556 u32 spm_ack_chk_latch4; 557 }; 558 check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974); 559 560 static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; 561 562 enum dyna_load_pcm_index { 563 DYNA_LOAD_PCM_SUSPEND_LP4_3733 = 0, 564 DYNA_LOAD_PCM_SUSPEND_LP4_3200, 565 DYNA_LOAD_PCM_MAX, 566 }; 567 568 struct pcm_desc { 569 u16 size; /* binary array size */ 570 u8 sess; /* session number */ 571 u8 replace; /* replace mode */ 572 u16 addr_2nd; /* 2nd binary array size */ 573 u16 reserved; /* for 32bit alignment */ 574 u32 vector[PCM_EVENT_VECTOR_NUM]; /* event vector config */ 575 }; 576 577 struct dyna_load_pcm { 578 u32 *buf; /* binary array */ 579 struct pcm_desc desc; 580 }; 581 582 int spm_init(void); 583 584 static const struct power_domain_data disp[] = { 585 { 586 .pwr_con = &mtk_spm->dis_pwr_con, 587 .pwr_sta_mask = DISP_PWR_STA_MASK, 588 .sram_pdn_mask = DISP_SRAM_PDN_MASK, 589 .sram_ack_mask = DISP_SRAM_ACK_MASK, 590 }, 591 }; 592 593 static const struct power_domain_data audio[] = { 594 { 595 .pwr_con = &mtk_spm->audio_pwr_con, 596 .pwr_sta_mask = AUDIO_PWR_STA_MASK, 597 .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, 598 .sram_ack_mask = AUDIO_SRAM_ACK_MASK, 599 }, 600 }; 601 602 #endif /* SOC_MEDIATEK_MT8183_SPM_H */ 603