1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <[email protected]>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_framebuffer.h>
20
21 #include "msm_drv.h"
22 #include "dpu_kms.h"
23 #include "dpu_hwio.h"
24 #include "dpu_hw_catalog.h"
25 #include "dpu_hw_intf.h"
26 #include "dpu_hw_ctl.h"
27 #include "dpu_hw_dspp.h"
28 #include "dpu_hw_dsc.h"
29 #include "dpu_hw_merge3d.h"
30 #include "dpu_hw_cdm.h"
31 #include "dpu_formats.h"
32 #include "dpu_encoder_phys.h"
33 #include "dpu_crtc.h"
34 #include "dpu_trace.h"
35 #include "dpu_core_irq.h"
36 #include "disp/msm_disp_snapshot.h"
37
38 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
40
41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
43
44 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\
45 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
46
47 /*
48 * Two to anticipate panels that can do cmd/vid dynamic switching
49 * plan is to create all possible physical encoder types, and switch between
50 * them at runtime
51 */
52 #define NUM_PHYS_ENCODER_TYPES 2
53
54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
56
57 #define MAX_CHANNELS_PER_ENC 2
58
59 #define IDLE_SHORT_TIMEOUT 1
60
61 #define MAX_HDISPLAY_SPLIT 1080
62
63 /* timeout in frames waiting for frame done */
64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
65
66 /**
67 * enum dpu_enc_rc_events - events for resource control state machine
68 * @DPU_ENC_RC_EVENT_KICKOFF:
69 * This event happens at NORMAL priority.
70 * Event that signals the start of the transfer. When this event is
71 * received, enable MDP/DSI core clocks. Regardless of the previous
72 * state, the resource should be in ON state at the end of this event.
73 * @DPU_ENC_RC_EVENT_FRAME_DONE:
74 * This event happens at INTERRUPT level.
75 * Event signals the end of the data transfer after the PP FRAME_DONE
76 * event. At the end of this event, a delayed work is scheduled to go to
77 * IDLE_PC state after IDLE_TIMEOUT time.
78 * @DPU_ENC_RC_EVENT_PRE_STOP:
79 * This event happens at NORMAL priority.
80 * This event, when received during the ON state, leave the RC STATE
81 * in the PRE_OFF state. It should be followed by the STOP event as
82 * part of encoder disable.
83 * If received during IDLE or OFF states, it will do nothing.
84 * @DPU_ENC_RC_EVENT_STOP:
85 * This event happens at NORMAL priority.
86 * When this event is received, disable all the MDP/DSI core clocks, and
87 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
89 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
90 * Resource state should be in OFF at the end of the event.
91 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
92 * This event happens at NORMAL priority from a work item.
93 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
94 * This would disable MDP/DSI core clocks and change the resource state
95 * to IDLE.
96 */
97 enum dpu_enc_rc_events {
98 DPU_ENC_RC_EVENT_KICKOFF = 1,
99 DPU_ENC_RC_EVENT_FRAME_DONE,
100 DPU_ENC_RC_EVENT_PRE_STOP,
101 DPU_ENC_RC_EVENT_STOP,
102 DPU_ENC_RC_EVENT_ENTER_IDLE
103 };
104
105 /*
106 * enum dpu_enc_rc_states - states that the resource control maintains
107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
112 */
113 enum dpu_enc_rc_states {
114 DPU_ENC_RC_STATE_OFF,
115 DPU_ENC_RC_STATE_PRE_OFF,
116 DPU_ENC_RC_STATE_ON,
117 DPU_ENC_RC_STATE_IDLE
118 };
119
120 /**
121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
122 * encoders. Virtual encoder manages one "logical" display. Physical
123 * encoders manage one intf block, tied to a specific panel/sub-panel.
124 * Virtual encoder defers as much as possible to the physical encoders.
125 * Virtual encoder registers itself with the DRM Framework as the encoder.
126 * @base: drm_encoder base class for registration with DRM
127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
128 * @enabled: True if the encoder is active, protected by enc_lock
129 * @commit_done_timedout: True if there has been a timeout on commit after
130 * enabling the encoder.
131 * @num_phys_encs: Actual number of physical encoders contained.
132 * @phys_encs: Container of physical encoders managed.
133 * @cur_master: Pointer to the current master in this mode. Optimization
134 * Only valid after enable. Cleared as disable.
135 * @cur_slave: As above but for the slave encoder.
136 * @hw_pp: Handle to the pingpong blocks used for the display. No.
137 * pingpong blocks can be different than num_phys_encs.
138 * @hw_dsc: Handle to the DSC blocks used for the display.
139 * @dsc_mask: Bitmask of used DSC blocks.
140 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
141 * for partial update right-only cases, such as pingpong
142 * split where virtual pingpong does not generate IRQs
143 * @crtc: Pointer to the currently assigned crtc. Normally you
144 * would use crtc->state->encoder_mask to determine the
145 * link between encoder/crtc. However in this case we need
146 * to track crtc in the disable() hook which is called
147 * _after_ encoder_mask is cleared.
148 * @connector: If a mode is set, cached pointer to the active connector
149 * @enc_lock: Lock around physical encoder
150 * create/destroy/enable/disable
151 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
152 * busy processing current command.
153 * Bit0 = phys_encs[0] etc.
154 * @frame_done_timeout_ms: frame done timeout in ms
155 * @frame_done_timeout_cnt: atomic counter tracking the number of frame
156 * done timeouts
157 * @frame_done_timer: watchdog timer for frame done event
158 * @disp_info: local copy of msm_display_info struct
159 * @idle_pc_supported: indicate if idle power collaps is supported
160 * @rc_lock: resource control mutex lock to protect
161 * virt encoder over various state changes
162 * @rc_state: resource controller state
163 * @delayed_off_work: delayed worker to schedule disabling of
164 * clks and resources after IDLE_TIMEOUT time.
165 * @topology: topology of the display
166 * @idle_timeout: idle timeout duration in milliseconds
167 * @wide_bus_en: wide bus is enabled on this interface
168 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
169 */
170 struct dpu_encoder_virt {
171 struct drm_encoder base;
172 spinlock_t enc_spinlock;
173
174 bool enabled;
175 bool commit_done_timedout;
176
177 unsigned int num_phys_encs;
178 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
179 struct dpu_encoder_phys *cur_master;
180 struct dpu_encoder_phys *cur_slave;
181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
182 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
183
184 unsigned int dsc_mask;
185
186 bool intfs_swapped;
187
188 struct drm_crtc *crtc;
189 struct drm_connector *connector;
190
191 struct mutex enc_lock;
192 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
193
194 atomic_t frame_done_timeout_ms;
195 atomic_t frame_done_timeout_cnt;
196 struct timer_list frame_done_timer;
197
198 struct msm_display_info disp_info;
199
200 bool idle_pc_supported;
201 struct mutex rc_lock;
202 enum dpu_enc_rc_states rc_state;
203 struct delayed_work delayed_off_work;
204 struct msm_display_topology topology;
205
206 u32 idle_timeout;
207
208 bool wide_bus_en;
209
210 /* DSC configuration */
211 struct drm_dsc_config *dsc;
212 };
213
214 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
215
216 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
217 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
218 };
219
220 /**
221 * dpu_encoder_get_drm_fmt - return DRM fourcc format
222 * @phys_enc: Pointer to physical encoder structure
223 */
dpu_encoder_get_drm_fmt(struct dpu_encoder_phys * phys_enc)224 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc)
225 {
226 struct drm_encoder *drm_enc;
227 struct dpu_encoder_virt *dpu_enc;
228 struct drm_display_info *info;
229 struct drm_display_mode *mode;
230
231 drm_enc = phys_enc->parent;
232 dpu_enc = to_dpu_encoder_virt(drm_enc);
233 info = &dpu_enc->connector->display_info;
234 mode = &phys_enc->cached_mode;
235
236 if (drm_mode_is_420_only(info, mode))
237 return DRM_FORMAT_YUV420;
238
239 return DRM_FORMAT_RGB888;
240 }
241
242 /**
243 * dpu_encoder_needs_periph_flush - return true if physical encoder requires
244 * peripheral flush
245 * @phys_enc: Pointer to physical encoder structure
246 */
dpu_encoder_needs_periph_flush(struct dpu_encoder_phys * phys_enc)247 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc)
248 {
249 struct drm_encoder *drm_enc;
250 struct dpu_encoder_virt *dpu_enc;
251 struct msm_display_info *disp_info;
252 struct msm_drm_private *priv;
253 struct drm_display_mode *mode;
254
255 drm_enc = phys_enc->parent;
256 dpu_enc = to_dpu_encoder_virt(drm_enc);
257 disp_info = &dpu_enc->disp_info;
258 priv = drm_enc->dev->dev_private;
259 mode = &phys_enc->cached_mode;
260
261 return phys_enc->hw_intf->cap->type == INTF_DP &&
262 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode);
263 }
264
265 /**
266 * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled
267 * @drm_enc: Pointer to previously created drm encoder structure
268 */
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)269 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
270 {
271 const struct dpu_encoder_virt *dpu_enc;
272 struct msm_drm_private *priv = drm_enc->dev->dev_private;
273 const struct msm_display_info *disp_info;
274 int index;
275
276 dpu_enc = to_dpu_encoder_virt(drm_enc);
277 disp_info = &dpu_enc->disp_info;
278 index = disp_info->h_tile_instance[0];
279
280 if (disp_info->intf_type == INTF_DP)
281 return msm_dp_wide_bus_available(priv->dp[index]);
282 else if (disp_info->intf_type == INTF_DSI)
283 return msm_dsi_wide_bus_enabled(priv->dsi[index]);
284
285 return false;
286 }
287
288 /**
289 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
290 * for the encoder.
291 * @drm_enc: Pointer to previously created drm encoder structure
292 */
dpu_encoder_is_dsc_enabled(const struct drm_encoder * drm_enc)293 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
294 {
295 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
296
297 return dpu_enc->dsc ? true : false;
298 }
299
300 /**
301 * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
302 * in virtual encoder that can collect CRC values
303 * @drm_enc: Pointer to previously created drm encoder structure
304 * Returns: Number of physical encoders for given drm encoder
305 */
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)306 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
307 {
308 struct dpu_encoder_virt *dpu_enc;
309 int i, num_intf = 0;
310
311 dpu_enc = to_dpu_encoder_virt(drm_enc);
312
313 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
314 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
315
316 if (phys->hw_intf && phys->hw_intf->ops.setup_misr
317 && phys->hw_intf->ops.collect_misr)
318 num_intf++;
319 }
320
321 return num_intf;
322 }
323
324 /**
325 * dpu_encoder_setup_misr - enable misr calculations
326 * @drm_enc: Pointer to previously created drm encoder structure
327 */
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)328 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
329 {
330 struct dpu_encoder_virt *dpu_enc;
331
332 int i;
333
334 dpu_enc = to_dpu_encoder_virt(drm_enc);
335
336 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
337 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
338
339 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
340 continue;
341
342 phys->hw_intf->ops.setup_misr(phys->hw_intf);
343 }
344 }
345
346 /**
347 * dpu_encoder_get_crc - get the crc value from interface blocks
348 * @drm_enc: Pointer to previously created drm encoder structure
349 * @crcs: array to fill with CRC data
350 * @pos: offset into the @crcs array
351 * Returns: 0 on success, error otherwise
352 */
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)353 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
354 {
355 struct dpu_encoder_virt *dpu_enc;
356
357 int i, rc = 0, entries_added = 0;
358
359 if (!drm_enc->crtc) {
360 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
361 return -EINVAL;
362 }
363
364 dpu_enc = to_dpu_encoder_virt(drm_enc);
365
366 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
367 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
368
369 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
370 continue;
371
372 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
373 if (rc)
374 return rc;
375 entries_added++;
376 }
377
378 return entries_added;
379 }
380
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)381 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
382 {
383 struct dpu_hw_dither_cfg dither_cfg = { 0 };
384
385 if (!hw_pp->ops.setup_dither)
386 return;
387
388 switch (bpc) {
389 case 6:
390 dither_cfg.c0_bitdepth = 6;
391 dither_cfg.c1_bitdepth = 6;
392 dither_cfg.c2_bitdepth = 6;
393 dither_cfg.c3_bitdepth = 6;
394 dither_cfg.temporal_en = 0;
395 break;
396 default:
397 hw_pp->ops.setup_dither(hw_pp, NULL);
398 return;
399 }
400
401 memcpy(&dither_cfg.matrix, dither_matrix,
402 sizeof(u32) * DITHER_MATRIX_SZ);
403
404 hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
405 }
406
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)407 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
408 {
409 switch (intf_mode) {
410 case INTF_MODE_VIDEO:
411 return "INTF_MODE_VIDEO";
412 case INTF_MODE_CMD:
413 return "INTF_MODE_CMD";
414 case INTF_MODE_WB_BLOCK:
415 return "INTF_MODE_WB_BLOCK";
416 case INTF_MODE_WB_LINE:
417 return "INTF_MODE_WB_LINE";
418 default:
419 return "INTF_MODE_UNKNOWN";
420 }
421 }
422
423 /**
424 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
425 * timed out, including reporting frame error event to crtc and debug dump
426 * @phys_enc: Pointer to physical encoder structure
427 * @intr_idx: Failing interrupt index
428 */
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)429 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
430 enum dpu_intr_idx intr_idx)
431 {
432 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
433 DRMID(phys_enc->parent),
434 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
435 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
436 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,
437 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
438
439 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
440 DPU_ENCODER_FRAME_EVENT_ERROR);
441 }
442
443 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
444 u32 irq_idx, struct dpu_encoder_wait_info *info);
445
446 /**
447 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
448 * note: will call dpu_encoder_helper_wait_for_irq on timeout
449 * @phys_enc: Pointer to physical encoder structure
450 * @irq_idx: IRQ index
451 * @func: IRQ callback to be called in case of timeout
452 * @wait_info: wait info struct
453 * @return: 0 or -ERROR
454 */
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,unsigned int irq_idx,void (* func)(void * arg),struct dpu_encoder_wait_info * wait_info)455 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
456 unsigned int irq_idx,
457 void (*func)(void *arg),
458 struct dpu_encoder_wait_info *wait_info)
459 {
460 u32 irq_status;
461 int ret;
462
463 if (!wait_info) {
464 DPU_ERROR("invalid params\n");
465 return -EINVAL;
466 }
467 /* note: do master / slave checking outside */
468
469 /* return EWOULDBLOCK since we know the wait isn't necessary */
470 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
471 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n",
472 DRMID(phys_enc->parent), func,
473 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
474 return -EWOULDBLOCK;
475 }
476
477 if (irq_idx == 0) {
478 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
479 DRMID(phys_enc->parent), func);
480 return 0;
481 }
482
483 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n",
484 DRMID(phys_enc->parent), func,
485 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0,
486 atomic_read(wait_info->atomic_cnt));
487
488 ret = dpu_encoder_helper_wait_event_timeout(
489 DRMID(phys_enc->parent),
490 irq_idx,
491 wait_info);
492
493 if (ret <= 0) {
494 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);
495 if (irq_status) {
496 unsigned long flags;
497
498 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
499 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
500 DRMID(phys_enc->parent), func,
501 phys_enc->hw_pp->idx - PINGPONG_0,
502 atomic_read(wait_info->atomic_cnt));
503 local_irq_save(flags);
504 func(phys_enc);
505 local_irq_restore(flags);
506 ret = 0;
507 } else {
508 ret = -ETIMEDOUT;
509 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
510 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
511 DRMID(phys_enc->parent), func,
512 phys_enc->hw_pp->idx - PINGPONG_0,
513 atomic_read(wait_info->atomic_cnt));
514 }
515 } else {
516 ret = 0;
517 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
518 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
519 phys_enc->hw_pp->idx - PINGPONG_0,
520 atomic_read(wait_info->atomic_cnt));
521 }
522
523 return ret;
524 }
525
526 /**
527 * dpu_encoder_get_vsync_count - get vsync count for the encoder.
528 * @drm_enc: Pointer to previously created drm encoder structure
529 */
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)530 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
531 {
532 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
533 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
534 return phys ? atomic_read(&phys->vsync_cnt) : 0;
535 }
536
537 /**
538 * dpu_encoder_get_linecount - get interface line count for the encoder.
539 * @drm_enc: Pointer to previously created drm encoder structure
540 */
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)541 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
542 {
543 struct dpu_encoder_virt *dpu_enc;
544 struct dpu_encoder_phys *phys;
545 int linecount = 0;
546
547 dpu_enc = to_dpu_encoder_virt(drm_enc);
548 phys = dpu_enc ? dpu_enc->cur_master : NULL;
549
550 if (phys && phys->ops.get_line_count)
551 linecount = phys->ops.get_line_count(phys);
552
553 return linecount;
554 }
555
556 /**
557 * dpu_encoder_helper_split_config - split display configuration helper function
558 * This helper function may be used by physical encoders to configure
559 * the split display related registers.
560 * @phys_enc: Pointer to physical encoder structure
561 * @interface: enum dpu_intf setting
562 */
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)563 void dpu_encoder_helper_split_config(
564 struct dpu_encoder_phys *phys_enc,
565 enum dpu_intf interface)
566 {
567 struct dpu_encoder_virt *dpu_enc;
568 struct split_pipe_cfg cfg = { 0 };
569 struct dpu_hw_mdp *hw_mdptop;
570 struct msm_display_info *disp_info;
571
572 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
573 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
574 return;
575 }
576
577 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
578 hw_mdptop = phys_enc->hw_mdptop;
579 disp_info = &dpu_enc->disp_info;
580
581 if (disp_info->intf_type != INTF_DSI)
582 return;
583
584 /**
585 * disable split modes since encoder will be operating in as the only
586 * encoder, either for the entire use case in the case of, for example,
587 * single DSI, or for this frame in the case of left/right only partial
588 * update.
589 */
590 if (phys_enc->split_role == ENC_ROLE_SOLO) {
591 if (hw_mdptop->ops.setup_split_pipe)
592 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
593 return;
594 }
595
596 cfg.en = true;
597 cfg.mode = phys_enc->intf_mode;
598 cfg.intf = interface;
599
600 if (cfg.en && phys_enc->ops.needs_single_flush &&
601 phys_enc->ops.needs_single_flush(phys_enc))
602 cfg.split_flush_en = true;
603
604 if (phys_enc->split_role == ENC_ROLE_MASTER) {
605 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
606
607 if (hw_mdptop->ops.setup_split_pipe)
608 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
609 }
610 }
611
612 /**
613 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
614 * @drm_enc: Pointer to previously created drm encoder structure
615 */
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)616 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
617 {
618 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
619 int i, intf_count = 0, num_dsc = 0;
620
621 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
622 if (dpu_enc->phys_encs[i])
623 intf_count++;
624
625 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
626 if (dpu_enc->hw_dsc[i])
627 num_dsc++;
628
629 return (num_dsc > 0) && (num_dsc > intf_count);
630 }
631
632 /**
633 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
634 * This helper function is used by physical encoder to get DSC config
635 * used for this encoder.
636 * @drm_enc: Pointer to encoder structure
637 */
dpu_encoder_get_dsc_config(struct drm_encoder * drm_enc)638 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
639 {
640 struct msm_drm_private *priv = drm_enc->dev->dev_private;
641 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
642 int index = dpu_enc->disp_info.h_tile_instance[0];
643
644 if (dpu_enc->disp_info.intf_type == INTF_DSI)
645 return msm_dsi_get_dsc_config(priv->dsi[index]);
646
647 return NULL;
648 }
649
dpu_encoder_get_topology(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)650 static struct msm_display_topology dpu_encoder_get_topology(
651 struct dpu_encoder_virt *dpu_enc,
652 struct drm_display_mode *mode,
653 struct drm_crtc_state *crtc_state,
654 struct drm_connector_state *conn_state)
655 {
656 struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
657 struct msm_display_info *disp_info = &dpu_enc->disp_info;
658 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
659 struct drm_dsc_config *dsc = dpu_encoder_get_dsc_config(&dpu_enc->base);
660 struct msm_display_topology topology = {0};
661 int i, intf_count = 0;
662
663 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
664 if (dpu_enc->phys_encs[i])
665 intf_count++;
666
667 /* Datapath topology selection
668 *
669 * Dual display
670 * 2 LM, 2 INTF ( Split display using 2 interfaces)
671 *
672 * Single display
673 * 1 LM, 1 INTF
674 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
675 *
676 * Add dspps to the reservation requirements if ctm is requested
677 */
678 if (intf_count == 2)
679 topology.num_lm = 2;
680 else if (!dpu_kms->catalog->caps->has_3d_merge)
681 topology.num_lm = 1;
682 else
683 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
684
685 if (crtc_state->ctm)
686 topology.num_dspp = topology.num_lm;
687
688 topology.num_intf = intf_count;
689
690 if (dsc) {
691 /*
692 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
693 * when Display Stream Compression (DSC) is enabled,
694 * and when enough DSC blocks are available.
695 * This is power-optimal and can drive up to (including) 4k
696 * screens.
697 */
698 WARN(topology.num_intf > 2,
699 "DSC topology cannot support more than 2 interfaces\n");
700 if (intf_count >= 2 || dpu_kms->catalog->dsc_count >= 2) {
701 topology.num_dsc = 2;
702 topology.num_lm = 2;
703 } else {
704 topology.num_dsc = 1;
705 topology.num_lm = 1;
706 }
707 }
708
709 /*
710 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it.
711 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check()
712 * earlier.
713 */
714 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
715 struct drm_framebuffer *fb;
716
717 fb = conn_state->writeback_job->fb;
718
719 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
720 topology.needs_cdm = true;
721 } else if (disp_info->intf_type == INTF_DP) {
722 if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], mode))
723 topology.needs_cdm = true;
724 }
725
726 return topology;
727 }
728
dpu_encoder_assign_crtc_resources(struct dpu_kms * dpu_kms,struct drm_encoder * drm_enc,struct dpu_global_state * global_state,struct drm_crtc_state * crtc_state)729 static void dpu_encoder_assign_crtc_resources(struct dpu_kms *dpu_kms,
730 struct drm_encoder *drm_enc,
731 struct dpu_global_state *global_state,
732 struct drm_crtc_state *crtc_state)
733 {
734 struct dpu_crtc_state *cstate;
735 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
736 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
737 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC];
738 int num_lm, num_ctl, num_dspp, i;
739
740 cstate = to_dpu_crtc_state(crtc_state);
741
742 memset(cstate->mixers, 0, sizeof(cstate->mixers));
743
744 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
745 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
746 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
747 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
748 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
749 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
750 ARRAY_SIZE(hw_dspp));
751
752 for (i = 0; i < num_lm; i++) {
753 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
754
755 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
756 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
757 cstate->mixers[i].hw_dspp = i < num_dspp ? to_dpu_hw_dspp(hw_dspp[i]) : NULL;
758 }
759
760 cstate->num_mixers = num_lm;
761 }
762
763 /**
764 * dpu_encoder_virt_check_mode_changed: check if full modeset is required
765 * @drm_enc: Pointer to drm encoder structure
766 * @crtc_state: Corresponding CRTC state to be checked
767 * @conn_state: Corresponding Connector's state to be checked
768 *
769 * Check if the changes in the object properties demand full mode set.
770 */
dpu_encoder_virt_check_mode_changed(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)771 int dpu_encoder_virt_check_mode_changed(struct drm_encoder *drm_enc,
772 struct drm_crtc_state *crtc_state,
773 struct drm_connector_state *conn_state)
774 {
775 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
776 struct msm_display_topology topology;
777
778 DPU_DEBUG_ENC(dpu_enc, "\n");
779
780 /* Using mode instead of adjusted_mode as it wasn't computed yet */
781 topology = dpu_encoder_get_topology(dpu_enc, &crtc_state->mode, crtc_state, conn_state);
782
783 if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm)
784 crtc_state->mode_changed = true;
785 else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm)
786 crtc_state->mode_changed = true;
787
788 return 0;
789 }
790
dpu_encoder_virt_atomic_check(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)791 static int dpu_encoder_virt_atomic_check(
792 struct drm_encoder *drm_enc,
793 struct drm_crtc_state *crtc_state,
794 struct drm_connector_state *conn_state)
795 {
796 struct dpu_encoder_virt *dpu_enc;
797 struct msm_drm_private *priv;
798 struct dpu_kms *dpu_kms;
799 struct drm_display_mode *adj_mode;
800 struct msm_display_topology topology;
801 struct dpu_global_state *global_state;
802 int ret = 0;
803
804 if (!drm_enc || !crtc_state || !conn_state) {
805 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
806 drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
807 return -EINVAL;
808 }
809
810 dpu_enc = to_dpu_encoder_virt(drm_enc);
811 DPU_DEBUG_ENC(dpu_enc, "\n");
812
813 priv = drm_enc->dev->dev_private;
814 dpu_kms = to_dpu_kms(priv->kms);
815 adj_mode = &crtc_state->adjusted_mode;
816 global_state = dpu_kms_get_global_state(crtc_state->state);
817 if (IS_ERR(global_state))
818 return PTR_ERR(global_state);
819
820 trace_dpu_enc_atomic_check(DRMID(drm_enc));
821
822 topology = dpu_encoder_get_topology(dpu_enc, adj_mode, crtc_state, conn_state);
823
824 /*
825 * Release and Allocate resources on every modeset
826 */
827 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
828 dpu_rm_release(global_state, drm_enc);
829
830 if (crtc_state->enable)
831 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
832 drm_enc, crtc_state, &topology);
833 if (!ret)
834 dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc,
835 global_state, crtc_state);
836 }
837
838 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
839
840 return ret;
841 }
842
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)843 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
844 struct msm_display_info *disp_info)
845 {
846 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
847 struct msm_drm_private *priv;
848 struct dpu_kms *dpu_kms;
849 struct dpu_hw_mdp *hw_mdptop;
850 struct drm_encoder *drm_enc;
851 struct dpu_encoder_phys *phys_enc;
852 int i;
853
854 if (!dpu_enc || !disp_info) {
855 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
856 dpu_enc != NULL, disp_info != NULL);
857 return;
858 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
859 DPU_ERROR("invalid num phys enc %d/%d\n",
860 dpu_enc->num_phys_encs,
861 (int) ARRAY_SIZE(dpu_enc->hw_pp));
862 return;
863 }
864
865 drm_enc = &dpu_enc->base;
866 /* this pointers are checked in virt_enable_helper */
867 priv = drm_enc->dev->dev_private;
868
869 dpu_kms = to_dpu_kms(priv->kms);
870 hw_mdptop = dpu_kms->hw_mdp;
871 if (!hw_mdptop) {
872 DPU_ERROR("invalid mdptop\n");
873 return;
874 }
875
876 if (hw_mdptop->ops.setup_vsync_source) {
877 for (i = 0; i < dpu_enc->num_phys_encs; i++)
878 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
879
880 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
881 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
882
883 vsync_cfg.vsync_source = disp_info->vsync_source;
884
885 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
886
887 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
888 phys_enc = dpu_enc->phys_encs[i];
889
890 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
891 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
892 vsync_cfg.vsync_source);
893 }
894 }
895 }
896
_dpu_encoder_irq_enable(struct drm_encoder * drm_enc)897 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc)
898 {
899 struct dpu_encoder_virt *dpu_enc;
900 int i;
901
902 if (!drm_enc) {
903 DPU_ERROR("invalid encoder\n");
904 return;
905 }
906
907 dpu_enc = to_dpu_encoder_virt(drm_enc);
908
909 DPU_DEBUG_ENC(dpu_enc, "\n");
910 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
911 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
912
913 phys->ops.irq_enable(phys);
914 }
915 }
916
_dpu_encoder_irq_disable(struct drm_encoder * drm_enc)917 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc)
918 {
919 struct dpu_encoder_virt *dpu_enc;
920 int i;
921
922 if (!drm_enc) {
923 DPU_ERROR("invalid encoder\n");
924 return;
925 }
926
927 dpu_enc = to_dpu_encoder_virt(drm_enc);
928
929 DPU_DEBUG_ENC(dpu_enc, "\n");
930 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
931 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
932
933 phys->ops.irq_disable(phys);
934 }
935 }
936
_dpu_encoder_resource_enable(struct drm_encoder * drm_enc)937 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc)
938 {
939 struct msm_drm_private *priv;
940 struct dpu_kms *dpu_kms;
941 struct dpu_encoder_virt *dpu_enc;
942
943 dpu_enc = to_dpu_encoder_virt(drm_enc);
944 priv = drm_enc->dev->dev_private;
945 dpu_kms = to_dpu_kms(priv->kms);
946
947 trace_dpu_enc_rc_enable(DRMID(drm_enc));
948
949 if (!dpu_enc->cur_master) {
950 DPU_ERROR("encoder master not set\n");
951 return;
952 }
953
954 /* enable DPU core clks */
955 pm_runtime_get_sync(&dpu_kms->pdev->dev);
956
957 /* enable all the irq */
958 _dpu_encoder_irq_enable(drm_enc);
959 }
960
_dpu_encoder_resource_disable(struct drm_encoder * drm_enc)961 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc)
962 {
963 struct msm_drm_private *priv;
964 struct dpu_kms *dpu_kms;
965 struct dpu_encoder_virt *dpu_enc;
966
967 dpu_enc = to_dpu_encoder_virt(drm_enc);
968 priv = drm_enc->dev->dev_private;
969 dpu_kms = to_dpu_kms(priv->kms);
970
971 trace_dpu_enc_rc_disable(DRMID(drm_enc));
972
973 if (!dpu_enc->cur_master) {
974 DPU_ERROR("encoder master not set\n");
975 return;
976 }
977
978 /* disable all the irq */
979 _dpu_encoder_irq_disable(drm_enc);
980
981 /* disable DPU core clks */
982 pm_runtime_put_sync(&dpu_kms->pdev->dev);
983 }
984
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)985 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
986 u32 sw_event)
987 {
988 struct dpu_encoder_virt *dpu_enc;
989 struct msm_drm_private *priv;
990 bool is_vid_mode = false;
991
992 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
993 DPU_ERROR("invalid parameters\n");
994 return -EINVAL;
995 }
996 dpu_enc = to_dpu_encoder_virt(drm_enc);
997 priv = drm_enc->dev->dev_private;
998 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
999
1000 /*
1001 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
1002 * events and return early for other events (ie wb display).
1003 */
1004 if (!dpu_enc->idle_pc_supported &&
1005 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
1006 sw_event != DPU_ENC_RC_EVENT_STOP &&
1007 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
1008 return 0;
1009
1010 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
1011 dpu_enc->rc_state, "begin");
1012
1013 switch (sw_event) {
1014 case DPU_ENC_RC_EVENT_KICKOFF:
1015 /* cancel delayed off work, if any */
1016 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
1017 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
1018 sw_event);
1019
1020 mutex_lock(&dpu_enc->rc_lock);
1021
1022 /* return if the resource control is already in ON state */
1023 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
1024 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
1025 DRMID(drm_enc), sw_event);
1026 mutex_unlock(&dpu_enc->rc_lock);
1027 return 0;
1028 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
1029 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
1030 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
1031 DRMID(drm_enc), sw_event,
1032 dpu_enc->rc_state);
1033 mutex_unlock(&dpu_enc->rc_lock);
1034 return -EINVAL;
1035 }
1036
1037 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
1038 _dpu_encoder_irq_enable(drm_enc);
1039 else
1040 _dpu_encoder_resource_enable(drm_enc);
1041
1042 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
1043
1044 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1045 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1046 "kickoff");
1047
1048 mutex_unlock(&dpu_enc->rc_lock);
1049 break;
1050
1051 case DPU_ENC_RC_EVENT_FRAME_DONE:
1052 /*
1053 * mutex lock is not used as this event happens at interrupt
1054 * context. And locking is not required as, the other events
1055 * like KICKOFF and STOP does a wait-for-idle before executing
1056 * the resource_control
1057 */
1058 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
1059 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
1060 DRMID(drm_enc), sw_event,
1061 dpu_enc->rc_state);
1062 return -EINVAL;
1063 }
1064
1065 /*
1066 * schedule off work item only when there are no
1067 * frames pending
1068 */
1069 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
1070 DRM_DEBUG_KMS("id:%d skip schedule work\n",
1071 DRMID(drm_enc));
1072 return 0;
1073 }
1074
1075 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
1076 msecs_to_jiffies(dpu_enc->idle_timeout));
1077
1078 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1079 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1080 "frame done");
1081 break;
1082
1083 case DPU_ENC_RC_EVENT_PRE_STOP:
1084 /* cancel delayed off work, if any */
1085 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
1086 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
1087 sw_event);
1088
1089 mutex_lock(&dpu_enc->rc_lock);
1090
1091 if (is_vid_mode &&
1092 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
1093 _dpu_encoder_irq_enable(drm_enc);
1094 }
1095 /* skip if is already OFF or IDLE, resources are off already */
1096 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
1097 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
1098 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
1099 DRMID(drm_enc), sw_event,
1100 dpu_enc->rc_state);
1101 mutex_unlock(&dpu_enc->rc_lock);
1102 return 0;
1103 }
1104
1105 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
1106
1107 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1108 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1109 "pre stop");
1110
1111 mutex_unlock(&dpu_enc->rc_lock);
1112 break;
1113
1114 case DPU_ENC_RC_EVENT_STOP:
1115 mutex_lock(&dpu_enc->rc_lock);
1116
1117 /* return if the resource control is already in OFF state */
1118 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
1119 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
1120 DRMID(drm_enc), sw_event);
1121 mutex_unlock(&dpu_enc->rc_lock);
1122 return 0;
1123 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
1124 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
1125 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1126 mutex_unlock(&dpu_enc->rc_lock);
1127 return -EINVAL;
1128 }
1129
1130 /**
1131 * expect to arrive here only if in either idle state or pre-off
1132 * and in IDLE state the resources are already disabled
1133 */
1134 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
1135 _dpu_encoder_resource_disable(drm_enc);
1136
1137 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
1138
1139 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1140 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1141 "stop");
1142
1143 mutex_unlock(&dpu_enc->rc_lock);
1144 break;
1145
1146 case DPU_ENC_RC_EVENT_ENTER_IDLE:
1147 mutex_lock(&dpu_enc->rc_lock);
1148
1149 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
1150 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
1151 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1152 mutex_unlock(&dpu_enc->rc_lock);
1153 return 0;
1154 }
1155
1156 /*
1157 * if we are in ON but a frame was just kicked off,
1158 * ignore the IDLE event, it's probably a stale timer event
1159 */
1160 if (dpu_enc->frame_busy_mask[0]) {
1161 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
1162 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1163 mutex_unlock(&dpu_enc->rc_lock);
1164 return 0;
1165 }
1166
1167 if (is_vid_mode)
1168 _dpu_encoder_irq_disable(drm_enc);
1169 else
1170 _dpu_encoder_resource_disable(drm_enc);
1171
1172 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
1173
1174 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1175 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1176 "idle");
1177
1178 mutex_unlock(&dpu_enc->rc_lock);
1179 break;
1180
1181 default:
1182 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
1183 sw_event);
1184 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1185 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1186 "error");
1187 break;
1188 }
1189
1190 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1191 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1192 "end");
1193 return 0;
1194 }
1195
1196 /**
1197 * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder.
1198 * @drm_enc: Pointer to previously created drm encoder structure
1199 * @job: Pointer to the current drm writeback job
1200 */
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1201 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
1202 struct drm_writeback_job *job)
1203 {
1204 struct dpu_encoder_virt *dpu_enc;
1205 int i;
1206
1207 dpu_enc = to_dpu_encoder_virt(drm_enc);
1208
1209 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1210 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1211
1212 if (phys->ops.prepare_wb_job)
1213 phys->ops.prepare_wb_job(phys, job);
1214
1215 }
1216 }
1217
1218 /**
1219 * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder.
1220 * @drm_enc: Pointer to previously created drm encoder structure
1221 * @job: Pointer to the current drm writeback job
1222 */
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1223 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1224 struct drm_writeback_job *job)
1225 {
1226 struct dpu_encoder_virt *dpu_enc;
1227 int i;
1228
1229 dpu_enc = to_dpu_encoder_virt(drm_enc);
1230
1231 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1232 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1233
1234 if (phys->ops.cleanup_wb_job)
1235 phys->ops.cleanup_wb_job(phys, job);
1236
1237 }
1238 }
1239
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1240 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1241 struct drm_crtc_state *crtc_state,
1242 struct drm_connector_state *conn_state)
1243 {
1244 struct dpu_encoder_virt *dpu_enc;
1245 struct msm_drm_private *priv;
1246 struct dpu_kms *dpu_kms;
1247 struct dpu_global_state *global_state;
1248 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1249 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1250 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1251 int num_ctl, num_pp, num_dsc;
1252 unsigned int dsc_mask = 0;
1253 int i;
1254
1255 if (!drm_enc) {
1256 DPU_ERROR("invalid encoder\n");
1257 return;
1258 }
1259
1260 dpu_enc = to_dpu_encoder_virt(drm_enc);
1261 DPU_DEBUG_ENC(dpu_enc, "\n");
1262
1263 priv = drm_enc->dev->dev_private;
1264 dpu_kms = to_dpu_kms(priv->kms);
1265
1266 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1267 if (IS_ERR_OR_NULL(global_state)) {
1268 DPU_ERROR("Failed to get global state");
1269 return;
1270 }
1271
1272 trace_dpu_enc_mode_set(DRMID(drm_enc));
1273
1274 /* Query resource that have been reserved in atomic check step. */
1275 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1276 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1277 ARRAY_SIZE(hw_pp));
1278 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1279 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1280
1281 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1282 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1283 : NULL;
1284
1285 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1286 drm_enc->base.id, DPU_HW_BLK_DSC,
1287 hw_dsc, ARRAY_SIZE(hw_dsc));
1288 for (i = 0; i < num_dsc; i++) {
1289 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1290 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1291 }
1292
1293 dpu_enc->dsc_mask = dsc_mask;
1294
1295 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
1296 dpu_enc->disp_info.intf_type == INTF_DP) {
1297 struct dpu_hw_blk *hw_cdm = NULL;
1298
1299 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1300 drm_enc->base.id, DPU_HW_BLK_CDM,
1301 &hw_cdm, 1);
1302 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
1303 }
1304
1305 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1306 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1307
1308 phys->hw_pp = dpu_enc->hw_pp[i];
1309 if (!phys->hw_pp) {
1310 DPU_ERROR_ENC(dpu_enc,
1311 "no pp block assigned at idx: %d\n", i);
1312 return;
1313 }
1314
1315 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
1316 if (!phys->hw_ctl) {
1317 DPU_ERROR_ENC(dpu_enc,
1318 "no ctl block assigned at idx: %d\n", i);
1319 return;
1320 }
1321
1322 phys->cached_mode = crtc_state->adjusted_mode;
1323 if (phys->ops.atomic_mode_set)
1324 phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1325 }
1326 }
1327
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1328 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1329 {
1330 struct dpu_encoder_virt *dpu_enc = NULL;
1331 int i;
1332
1333 if (!drm_enc || !drm_enc->dev) {
1334 DPU_ERROR("invalid parameters\n");
1335 return;
1336 }
1337
1338 dpu_enc = to_dpu_encoder_virt(drm_enc);
1339 if (!dpu_enc || !dpu_enc->cur_master) {
1340 DPU_ERROR("invalid dpu encoder/master\n");
1341 return;
1342 }
1343
1344
1345 if (dpu_enc->disp_info.intf_type == INTF_DP &&
1346 dpu_enc->cur_master->hw_mdptop &&
1347 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1348 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1349 dpu_enc->cur_master->hw_mdptop);
1350
1351 if (dpu_enc->disp_info.is_cmd_mode)
1352 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1353
1354 if (dpu_enc->disp_info.intf_type == INTF_DSI &&
1355 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1356 unsigned bpc = dpu_enc->connector->display_info.bpc;
1357 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1358 if (!dpu_enc->hw_pp[i])
1359 continue;
1360 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1361 }
1362 }
1363 }
1364
1365 /**
1366 * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs
1367 * @drm_enc: encoder pointer
1368 */
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1369 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1370 {
1371 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1372
1373 mutex_lock(&dpu_enc->enc_lock);
1374
1375 if (!dpu_enc->enabled)
1376 goto out;
1377
1378 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1379 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1380 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1381 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1382
1383 _dpu_encoder_virt_enable_helper(drm_enc);
1384
1385 out:
1386 mutex_unlock(&dpu_enc->enc_lock);
1387 }
1388
dpu_encoder_virt_atomic_enable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1389 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
1390 struct drm_atomic_state *state)
1391 {
1392 struct dpu_encoder_virt *dpu_enc = NULL;
1393 int ret = 0;
1394 struct drm_display_mode *cur_mode = NULL;
1395
1396 dpu_enc = to_dpu_encoder_virt(drm_enc);
1397 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
1398
1399 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
1400
1401 mutex_lock(&dpu_enc->enc_lock);
1402
1403 dpu_enc->commit_done_timedout = false;
1404
1405 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1406
1407 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1408
1409 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc);
1410
1411 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1412 cur_mode->vdisplay);
1413
1414 /* always enable slave encoder before master */
1415 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1416 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1417
1418 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1419 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1420
1421 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1422 if (ret) {
1423 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1424 ret);
1425 goto out;
1426 }
1427
1428 _dpu_encoder_virt_enable_helper(drm_enc);
1429
1430 dpu_enc->enabled = true;
1431
1432 out:
1433 mutex_unlock(&dpu_enc->enc_lock);
1434 }
1435
dpu_encoder_virt_atomic_disable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1436 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
1437 struct drm_atomic_state *state)
1438 {
1439 struct dpu_encoder_virt *dpu_enc = NULL;
1440 struct drm_crtc *crtc;
1441 struct drm_crtc_state *old_state = NULL;
1442 int i = 0;
1443
1444 dpu_enc = to_dpu_encoder_virt(drm_enc);
1445 DPU_DEBUG_ENC(dpu_enc, "\n");
1446
1447 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
1448 if (crtc)
1449 old_state = drm_atomic_get_old_crtc_state(state, crtc);
1450
1451 /*
1452 * The encoder is already disabled if self refresh mode was set earlier,
1453 * in the old_state for the corresponding crtc.
1454 */
1455 if (old_state && old_state->self_refresh_active)
1456 return;
1457
1458 mutex_lock(&dpu_enc->enc_lock);
1459 dpu_enc->enabled = false;
1460
1461 trace_dpu_enc_disable(DRMID(drm_enc));
1462
1463 /* wait for idle */
1464 dpu_encoder_wait_for_tx_complete(drm_enc);
1465
1466 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1467
1468 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1469 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1470
1471 if (phys->ops.disable)
1472 phys->ops.disable(phys);
1473 }
1474
1475
1476 /* after phys waits for frame-done, should be no more frames pending */
1477 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1478 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1479 del_timer_sync(&dpu_enc->frame_done_timer);
1480 }
1481
1482 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1483
1484 dpu_enc->connector = NULL;
1485
1486 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1487
1488 mutex_unlock(&dpu_enc->enc_lock);
1489 }
1490
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,struct dpu_rm * dpu_rm,enum dpu_intf_type type,u32 controller_id)1491 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1492 struct dpu_rm *dpu_rm,
1493 enum dpu_intf_type type, u32 controller_id)
1494 {
1495 int i = 0;
1496
1497 if (type == INTF_WB)
1498 return NULL;
1499
1500 for (i = 0; i < catalog->intf_count; i++) {
1501 if (catalog->intf[i].type == type
1502 && catalog->intf[i].controller_id == controller_id) {
1503 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
1504 }
1505 }
1506
1507 return NULL;
1508 }
1509
1510 /**
1511 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
1512 * @drm_enc: Pointer to drm encoder structure
1513 * @phy_enc: Pointer to physical encoder
1514 * Note: This is called from IRQ handler context.
1515 */
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1516 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1517 struct dpu_encoder_phys *phy_enc)
1518 {
1519 struct dpu_encoder_virt *dpu_enc = NULL;
1520 unsigned long lock_flags;
1521
1522 if (!drm_enc || !phy_enc)
1523 return;
1524
1525 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1526 dpu_enc = to_dpu_encoder_virt(drm_enc);
1527
1528 atomic_inc(&phy_enc->vsync_cnt);
1529
1530 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1531 if (dpu_enc->crtc)
1532 dpu_crtc_vblank_callback(dpu_enc->crtc);
1533 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1534
1535 DPU_ATRACE_END("encoder_vblank_callback");
1536 }
1537
1538 /**
1539 * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
1540 * @drm_enc: Pointer to drm encoder structure
1541 * @phy_enc: Pointer to physical encoder
1542 * Note: This is called from IRQ handler context.
1543 */
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1544 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1545 struct dpu_encoder_phys *phy_enc)
1546 {
1547 if (!phy_enc)
1548 return;
1549
1550 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1551 atomic_inc(&phy_enc->underrun_cnt);
1552
1553 /* trigger dump only on the first underrun */
1554 if (atomic_read(&phy_enc->underrun_cnt) == 1)
1555 msm_disp_snapshot_state(drm_enc->dev);
1556
1557 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1558 atomic_read(&phy_enc->underrun_cnt));
1559 DPU_ATRACE_END("encoder_underrun_callback");
1560 }
1561
1562 /**
1563 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to
1564 * @drm_enc: encoder pointer
1565 * @crtc: crtc pointer
1566 */
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1567 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1568 {
1569 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1570 unsigned long lock_flags;
1571
1572 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1573 /* crtc should always be cleared before re-assigning */
1574 WARN_ON(crtc && dpu_enc->crtc);
1575 dpu_enc->crtc = crtc;
1576 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1577 }
1578
1579 /**
1580 * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if
1581 * the encoder is assigned to the given crtc
1582 * @drm_enc: encoder pointer
1583 * @crtc: crtc pointer
1584 * @enable: true if vblank should be enabled
1585 */
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1586 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1587 struct drm_crtc *crtc, bool enable)
1588 {
1589 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1590 unsigned long lock_flags;
1591 int i;
1592
1593 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1594
1595 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1596 if (dpu_enc->crtc != crtc) {
1597 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1598 return;
1599 }
1600 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1601
1602 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1603 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1604
1605 if (phys->ops.control_vblank_irq)
1606 phys->ops.control_vblank_irq(phys, enable);
1607 }
1608 }
1609
1610 /**
1611 * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys
1612 * encoder completes last request frame
1613 * @drm_enc: Pointer to drm encoder structure
1614 * @ready_phys: Pointer to physical encoder
1615 * @event: Event to process
1616 */
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1617 void dpu_encoder_frame_done_callback(
1618 struct drm_encoder *drm_enc,
1619 struct dpu_encoder_phys *ready_phys, u32 event)
1620 {
1621 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1622 unsigned int i;
1623
1624 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1625 | DPU_ENCODER_FRAME_EVENT_ERROR
1626 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1627
1628 if (!dpu_enc->frame_busy_mask[0]) {
1629 /**
1630 * suppress frame_done without waiter,
1631 * likely autorefresh
1632 */
1633 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1634 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1635 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,
1636 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);
1637 return;
1638 }
1639
1640 /* One of the physical encoders has become idle */
1641 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1642 if (dpu_enc->phys_encs[i] == ready_phys) {
1643 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1644 dpu_enc->frame_busy_mask[0]);
1645 clear_bit(i, dpu_enc->frame_busy_mask);
1646 }
1647 }
1648
1649 if (!dpu_enc->frame_busy_mask[0]) {
1650 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1651 del_timer(&dpu_enc->frame_done_timer);
1652
1653 dpu_encoder_resource_control(drm_enc,
1654 DPU_ENC_RC_EVENT_FRAME_DONE);
1655
1656 if (dpu_enc->crtc)
1657 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1658 }
1659 } else {
1660 if (dpu_enc->crtc)
1661 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1662 }
1663 }
1664
dpu_encoder_off_work(struct work_struct * work)1665 static void dpu_encoder_off_work(struct work_struct *work)
1666 {
1667 struct dpu_encoder_virt *dpu_enc = container_of(work,
1668 struct dpu_encoder_virt, delayed_off_work.work);
1669
1670 dpu_encoder_resource_control(&dpu_enc->base,
1671 DPU_ENC_RC_EVENT_ENTER_IDLE);
1672
1673 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1674 DPU_ENCODER_FRAME_EVENT_IDLE);
1675 }
1676
1677 /**
1678 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1679 * @drm_enc: Pointer to drm encoder structure
1680 * @phys: Pointer to physical encoder structure
1681 * @extra_flush_bits: Additional bit mask to include in flush trigger
1682 */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1683 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1684 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1685 {
1686 struct dpu_hw_ctl *ctl;
1687 int pending_kickoff_cnt;
1688 u32 ret = UINT_MAX;
1689
1690 if (!phys->hw_pp) {
1691 DPU_ERROR("invalid pingpong hw\n");
1692 return;
1693 }
1694
1695 ctl = phys->hw_ctl;
1696 if (!ctl->ops.trigger_flush) {
1697 DPU_ERROR("missing trigger cb\n");
1698 return;
1699 }
1700
1701 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1702
1703 if (extra_flush_bits && ctl->ops.update_pending_flush)
1704 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1705
1706 ctl->ops.trigger_flush(ctl);
1707
1708 if (ctl->ops.get_pending_flush)
1709 ret = ctl->ops.get_pending_flush(ctl);
1710
1711 trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1712 dpu_encoder_helper_get_intf_type(phys->intf_mode),
1713 phys->hw_intf ? phys->hw_intf->idx : -1,
1714 phys->hw_wb ? phys->hw_wb->idx : -1,
1715 pending_kickoff_cnt, ctl->idx,
1716 extra_flush_bits, ret);
1717 }
1718
1719 /**
1720 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1721 * @phys: Pointer to physical encoder structure
1722 */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1723 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1724 {
1725 if (!phys) {
1726 DPU_ERROR("invalid argument(s)\n");
1727 return;
1728 }
1729
1730 if (!phys->hw_pp) {
1731 DPU_ERROR("invalid pingpong hw\n");
1732 return;
1733 }
1734
1735 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1736 phys->ops.trigger_start(phys);
1737 }
1738
1739 /**
1740 * dpu_encoder_helper_trigger_start - control start helper function
1741 * This helper function may be optionally specified by physical
1742 * encoders if they require ctl_start triggering.
1743 * @phys_enc: Pointer to physical encoder structure
1744 */
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1745 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1746 {
1747 struct dpu_hw_ctl *ctl;
1748
1749 ctl = phys_enc->hw_ctl;
1750 if (ctl->ops.trigger_start) {
1751 ctl->ops.trigger_start(ctl);
1752 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1753 }
1754 }
1755
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,unsigned int irq_idx,struct dpu_encoder_wait_info * info)1756 static int dpu_encoder_helper_wait_event_timeout(
1757 int32_t drm_id,
1758 unsigned int irq_idx,
1759 struct dpu_encoder_wait_info *info)
1760 {
1761 int rc = 0;
1762 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1763 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1764 s64 time;
1765
1766 do {
1767 rc = wait_event_timeout(*(info->wq),
1768 atomic_read(info->atomic_cnt) == 0, jiffies);
1769 time = ktime_to_ms(ktime_get());
1770
1771 trace_dpu_enc_wait_event_timeout(drm_id,
1772 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
1773 rc, time,
1774 expected_time,
1775 atomic_read(info->atomic_cnt));
1776 /* If we timed out, counter is valid and time is less, wait again */
1777 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1778 (time < expected_time));
1779
1780 return rc;
1781 }
1782
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1783 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1784 {
1785 struct dpu_encoder_virt *dpu_enc;
1786 struct dpu_hw_ctl *ctl;
1787 int rc;
1788 struct drm_encoder *drm_enc;
1789
1790 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1791 ctl = phys_enc->hw_ctl;
1792 drm_enc = phys_enc->parent;
1793
1794 if (!ctl->ops.reset)
1795 return;
1796
1797 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1798 ctl->idx);
1799
1800 rc = ctl->ops.reset(ctl);
1801 if (rc) {
1802 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1803 msm_disp_snapshot_state(drm_enc->dev);
1804 }
1805
1806 phys_enc->enable_state = DPU_ENC_ENABLED;
1807 }
1808
1809 /**
1810 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1811 * Iterate through the physical encoders and perform consolidated flush
1812 * and/or control start triggering as needed. This is done in the virtual
1813 * encoder rather than the individual physical ones in order to handle
1814 * use cases that require visibility into multiple physical encoders at
1815 * a time.
1816 * @dpu_enc: Pointer to virtual encoder structure
1817 */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1818 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1819 {
1820 struct dpu_hw_ctl *ctl;
1821 uint32_t i, pending_flush;
1822 unsigned long lock_flags;
1823
1824 pending_flush = 0x0;
1825
1826 /* update pending counts and trigger kickoff ctl flush atomically */
1827 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1828
1829 /* don't perform flush/start operations for slave encoders */
1830 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1831 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1832
1833 if (phys->enable_state == DPU_ENC_DISABLED)
1834 continue;
1835
1836 ctl = phys->hw_ctl;
1837
1838 /*
1839 * This is cleared in frame_done worker, which isn't invoked
1840 * for async commits. So don't set this for async, since it'll
1841 * roll over to the next commit.
1842 */
1843 if (phys->split_role != ENC_ROLE_SLAVE)
1844 set_bit(i, dpu_enc->frame_busy_mask);
1845
1846 if (!phys->ops.needs_single_flush ||
1847 !phys->ops.needs_single_flush(phys))
1848 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1849 else if (ctl->ops.get_pending_flush)
1850 pending_flush |= ctl->ops.get_pending_flush(ctl);
1851 }
1852
1853 /* for split flush, combine pending flush masks and send to master */
1854 if (pending_flush && dpu_enc->cur_master) {
1855 _dpu_encoder_trigger_flush(
1856 &dpu_enc->base,
1857 dpu_enc->cur_master,
1858 pending_flush);
1859 }
1860
1861 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1862
1863 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1864 }
1865
1866 /**
1867 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous
1868 * kickoff and trigger the ctl prepare progress for command mode display.
1869 * @drm_enc: encoder pointer
1870 */
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1871 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1872 {
1873 struct dpu_encoder_virt *dpu_enc;
1874 struct dpu_encoder_phys *phys;
1875 unsigned int i;
1876 struct dpu_hw_ctl *ctl;
1877 struct msm_display_info *disp_info;
1878
1879 if (!drm_enc) {
1880 DPU_ERROR("invalid encoder\n");
1881 return;
1882 }
1883 dpu_enc = to_dpu_encoder_virt(drm_enc);
1884 disp_info = &dpu_enc->disp_info;
1885
1886 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1887 phys = dpu_enc->phys_encs[i];
1888
1889 ctl = phys->hw_ctl;
1890 ctl->ops.clear_pending_flush(ctl);
1891
1892 /* update only for command mode primary ctl */
1893 if ((phys == dpu_enc->cur_master) &&
1894 disp_info->is_cmd_mode
1895 && ctl->ops.trigger_pending)
1896 ctl->ops.trigger_pending(ctl);
1897 }
1898 }
1899
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1900 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1901 struct drm_display_mode *mode)
1902 {
1903 u64 pclk_rate;
1904 u32 pclk_period;
1905 u32 line_time;
1906
1907 /*
1908 * For linetime calculation, only operate on master encoder.
1909 */
1910 if (!dpu_enc->cur_master)
1911 return 0;
1912
1913 if (!dpu_enc->cur_master->ops.get_line_count) {
1914 DPU_ERROR("get_line_count function not defined\n");
1915 return 0;
1916 }
1917
1918 pclk_rate = mode->clock; /* pixel clock in kHz */
1919 if (pclk_rate == 0) {
1920 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1921 return 0;
1922 }
1923
1924 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1925 if (pclk_period == 0) {
1926 DPU_ERROR("pclk period is 0\n");
1927 return 0;
1928 }
1929
1930 /*
1931 * Line time calculation based on Pixel clock and HTOTAL.
1932 * Final unit is in ns.
1933 */
1934 line_time = (pclk_period * mode->htotal) / 1000;
1935 if (line_time == 0) {
1936 DPU_ERROR("line time calculation is 0\n");
1937 return 0;
1938 }
1939
1940 DPU_DEBUG_ENC(dpu_enc,
1941 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1942 pclk_rate, pclk_period, line_time);
1943
1944 return line_time;
1945 }
1946
1947 /**
1948 * dpu_encoder_vsync_time - get the time of the next vsync
1949 * @drm_enc: encoder pointer
1950 * @wakeup_time: pointer to ktime_t to write the vsync time to
1951 */
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1952 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1953 {
1954 struct drm_display_mode *mode;
1955 struct dpu_encoder_virt *dpu_enc;
1956 u32 cur_line;
1957 u32 line_time;
1958 u32 vtotal, time_to_vsync;
1959 ktime_t cur_time;
1960
1961 dpu_enc = to_dpu_encoder_virt(drm_enc);
1962
1963 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1964 DPU_ERROR("crtc/crtc state object is NULL\n");
1965 return -EINVAL;
1966 }
1967 mode = &drm_enc->crtc->state->adjusted_mode;
1968
1969 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1970 if (!line_time)
1971 return -EINVAL;
1972
1973 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1974
1975 vtotal = mode->vtotal;
1976 if (cur_line >= vtotal)
1977 time_to_vsync = line_time * vtotal;
1978 else
1979 time_to_vsync = line_time * (vtotal - cur_line);
1980
1981 if (time_to_vsync == 0) {
1982 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1983 vtotal);
1984 return -EINVAL;
1985 }
1986
1987 cur_time = ktime_get();
1988 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1989
1990 DPU_DEBUG_ENC(dpu_enc,
1991 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1992 cur_line, vtotal, time_to_vsync,
1993 ktime_to_ms(cur_time),
1994 ktime_to_ms(*wakeup_time));
1995 return 0;
1996 }
1997
1998 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1999 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
2000 u32 enc_ip_width)
2001 {
2002 int ssm_delay, total_pixels, soft_slice_per_enc;
2003
2004 soft_slice_per_enc = enc_ip_width / dsc->slice_width;
2005
2006 /*
2007 * minimum number of initial line pixels is a sum of:
2008 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
2009 * 91 for 10 bpc) * 3
2010 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
2011 * 3. the initial xmit delay
2012 * 4. total pipeline delay through the "lock step" of encoder (47)
2013 * 5. 6 additional pixels as the output of the rate buffer is
2014 * 48 bits wide
2015 */
2016 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
2017 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
2018 if (soft_slice_per_enc > 1)
2019 total_pixels += (ssm_delay * 3);
2020 return DIV_ROUND_UP(total_pixels, dsc->slice_width);
2021 }
2022
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)2023 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
2024 struct dpu_hw_dsc *hw_dsc,
2025 struct dpu_hw_pingpong *hw_pp,
2026 struct drm_dsc_config *dsc,
2027 u32 common_mode,
2028 u32 initial_lines)
2029 {
2030 if (hw_dsc->ops.dsc_config)
2031 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
2032
2033 if (hw_dsc->ops.dsc_config_thresh)
2034 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
2035
2036 if (hw_pp->ops.setup_dsc)
2037 hw_pp->ops.setup_dsc(hw_pp);
2038
2039 if (hw_dsc->ops.dsc_bind_pingpong_blk)
2040 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx);
2041
2042 if (hw_pp->ops.enable_dsc)
2043 hw_pp->ops.enable_dsc(hw_pp);
2044
2045 if (ctl->ops.update_pending_flush_dsc)
2046 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2047 }
2048
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)2049 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
2050 struct drm_dsc_config *dsc)
2051 {
2052 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2053 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2054 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2055 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2056 int this_frame_slices;
2057 int intf_ip_w, enc_ip_w;
2058 int dsc_common_mode;
2059 int pic_width;
2060 u32 initial_lines;
2061 int num_dsc = 0;
2062 int i;
2063
2064 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2065 hw_pp[i] = dpu_enc->hw_pp[i];
2066 hw_dsc[i] = dpu_enc->hw_dsc[i];
2067
2068 if (!hw_pp[i] || !hw_dsc[i])
2069 break;
2070
2071 num_dsc++;
2072 }
2073
2074 pic_width = dsc->pic_width;
2075
2076 dsc_common_mode = 0;
2077 if (num_dsc > 1)
2078 dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
2079 if (dpu_encoder_use_dsc_merge(enc_master->parent))
2080 dsc_common_mode |= DSC_MODE_MULTIPLEX;
2081 if (enc_master->intf_mode == INTF_MODE_VIDEO)
2082 dsc_common_mode |= DSC_MODE_VIDEO;
2083
2084 this_frame_slices = pic_width / dsc->slice_width;
2085 intf_ip_w = this_frame_slices * dsc->slice_width;
2086
2087 enc_ip_w = intf_ip_w / num_dsc;
2088 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
2089
2090 for (i = 0; i < num_dsc; i++)
2091 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
2092 dsc, dsc_common_mode, initial_lines);
2093 }
2094
2095 /**
2096 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
2097 * path (i.e. ctl flush and start) at next appropriate time.
2098 * Immediately: if no previous commit is outstanding.
2099 * Delayed: Block until next trigger can be issued.
2100 * @drm_enc: encoder pointer
2101 */
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)2102 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
2103 {
2104 struct dpu_encoder_virt *dpu_enc;
2105 struct dpu_encoder_phys *phys;
2106 bool needs_hw_reset = false;
2107 unsigned int i;
2108
2109 dpu_enc = to_dpu_encoder_virt(drm_enc);
2110
2111 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
2112
2113 /* prepare for next kickoff, may include waiting on previous kickoff */
2114 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
2115 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2116 phys = dpu_enc->phys_encs[i];
2117 if (phys->ops.prepare_for_kickoff)
2118 phys->ops.prepare_for_kickoff(phys);
2119 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
2120 needs_hw_reset = true;
2121 }
2122 DPU_ATRACE_END("enc_prepare_for_kickoff");
2123
2124 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
2125
2126 /* if any phys needs reset, reset all phys, in-order */
2127 if (needs_hw_reset) {
2128 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
2129 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2130 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
2131 }
2132 }
2133
2134 if (dpu_enc->dsc)
2135 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
2136 }
2137
2138 /**
2139 * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit.
2140 * @drm_enc: Pointer to drm encoder structure
2141 */
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)2142 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
2143 {
2144 struct dpu_encoder_virt *dpu_enc;
2145 unsigned int i;
2146 struct dpu_encoder_phys *phys;
2147
2148 dpu_enc = to_dpu_encoder_virt(drm_enc);
2149
2150 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
2151 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2152 phys = dpu_enc->phys_encs[i];
2153 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
2154 DPU_DEBUG("invalid FB not kicking off\n");
2155 return false;
2156 }
2157 }
2158 }
2159
2160 return true;
2161 }
2162
2163 /**
2164 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path
2165 * (i.e. ctl flush and start) immediately.
2166 * @drm_enc: encoder pointer
2167 */
dpu_encoder_kickoff(struct drm_encoder * drm_enc)2168 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
2169 {
2170 struct dpu_encoder_virt *dpu_enc;
2171 struct dpu_encoder_phys *phys;
2172 unsigned long timeout_ms;
2173 unsigned int i;
2174
2175 DPU_ATRACE_BEGIN("encoder_kickoff");
2176 dpu_enc = to_dpu_encoder_virt(drm_enc);
2177
2178 trace_dpu_enc_kickoff(DRMID(drm_enc));
2179
2180 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
2181 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
2182
2183 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
2184 mod_timer(&dpu_enc->frame_done_timer,
2185 jiffies + msecs_to_jiffies(timeout_ms));
2186
2187 /* All phys encs are ready to go, trigger the kickoff */
2188 _dpu_encoder_kickoff_phys(dpu_enc);
2189
2190 /* allow phys encs to handle any post-kickoff business */
2191 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2192 phys = dpu_enc->phys_encs[i];
2193 if (phys->ops.handle_post_kickoff)
2194 phys->ops.handle_post_kickoff(phys);
2195 }
2196
2197 DPU_ATRACE_END("encoder_kickoff");
2198 }
2199
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)2200 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
2201 {
2202 struct dpu_hw_mixer_cfg mixer;
2203 int i, num_lm;
2204 struct dpu_global_state *global_state;
2205 struct dpu_hw_blk *hw_lm[2];
2206 struct dpu_hw_mixer *hw_mixer[2];
2207 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2208
2209 memset(&mixer, 0, sizeof(mixer));
2210
2211 /* reset all mixers for this encoder */
2212 if (phys_enc->hw_ctl->ops.clear_all_blendstages)
2213 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
2214
2215 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
2216
2217 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
2218 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
2219
2220 for (i = 0; i < num_lm; i++) {
2221 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
2222 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer)
2223 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2224
2225 /* clear all blendstages */
2226 if (phys_enc->hw_ctl->ops.setup_blendstage)
2227 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2228 }
2229 }
2230
dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp)2231 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
2232 struct dpu_hw_dsc *hw_dsc,
2233 struct dpu_hw_pingpong *hw_pp)
2234 {
2235 if (hw_dsc->ops.dsc_disable)
2236 hw_dsc->ops.dsc_disable(hw_dsc);
2237
2238 if (hw_pp->ops.disable_dsc)
2239 hw_pp->ops.disable_dsc(hw_pp);
2240
2241 if (hw_dsc->ops.dsc_bind_pingpong_blk)
2242 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
2243
2244 if (ctl->ops.update_pending_flush_dsc)
2245 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2246 }
2247
dpu_encoder_unprep_dsc(struct dpu_encoder_virt * dpu_enc)2248 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
2249 {
2250 /* coding only for 2LM, 2enc, 1 dsc config */
2251 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2252 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2253 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2254 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2255 int i;
2256
2257 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2258 hw_pp[i] = dpu_enc->hw_pp[i];
2259 hw_dsc[i] = dpu_enc->hw_dsc[i];
2260
2261 if (hw_pp[i] && hw_dsc[i])
2262 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
2263 }
2264 }
2265
2266 /**
2267 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
2268 * @phys_enc: Pointer to physical encoder structure
2269 */
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2270 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2271 {
2272 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2273 struct dpu_hw_intf_cfg intf_cfg = { 0 };
2274 int i;
2275 struct dpu_encoder_virt *dpu_enc;
2276
2277 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2278
2279 phys_enc->hw_ctl->ops.reset(ctl);
2280
2281 dpu_encoder_helper_reset_mixers(phys_enc);
2282
2283 /*
2284 * TODO: move the once-only operation like CTL flush/trigger
2285 * into dpu_encoder_virt_disable() and all operations which need
2286 * to be done per phys encoder into the phys_disable() op.
2287 */
2288 if (phys_enc->hw_wb) {
2289 /* disable the PP block */
2290 if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2291 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE);
2292
2293 /* mark WB flush as pending */
2294 if (phys_enc->hw_ctl->ops.update_pending_flush_wb)
2295 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2296 } else {
2297 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2298 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2299 phys_enc->hw_intf->ops.bind_pingpong_blk(
2300 dpu_enc->phys_encs[i]->hw_intf,
2301 PINGPONG_NONE);
2302
2303 /* mark INTF flush as pending */
2304 if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
2305 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
2306 dpu_enc->phys_encs[i]->hw_intf->idx);
2307 }
2308 }
2309
2310 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
2311 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
2312
2313 /* reset the merge 3D HW block */
2314 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
2315 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2316 BLEND_3D_NONE);
2317 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d)
2318 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
2319 phys_enc->hw_pp->merge_3d->idx);
2320 }
2321
2322 if (phys_enc->hw_cdm) {
2323 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp)
2324 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
2325 PINGPONG_NONE);
2326 if (phys_enc->hw_ctl->ops.update_pending_flush_cdm)
2327 phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl,
2328 phys_enc->hw_cdm->idx);
2329 }
2330
2331 if (dpu_enc->dsc) {
2332 dpu_encoder_unprep_dsc(dpu_enc);
2333 dpu_enc->dsc = NULL;
2334 }
2335
2336 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2337 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2338 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
2339
2340 if (phys_enc->hw_intf)
2341 intf_cfg.intf = phys_enc->hw_intf->idx;
2342 if (phys_enc->hw_wb)
2343 intf_cfg.wb = phys_enc->hw_wb->idx;
2344
2345 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d)
2346 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2347
2348 if (ctl->ops.reset_intf_cfg)
2349 ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2350
2351 ctl->ops.trigger_flush(ctl);
2352 ctl->ops.trigger_start(ctl);
2353 ctl->ops.clear_pending_flush(ctl);
2354 }
2355
2356 /**
2357 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
2358 * @phys_enc: Pointer to physical encoder
2359 * @dpu_fmt: Pinter to the format description
2360 * @output_type: HDMI/WB
2361 */
dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys * phys_enc,const struct msm_format * dpu_fmt,u32 output_type)2362 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
2363 const struct msm_format *dpu_fmt,
2364 u32 output_type)
2365 {
2366 struct dpu_hw_cdm *hw_cdm;
2367 struct dpu_hw_cdm_cfg *cdm_cfg;
2368 struct dpu_hw_pingpong *hw_pp;
2369 int ret;
2370
2371 if (!phys_enc)
2372 return;
2373
2374 cdm_cfg = &phys_enc->cdm_cfg;
2375 hw_pp = phys_enc->hw_pp;
2376 hw_cdm = phys_enc->hw_cdm;
2377
2378 if (!hw_cdm)
2379 return;
2380
2381 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
2382 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
2383 &dpu_fmt->pixel_format);
2384 if (hw_cdm->ops.bind_pingpong_blk)
2385 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
2386
2387 return;
2388 }
2389
2390 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
2391
2392 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
2393 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
2394 cdm_cfg->output_fmt = dpu_fmt;
2395 cdm_cfg->output_type = output_type;
2396 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
2397 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
2398 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
2399
2400 /* enable 10 bit logic */
2401 switch (cdm_cfg->output_fmt->chroma_sample) {
2402 case CHROMA_FULL:
2403 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2404 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2405 break;
2406 case CHROMA_H2V1:
2407 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2408 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2409 break;
2410 case CHROMA_420:
2411 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2412 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
2413 break;
2414 case CHROMA_H1V2:
2415 default:
2416 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
2417 DRMID(phys_enc->parent));
2418 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2419 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2420 break;
2421 }
2422
2423 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
2424 DRMID(phys_enc->parent), cdm_cfg->output_width,
2425 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
2426 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
2427 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
2428
2429 if (hw_cdm->ops.enable) {
2430 cdm_cfg->pp_id = hw_pp->idx;
2431 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
2432 if (ret < 0) {
2433 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
2434 DRMID(phys_enc->parent), ret);
2435 return;
2436 }
2437 }
2438 }
2439
2440 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2441 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2442 {
2443 struct drm_encoder *drm_enc = s->private;
2444 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2445 int i;
2446
2447 mutex_lock(&dpu_enc->enc_lock);
2448 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2449 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2450
2451 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d",
2452 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,
2453 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,
2454 atomic_read(&phys->vsync_cnt),
2455 atomic_read(&phys->underrun_cnt),
2456 atomic_read(&dpu_enc->frame_done_timeout_cnt));
2457
2458 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2459 }
2460 mutex_unlock(&dpu_enc->enc_lock);
2461
2462 return 0;
2463 }
2464
2465 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2466
dpu_encoder_debugfs_init(struct drm_encoder * drm_enc,struct dentry * root)2467 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root)
2468 {
2469 /* don't error check these */
2470 debugfs_create_file("status", 0600,
2471 root, drm_enc, &_dpu_encoder_status_fops);
2472 }
2473 #else
2474 #define dpu_encoder_debugfs_init NULL
2475 #endif
2476
dpu_encoder_virt_add_phys_encs(struct drm_device * dev,struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2477 static int dpu_encoder_virt_add_phys_encs(
2478 struct drm_device *dev,
2479 struct msm_display_info *disp_info,
2480 struct dpu_encoder_virt *dpu_enc,
2481 struct dpu_enc_phys_init_params *params)
2482 {
2483 struct dpu_encoder_phys *enc = NULL;
2484
2485 DPU_DEBUG_ENC(dpu_enc, "\n");
2486
2487 /*
2488 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2489 * in this function, check up-front.
2490 */
2491 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2492 ARRAY_SIZE(dpu_enc->phys_encs)) {
2493 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2494 dpu_enc->num_phys_encs);
2495 return -EINVAL;
2496 }
2497
2498
2499 if (disp_info->intf_type == INTF_WB) {
2500 enc = dpu_encoder_phys_wb_init(dev, params);
2501
2502 if (IS_ERR(enc)) {
2503 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2504 PTR_ERR(enc));
2505 return PTR_ERR(enc);
2506 }
2507
2508 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2509 ++dpu_enc->num_phys_encs;
2510 } else if (disp_info->is_cmd_mode) {
2511 enc = dpu_encoder_phys_cmd_init(dev, params);
2512
2513 if (IS_ERR(enc)) {
2514 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2515 PTR_ERR(enc));
2516 return PTR_ERR(enc);
2517 }
2518
2519 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2520 ++dpu_enc->num_phys_encs;
2521 } else {
2522 enc = dpu_encoder_phys_vid_init(dev, params);
2523
2524 if (IS_ERR(enc)) {
2525 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2526 PTR_ERR(enc));
2527 return PTR_ERR(enc);
2528 }
2529
2530 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2531 ++dpu_enc->num_phys_encs;
2532 }
2533
2534 if (params->split_role == ENC_ROLE_SLAVE)
2535 dpu_enc->cur_slave = enc;
2536 else
2537 dpu_enc->cur_master = enc;
2538
2539 return 0;
2540 }
2541
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2542 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2543 struct dpu_kms *dpu_kms,
2544 struct msm_display_info *disp_info)
2545 {
2546 int ret = 0;
2547 int i = 0;
2548 struct dpu_enc_phys_init_params phys_params;
2549
2550 if (!dpu_enc) {
2551 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2552 return -EINVAL;
2553 }
2554
2555 dpu_enc->cur_master = NULL;
2556
2557 memset(&phys_params, 0, sizeof(phys_params));
2558 phys_params.dpu_kms = dpu_kms;
2559 phys_params.parent = &dpu_enc->base;
2560 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2561
2562 WARN_ON(disp_info->num_of_h_tiles < 1);
2563
2564 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2565
2566 if (disp_info->intf_type != INTF_WB)
2567 dpu_enc->idle_pc_supported =
2568 dpu_kms->catalog->caps->has_idle_pc;
2569
2570 mutex_lock(&dpu_enc->enc_lock);
2571 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2572 /*
2573 * Left-most tile is at index 0, content is controller id
2574 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2575 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2576 */
2577 u32 controller_id = disp_info->h_tile_instance[i];
2578
2579 if (disp_info->num_of_h_tiles > 1) {
2580 if (i == 0)
2581 phys_params.split_role = ENC_ROLE_MASTER;
2582 else
2583 phys_params.split_role = ENC_ROLE_SLAVE;
2584 } else {
2585 phys_params.split_role = ENC_ROLE_SOLO;
2586 }
2587
2588 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2589 i, controller_id, phys_params.split_role);
2590
2591 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
2592 disp_info->intf_type,
2593 controller_id);
2594
2595 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
2596 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
2597
2598 if (!phys_params.hw_intf && !phys_params.hw_wb) {
2599 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2600 ret = -EINVAL;
2601 break;
2602 }
2603
2604 if (phys_params.hw_intf && phys_params.hw_wb) {
2605 DPU_ERROR_ENC(dpu_enc,
2606 "invalid phys both intf and wb block at idx: %d\n", i);
2607 ret = -EINVAL;
2608 break;
2609 }
2610
2611 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info,
2612 dpu_enc, &phys_params);
2613 if (ret) {
2614 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2615 break;
2616 }
2617 }
2618
2619 mutex_unlock(&dpu_enc->enc_lock);
2620
2621 return ret;
2622 }
2623
dpu_encoder_frame_done_timeout(struct timer_list * t)2624 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2625 {
2626 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2627 frame_done_timer);
2628 struct drm_encoder *drm_enc = &dpu_enc->base;
2629 u32 event;
2630
2631 if (!drm_enc->dev) {
2632 DPU_ERROR("invalid parameters\n");
2633 return;
2634 }
2635
2636 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) {
2637 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2638 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2639 return;
2640 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2641 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2642 return;
2643 }
2644
2645 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2646
2647 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1)
2648 msm_disp_snapshot_state(drm_enc->dev);
2649
2650 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2651 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2652 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
2653 }
2654
2655 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2656 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2657 .atomic_disable = dpu_encoder_virt_atomic_disable,
2658 .atomic_enable = dpu_encoder_virt_atomic_enable,
2659 .atomic_check = dpu_encoder_virt_atomic_check,
2660 };
2661
2662 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2663 .debugfs_init = dpu_encoder_debugfs_init,
2664 };
2665
2666 /**
2667 * dpu_encoder_init - initialize virtual encoder object
2668 * @dev: Pointer to drm device structure
2669 * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant
2670 * @disp_info: Pointer to display information structure
2671 * Returns: Pointer to newly created drm encoder
2672 */
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode,struct msm_display_info * disp_info)2673 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2674 int drm_enc_mode,
2675 struct msm_display_info *disp_info)
2676 {
2677 struct msm_drm_private *priv = dev->dev_private;
2678 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2679 struct dpu_encoder_virt *dpu_enc;
2680 int ret;
2681
2682 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base,
2683 &dpu_encoder_funcs, drm_enc_mode, NULL);
2684 if (IS_ERR(dpu_enc))
2685 return ERR_CAST(dpu_enc);
2686
2687 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2688
2689 spin_lock_init(&dpu_enc->enc_spinlock);
2690 dpu_enc->enabled = false;
2691 mutex_init(&dpu_enc->enc_lock);
2692 mutex_init(&dpu_enc->rc_lock);
2693
2694 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2695 if (ret) {
2696 DPU_ERROR("failed to setup encoder\n");
2697 return ERR_PTR(-ENOMEM);
2698 }
2699
2700 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2701 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
2702 timer_setup(&dpu_enc->frame_done_timer,
2703 dpu_encoder_frame_done_timeout, 0);
2704
2705 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2706 dpu_encoder_off_work);
2707 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2708
2709 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2710
2711 DPU_DEBUG_ENC(dpu_enc, "created\n");
2712
2713 return &dpu_enc->base;
2714 }
2715
2716 /**
2717 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state
2718 * @drm_enc: encoder pointer
2719 *
2720 * Wait for hardware to have flushed the current pending changes to hardware at
2721 * a vblank or CTL_START. Physical encoders will map this differently depending
2722 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START.
2723 *
2724 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2725 */
dpu_encoder_wait_for_commit_done(struct drm_encoder * drm_enc)2726 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
2727 {
2728 struct dpu_encoder_virt *dpu_enc = NULL;
2729 int i, ret = 0;
2730
2731 if (!drm_enc) {
2732 DPU_ERROR("invalid encoder\n");
2733 return -EINVAL;
2734 }
2735 dpu_enc = to_dpu_encoder_virt(drm_enc);
2736 DPU_DEBUG_ENC(dpu_enc, "\n");
2737
2738 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2739 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2740
2741 if (phys->ops.wait_for_commit_done) {
2742 DPU_ATRACE_BEGIN("wait_for_commit_done");
2743 ret = phys->ops.wait_for_commit_done(phys);
2744 DPU_ATRACE_END("wait_for_commit_done");
2745 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) {
2746 dpu_enc->commit_done_timedout = true;
2747 msm_disp_snapshot_state(drm_enc->dev);
2748 }
2749 if (ret)
2750 return ret;
2751 }
2752 }
2753
2754 return ret;
2755 }
2756
2757 /**
2758 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel
2759 * @drm_enc: encoder pointer
2760 *
2761 * Wait for the hardware to transfer all the pixels to the panel. Physical
2762 * encoders will map this differently depending on the type: vid mode -> vsync_irq,
2763 * cmd mode -> pp_done.
2764 *
2765 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2766 */
dpu_encoder_wait_for_tx_complete(struct drm_encoder * drm_enc)2767 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc)
2768 {
2769 struct dpu_encoder_virt *dpu_enc = NULL;
2770 int i, ret = 0;
2771
2772 if (!drm_enc) {
2773 DPU_ERROR("invalid encoder\n");
2774 return -EINVAL;
2775 }
2776 dpu_enc = to_dpu_encoder_virt(drm_enc);
2777 DPU_DEBUG_ENC(dpu_enc, "\n");
2778
2779 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2780 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2781
2782 if (phys->ops.wait_for_tx_complete) {
2783 DPU_ATRACE_BEGIN("wait_for_tx_complete");
2784 ret = phys->ops.wait_for_tx_complete(phys);
2785 DPU_ATRACE_END("wait_for_tx_complete");
2786 if (ret)
2787 return ret;
2788 }
2789 }
2790
2791 return ret;
2792 }
2793
2794 /**
2795 * dpu_encoder_get_intf_mode - get interface mode of the given encoder
2796 * @encoder: Pointer to drm encoder object
2797 */
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2798 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2799 {
2800 struct dpu_encoder_virt *dpu_enc = NULL;
2801
2802 if (!encoder) {
2803 DPU_ERROR("invalid encoder\n");
2804 return INTF_MODE_NONE;
2805 }
2806 dpu_enc = to_dpu_encoder_virt(encoder);
2807
2808 if (dpu_enc->cur_master)
2809 return dpu_enc->cur_master->intf_mode;
2810
2811 if (dpu_enc->num_phys_encs)
2812 return dpu_enc->phys_encs[0]->intf_mode;
2813
2814 return INTF_MODE_NONE;
2815 }
2816
2817 /**
2818 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
2819 * This helper function is used by physical encoder to get DSC blocks mask
2820 * used for this encoder.
2821 * @phys_enc: Pointer to physical encoder structure
2822 */
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2823 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2824 {
2825 struct drm_encoder *encoder = phys_enc->parent;
2826 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2827
2828 return dpu_enc->dsc_mask;
2829 }
2830
dpu_encoder_phys_init(struct dpu_encoder_phys * phys_enc,struct dpu_enc_phys_init_params * p)2831 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
2832 struct dpu_enc_phys_init_params *p)
2833 {
2834 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
2835 phys_enc->hw_intf = p->hw_intf;
2836 phys_enc->hw_wb = p->hw_wb;
2837 phys_enc->parent = p->parent;
2838 phys_enc->dpu_kms = p->dpu_kms;
2839 phys_enc->split_role = p->split_role;
2840 phys_enc->enc_spinlock = p->enc_spinlock;
2841 phys_enc->enable_state = DPU_ENC_DISABLED;
2842
2843 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
2844 atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
2845
2846 atomic_set(&phys_enc->vsync_cnt, 0);
2847 atomic_set(&phys_enc->underrun_cnt, 0);
2848
2849 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
2850 }
2851