1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6
7 #include <linux/debugfs.h>
8 #include <linux/errno.h>
9 #include <linux/mutex.h>
10 #include <linux/pm_opp.h>
11 #include <linux/sort.h>
12 #include <linux/clk.h>
13 #include <linux/bitmap.h>
14
15 #include "dpu_kms.h"
16 #include "dpu_trace.h"
17 #include "dpu_crtc.h"
18 #include "dpu_core_perf.h"
19
20 /**
21 * enum dpu_perf_mode - performance tuning mode
22 * @DPU_PERF_MODE_NORMAL: performance controlled by user mode client
23 * @DPU_PERF_MODE_MINIMUM: performance bounded by minimum setting
24 * @DPU_PERF_MODE_FIXED: performance bounded by fixed setting
25 * @DPU_PERF_MODE_MAX: maximum value, used for error checking
26 */
27 enum dpu_perf_mode {
28 DPU_PERF_MODE_NORMAL,
29 DPU_PERF_MODE_MINIMUM,
30 DPU_PERF_MODE_FIXED,
31 DPU_PERF_MODE_MAX
32 };
33
34 /**
35 * _dpu_core_perf_calc_bw() - to calculate BW per crtc
36 * @perf_cfg: performance configuration
37 * @crtc: pointer to a crtc
38 * Return: returns aggregated BW for all planes in crtc.
39 */
_dpu_core_perf_calc_bw(const struct dpu_perf_cfg * perf_cfg,struct drm_crtc * crtc)40 static u64 _dpu_core_perf_calc_bw(const struct dpu_perf_cfg *perf_cfg,
41 struct drm_crtc *crtc)
42 {
43 struct drm_plane *plane;
44 struct dpu_plane_state *pstate;
45 u64 crtc_plane_bw = 0;
46 u32 bw_factor;
47
48 drm_atomic_crtc_for_each_plane(plane, crtc) {
49 pstate = to_dpu_plane_state(plane->state);
50 if (!pstate)
51 continue;
52
53 crtc_plane_bw += pstate->plane_fetch_bw;
54 }
55
56 bw_factor = perf_cfg->bw_inefficiency_factor;
57 if (bw_factor) {
58 crtc_plane_bw *= bw_factor;
59 do_div(crtc_plane_bw, 100);
60 }
61
62 return crtc_plane_bw;
63 }
64
65 /**
66 * _dpu_core_perf_calc_clk() - to calculate clock per crtc
67 * @perf_cfg: performance configuration
68 * @crtc: pointer to a crtc
69 * @state: pointer to a crtc state
70 * Return: returns max clk for all planes in crtc.
71 */
_dpu_core_perf_calc_clk(const struct dpu_perf_cfg * perf_cfg,struct drm_crtc * crtc,struct drm_crtc_state * state)72 static u64 _dpu_core_perf_calc_clk(const struct dpu_perf_cfg *perf_cfg,
73 struct drm_crtc *crtc, struct drm_crtc_state *state)
74 {
75 struct drm_plane *plane;
76 struct dpu_plane_state *pstate;
77 struct drm_display_mode *mode;
78 u64 crtc_clk;
79 u32 clk_factor;
80
81 mode = &state->adjusted_mode;
82
83 crtc_clk = (u64)mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
84
85 drm_atomic_crtc_for_each_plane(plane, crtc) {
86 pstate = to_dpu_plane_state(plane->state);
87 if (!pstate)
88 continue;
89
90 crtc_clk = max(pstate->plane_clk, crtc_clk);
91 }
92
93 clk_factor = perf_cfg->clk_inefficiency_factor;
94 if (clk_factor) {
95 crtc_clk *= clk_factor;
96 do_div(crtc_clk, 100);
97 }
98
99 return crtc_clk;
100 }
101
_dpu_crtc_get_kms(struct drm_crtc * crtc)102 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
103 {
104 struct msm_drm_private *priv;
105 priv = crtc->dev->dev_private;
106 return to_dpu_kms(priv->kms);
107 }
108
_dpu_core_perf_calc_crtc(const struct dpu_core_perf * core_perf,struct drm_crtc * crtc,struct drm_crtc_state * state,struct dpu_core_perf_params * perf)109 static void _dpu_core_perf_calc_crtc(const struct dpu_core_perf *core_perf,
110 struct drm_crtc *crtc,
111 struct drm_crtc_state *state,
112 struct dpu_core_perf_params *perf)
113 {
114 const struct dpu_perf_cfg *perf_cfg = core_perf->perf_cfg;
115
116 if (!perf_cfg || !crtc || !state || !perf) {
117 DPU_ERROR("invalid parameters\n");
118 return;
119 }
120
121 memset(perf, 0, sizeof(struct dpu_core_perf_params));
122
123 if (core_perf->perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
124 perf->bw_ctl = 0;
125 perf->max_per_pipe_ib = 0;
126 perf->core_clk_rate = 0;
127 } else if (core_perf->perf_tune.mode == DPU_PERF_MODE_FIXED) {
128 perf->bw_ctl = core_perf->fix_core_ab_vote;
129 perf->max_per_pipe_ib = core_perf->fix_core_ib_vote;
130 perf->core_clk_rate = core_perf->fix_core_clk_rate;
131 } else {
132 perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, crtc);
133 perf->max_per_pipe_ib = perf_cfg->min_dram_ib;
134 perf->core_clk_rate = _dpu_core_perf_calc_clk(perf_cfg, crtc, state);
135 }
136
137 DRM_DEBUG_ATOMIC(
138 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
139 crtc->base.id, perf->core_clk_rate,
140 perf->max_per_pipe_ib, perf->bw_ctl);
141 }
142
143 /**
144 * dpu_core_perf_crtc_check - validate performance of the given crtc state
145 * @crtc: Pointer to crtc
146 * @state: Pointer to new crtc state
147 * return: zero if success, or error code otherwise
148 */
dpu_core_perf_crtc_check(struct drm_crtc * crtc,struct drm_crtc_state * state)149 int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
150 struct drm_crtc_state *state)
151 {
152 u32 bw, threshold;
153 u64 bw_sum_of_intfs = 0;
154 enum dpu_crtc_client_type curr_client_type;
155 struct dpu_crtc_state *dpu_cstate;
156 struct drm_crtc *tmp_crtc;
157 struct dpu_kms *kms;
158
159 if (!crtc || !state) {
160 DPU_ERROR("invalid crtc\n");
161 return -EINVAL;
162 }
163
164 kms = _dpu_crtc_get_kms(crtc);
165
166 /* we only need bandwidth check on real-time clients (interfaces) */
167 if (dpu_crtc_get_client_type(crtc) == NRT_CLIENT)
168 return 0;
169
170 dpu_cstate = to_dpu_crtc_state(state);
171
172 /* obtain new values */
173 _dpu_core_perf_calc_crtc(&kms->perf, crtc, state, &dpu_cstate->new_perf);
174
175 bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
176 curr_client_type = dpu_crtc_get_client_type(crtc);
177
178 drm_for_each_crtc(tmp_crtc, crtc->dev) {
179 if (tmp_crtc->enabled &&
180 dpu_crtc_get_client_type(tmp_crtc) == curr_client_type &&
181 tmp_crtc != crtc) {
182 struct dpu_crtc_state *tmp_cstate =
183 to_dpu_crtc_state(tmp_crtc->state);
184
185 DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n",
186 tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
187 tmp_cstate->bw_control);
188
189 bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
190 }
191
192 /* convert bandwidth to kb */
193 bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
194 DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
195
196 threshold = kms->perf.perf_cfg->max_bw_high;
197
198 DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
199
200 if (!threshold) {
201 DPU_ERROR("no bandwidth limits specified\n");
202 return -E2BIG;
203 } else if (bw > threshold) {
204 DPU_ERROR("exceeds bandwidth: %ukb > %ukb\n", bw,
205 threshold);
206 return -E2BIG;
207 }
208 }
209
210 return 0;
211 }
212
_dpu_core_perf_crtc_update_bus(struct dpu_kms * kms,struct drm_crtc * crtc)213 static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
214 struct drm_crtc *crtc)
215 {
216 struct dpu_core_perf_params perf = { 0 };
217 enum dpu_crtc_client_type curr_client_type
218 = dpu_crtc_get_client_type(crtc);
219 struct drm_crtc *tmp_crtc;
220 struct dpu_crtc_state *dpu_cstate;
221 int i, ret = 0;
222 u64 avg_bw;
223
224 if (!kms->num_paths)
225 return 0;
226
227 drm_for_each_crtc(tmp_crtc, crtc->dev) {
228 if (tmp_crtc->enabled &&
229 curr_client_type ==
230 dpu_crtc_get_client_type(tmp_crtc)) {
231 dpu_cstate = to_dpu_crtc_state(tmp_crtc->state);
232
233 perf.max_per_pipe_ib = max(perf.max_per_pipe_ib,
234 dpu_cstate->new_perf.max_per_pipe_ib);
235
236 perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
237
238 DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n",
239 tmp_crtc->base.id,
240 dpu_cstate->new_perf.bw_ctl, kms->num_paths);
241 }
242 }
243
244 avg_bw = perf.bw_ctl;
245 do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/
246
247 for (i = 0; i < kms->num_paths; i++)
248 icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib);
249
250 return ret;
251 }
252
253 /**
254 * dpu_core_perf_crtc_release_bw() - request zero bandwidth
255 * @crtc: pointer to a crtc
256 *
257 * Function checks a state variable for the crtc, if all pending commit
258 * requests are done, meaning no more bandwidth is needed, release
259 * bandwidth request.
260 */
dpu_core_perf_crtc_release_bw(struct drm_crtc * crtc)261 void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
262 {
263 struct dpu_crtc *dpu_crtc;
264 struct dpu_kms *kms;
265
266 if (!crtc) {
267 DPU_ERROR("invalid crtc\n");
268 return;
269 }
270
271 kms = _dpu_crtc_get_kms(crtc);
272 dpu_crtc = to_dpu_crtc(crtc);
273
274 if (atomic_dec_return(&kms->bandwidth_ref) > 0)
275 return;
276
277 /* Release the bandwidth */
278 if (kms->perf.enable_bw_release) {
279 trace_dpu_cmd_release_bw(crtc->base.id);
280 DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id);
281 dpu_crtc->cur_perf.bw_ctl = 0;
282 _dpu_core_perf_crtc_update_bus(kms, crtc);
283 }
284 }
285
_dpu_core_perf_get_core_clk_rate(struct dpu_kms * kms)286 static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
287 {
288 u64 clk_rate;
289 struct drm_crtc *crtc;
290 struct dpu_crtc_state *dpu_cstate;
291
292 if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
293 return kms->perf.fix_core_clk_rate;
294
295 if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM)
296 return kms->perf.max_core_clk_rate;
297
298 clk_rate = 0;
299 drm_for_each_crtc(crtc, kms->dev) {
300 if (crtc->enabled) {
301 dpu_cstate = to_dpu_crtc_state(crtc->state);
302 clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
303 clk_rate);
304 }
305 }
306
307 return clk_rate;
308 }
309
310 /**
311 * dpu_core_perf_crtc_update - update performance of the given crtc
312 * @crtc: Pointer to crtc
313 * @params_changed: true if crtc parameters are modified
314 * return: zero if success, or error code otherwise
315 */
dpu_core_perf_crtc_update(struct drm_crtc * crtc,int params_changed)316 int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
317 int params_changed)
318 {
319 struct dpu_core_perf_params *new, *old;
320 bool update_bus = false, update_clk = false;
321 u64 clk_rate = 0;
322 struct dpu_crtc *dpu_crtc;
323 struct dpu_crtc_state *dpu_cstate;
324 struct dpu_kms *kms;
325 int ret;
326
327 if (!crtc) {
328 DPU_ERROR("invalid crtc\n");
329 return -EINVAL;
330 }
331
332 kms = _dpu_crtc_get_kms(crtc);
333
334 dpu_crtc = to_dpu_crtc(crtc);
335 dpu_cstate = to_dpu_crtc_state(crtc->state);
336
337 DRM_DEBUG_ATOMIC("crtc:%d enabled:%d core_clk:%llu\n",
338 crtc->base.id, crtc->enabled, kms->perf.core_clk_rate);
339
340 old = &dpu_crtc->cur_perf;
341 new = &dpu_cstate->new_perf;
342
343 if (crtc->enabled) {
344 /*
345 * cases for bus bandwidth update.
346 * 1. new bandwidth vote - "ab or ib vote" is higher
347 * than current vote for update request.
348 * 2. new bandwidth vote - "ab or ib vote" is lower
349 * than current vote at end of commit or stop.
350 */
351 if ((params_changed && ((new->bw_ctl > old->bw_ctl) ||
352 (new->max_per_pipe_ib > old->max_per_pipe_ib))) ||
353 (!params_changed && ((new->bw_ctl < old->bw_ctl) ||
354 (new->max_per_pipe_ib < old->max_per_pipe_ib)))) {
355 DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
356 crtc->base.id, params_changed,
357 new->bw_ctl, old->bw_ctl);
358 old->bw_ctl = new->bw_ctl;
359 old->max_per_pipe_ib = new->max_per_pipe_ib;
360 update_bus = true;
361 }
362
363 if ((params_changed && new->core_clk_rate > old->core_clk_rate) ||
364 (!params_changed && new->core_clk_rate < old->core_clk_rate)) {
365 old->core_clk_rate = new->core_clk_rate;
366 update_clk = true;
367 }
368 } else {
369 DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id);
370 memset(old, 0, sizeof(*old));
371 update_bus = true;
372 update_clk = true;
373 }
374
375 trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl,
376 new->core_clk_rate, !crtc->enabled, update_bus, update_clk);
377
378 if (update_bus) {
379 ret = _dpu_core_perf_crtc_update_bus(kms, crtc);
380 if (ret) {
381 DPU_ERROR("crtc-%d: failed to update bus bw vote\n",
382 crtc->base.id);
383 return ret;
384 }
385 }
386
387 /*
388 * Update the clock after bandwidth vote to ensure
389 * bandwidth is available before clock rate is increased.
390 */
391 if (update_clk) {
392 clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
393
394 DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
395
396 trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate);
397
398 clk_rate = min(clk_rate, kms->perf.max_core_clk_rate);
399 ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate);
400 if (ret) {
401 DPU_ERROR("failed to set core clock rate %llu\n", clk_rate);
402 return ret;
403 }
404
405 kms->perf.core_clk_rate = clk_rate;
406 DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate);
407 }
408 return 0;
409 }
410
411 #ifdef CONFIG_DEBUG_FS
412
_dpu_core_perf_mode_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)413 static ssize_t _dpu_core_perf_mode_write(struct file *file,
414 const char __user *user_buf, size_t count, loff_t *ppos)
415 {
416 struct dpu_core_perf *perf = file->private_data;
417 u32 perf_mode = 0;
418 int ret;
419
420 ret = kstrtouint_from_user(user_buf, count, 0, &perf_mode);
421 if (ret)
422 return ret;
423
424 if (perf_mode >= DPU_PERF_MODE_MAX)
425 return -EINVAL;
426
427 if (perf_mode == DPU_PERF_MODE_FIXED) {
428 DRM_INFO("fix performance mode\n");
429 } else if (perf_mode == DPU_PERF_MODE_MINIMUM) {
430 /* run the driver with max clk and BW vote */
431 DRM_INFO("minimum performance mode\n");
432 } else if (perf_mode == DPU_PERF_MODE_NORMAL) {
433 /* reset the perf tune params to 0 */
434 DRM_INFO("normal performance mode\n");
435 }
436 perf->perf_tune.mode = perf_mode;
437
438 return count;
439 }
440
_dpu_core_perf_mode_read(struct file * file,char __user * buff,size_t count,loff_t * ppos)441 static ssize_t _dpu_core_perf_mode_read(struct file *file,
442 char __user *buff, size_t count, loff_t *ppos)
443 {
444 struct dpu_core_perf *perf = file->private_data;
445 int len;
446 char buf[128];
447
448 len = scnprintf(buf, sizeof(buf),
449 "mode %d\n",
450 perf->perf_tune.mode);
451
452 return simple_read_from_buffer(buff, count, ppos, buf, len);
453 }
454
455 static const struct file_operations dpu_core_perf_mode_fops = {
456 .open = simple_open,
457 .read = _dpu_core_perf_mode_read,
458 .write = _dpu_core_perf_mode_write,
459 };
460
461 /**
462 * dpu_core_perf_debugfs_init - initialize debugfs for core performance context
463 * @dpu_kms: Pointer to the dpu_kms struct
464 * @parent: Pointer to parent debugfs
465 */
dpu_core_perf_debugfs_init(struct dpu_kms * dpu_kms,struct dentry * parent)466 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
467 {
468 struct dpu_core_perf *perf = &dpu_kms->perf;
469 struct dentry *entry;
470
471 entry = debugfs_create_dir("core_perf", parent);
472
473 debugfs_create_u64("max_core_clk_rate", 0600, entry,
474 &perf->max_core_clk_rate);
475 debugfs_create_u64("core_clk_rate", 0600, entry,
476 &perf->core_clk_rate);
477 debugfs_create_u32("enable_bw_release", 0600, entry,
478 (u32 *)&perf->enable_bw_release);
479 debugfs_create_u32("threshold_low", 0400, entry,
480 (u32 *)&perf->perf_cfg->max_bw_low);
481 debugfs_create_u32("threshold_high", 0400, entry,
482 (u32 *)&perf->perf_cfg->max_bw_high);
483 debugfs_create_u32("min_core_ib", 0400, entry,
484 (u32 *)&perf->perf_cfg->min_core_ib);
485 debugfs_create_u32("min_llcc_ib", 0400, entry,
486 (u32 *)&perf->perf_cfg->min_llcc_ib);
487 debugfs_create_u32("min_dram_ib", 0400, entry,
488 (u32 *)&perf->perf_cfg->min_dram_ib);
489 debugfs_create_file("perf_mode", 0600, entry,
490 (u32 *)perf, &dpu_core_perf_mode_fops);
491 debugfs_create_u64("fix_core_clk_rate", 0600, entry,
492 &perf->fix_core_clk_rate);
493 debugfs_create_u64("fix_core_ib_vote", 0600, entry,
494 &perf->fix_core_ib_vote);
495 debugfs_create_u64("fix_core_ab_vote", 0600, entry,
496 &perf->fix_core_ab_vote);
497
498 return 0;
499 }
500 #endif
501
502 /**
503 * dpu_core_perf_init - initialize the given core performance context
504 * @perf: Pointer to core performance context
505 * @perf_cfg: Pointer to platform performance configuration
506 * @max_core_clk_rate: Maximum core clock rate
507 */
dpu_core_perf_init(struct dpu_core_perf * perf,const struct dpu_perf_cfg * perf_cfg,unsigned long max_core_clk_rate)508 int dpu_core_perf_init(struct dpu_core_perf *perf,
509 const struct dpu_perf_cfg *perf_cfg,
510 unsigned long max_core_clk_rate)
511 {
512 perf->perf_cfg = perf_cfg;
513 perf->max_core_clk_rate = max_core_clk_rate;
514
515 return 0;
516 }
517