1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements all generic dp link training helper functions and top
28 * level generic training sequence. All variations of dp link training sequence
29 * should be called inside the top level training functions in this file to
30 * ensure the integrity of our overall training procedure across different types
31 * of link encoding and back end hardware.
32 */
33 #include "link_dp_training.h"
34 #include "link_dp_training_8b_10b.h"
35 #include "link_dp_training_128b_132b.h"
36 #include "link_dp_training_auxless.h"
37 #include "link_dp_training_dpia.h"
38 #include "link_dp_training_fixed_vs_pe_retimer.h"
39 #include "link_dpcd.h"
40 #include "link/accessories/link_dp_trace.h"
41 #include "link_dp_phy.h"
42 #include "link_dp_capability.h"
43 #include "link_edp_panel_control.h"
44 #include "link/link_detection.h"
45 #include "link/link_validation.h"
46 #include "atomfirmware.h"
47 #include "link_enc_cfg.h"
48 #include "resource.h"
49 #include "dm_helpers.h"
50
51 #define DC_LOGGER \
52 link->ctx->logger
53
54 #define POST_LT_ADJ_REQ_LIMIT 6
55 #define POST_LT_ADJ_REQ_TIMEOUT 200
56 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
57
dp_log_training_result(struct dc_link * link,const struct link_training_settings * lt_settings,enum link_training_result status)58 void dp_log_training_result(
59 struct dc_link *link,
60 const struct link_training_settings *lt_settings,
61 enum link_training_result status)
62 {
63 char *link_rate = "Unknown";
64 char *lt_result = "Unknown";
65 char *lt_spread = "Disabled";
66
67 switch (lt_settings->link_settings.link_rate) {
68 case LINK_RATE_LOW:
69 link_rate = "RBR";
70 break;
71 case LINK_RATE_RATE_2:
72 link_rate = "R2";
73 break;
74 case LINK_RATE_RATE_3:
75 link_rate = "R3";
76 break;
77 case LINK_RATE_HIGH:
78 link_rate = "HBR";
79 break;
80 case LINK_RATE_RBR2:
81 link_rate = "RBR2";
82 break;
83 case LINK_RATE_RATE_6:
84 link_rate = "R6";
85 break;
86 case LINK_RATE_HIGH2:
87 link_rate = "HBR2";
88 break;
89 case LINK_RATE_RATE_8:
90 link_rate = "R8";
91 break;
92 case LINK_RATE_HIGH3:
93 link_rate = "HBR3";
94 break;
95 case LINK_RATE_UHBR10:
96 link_rate = "UHBR10";
97 break;
98 case LINK_RATE_UHBR13_5:
99 link_rate = "UHBR13.5";
100 break;
101 case LINK_RATE_UHBR20:
102 link_rate = "UHBR20";
103 break;
104 default:
105 break;
106 }
107
108 switch (status) {
109 case LINK_TRAINING_SUCCESS:
110 lt_result = "pass";
111 break;
112 case LINK_TRAINING_CR_FAIL_LANE0:
113 lt_result = "CR failed lane0";
114 break;
115 case LINK_TRAINING_CR_FAIL_LANE1:
116 lt_result = "CR failed lane1";
117 break;
118 case LINK_TRAINING_CR_FAIL_LANE23:
119 lt_result = "CR failed lane23";
120 break;
121 case LINK_TRAINING_EQ_FAIL_CR:
122 lt_result = "CR failed in EQ";
123 break;
124 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
125 lt_result = "CR failed in EQ partially";
126 break;
127 case LINK_TRAINING_EQ_FAIL_EQ:
128 lt_result = "EQ failed";
129 break;
130 case LINK_TRAINING_LQA_FAIL:
131 lt_result = "LQA failed";
132 break;
133 case LINK_TRAINING_LINK_LOSS:
134 lt_result = "Link loss";
135 break;
136 case DP_128b_132b_LT_FAILED:
137 lt_result = "LT_FAILED received";
138 break;
139 case DP_128b_132b_MAX_LOOP_COUNT_REACHED:
140 lt_result = "max loop count reached";
141 break;
142 case DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT:
143 lt_result = "channel EQ timeout";
144 break;
145 case DP_128b_132b_CDS_DONE_TIMEOUT:
146 lt_result = "CDS timeout";
147 break;
148 default:
149 break;
150 }
151
152 switch (lt_settings->link_settings.link_spread) {
153 case LINK_SPREAD_DISABLED:
154 lt_spread = "Disabled";
155 break;
156 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
157 lt_spread = "0.5% 30KHz";
158 break;
159 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
160 lt_spread = "0.5% 33KHz";
161 break;
162 default:
163 break;
164 }
165
166 /* Connectivity log: link training */
167
168 /* TODO - DP2.0 Log: add connectivity log for FFE PRESET */
169
170 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
171 link_rate,
172 lt_settings->link_settings.lane_count,
173 lt_result,
174 lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
175 lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
176 lt_spread);
177 }
178
dp_initialize_scrambling_data_symbols(struct dc_link * link,enum dc_dp_training_pattern pattern)179 uint8_t dp_initialize_scrambling_data_symbols(
180 struct dc_link *link,
181 enum dc_dp_training_pattern pattern)
182 {
183 uint8_t disable_scrabled_data_symbols = 0;
184
185 switch (pattern) {
186 case DP_TRAINING_PATTERN_SEQUENCE_1:
187 case DP_TRAINING_PATTERN_SEQUENCE_2:
188 case DP_TRAINING_PATTERN_SEQUENCE_3:
189 disable_scrabled_data_symbols = 1;
190 break;
191 case DP_TRAINING_PATTERN_SEQUENCE_4:
192 case DP_128b_132b_TPS1:
193 case DP_128b_132b_TPS2:
194 disable_scrabled_data_symbols = 0;
195 break;
196 default:
197 ASSERT(0);
198 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
199 __func__, pattern);
200 break;
201 }
202 return disable_scrabled_data_symbols;
203 }
204
205 enum dpcd_training_patterns
dp_training_pattern_to_dpcd_training_pattern(struct dc_link * link,enum dc_dp_training_pattern pattern)206 dp_training_pattern_to_dpcd_training_pattern(
207 struct dc_link *link,
208 enum dc_dp_training_pattern pattern)
209 {
210 enum dpcd_training_patterns dpcd_tr_pattern =
211 DPCD_TRAINING_PATTERN_VIDEOIDLE;
212
213 switch (pattern) {
214 case DP_TRAINING_PATTERN_SEQUENCE_1:
215 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS1\n", __func__);
216 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
217 break;
218 case DP_TRAINING_PATTERN_SEQUENCE_2:
219 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS2\n", __func__);
220 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
221 break;
222 case DP_TRAINING_PATTERN_SEQUENCE_3:
223 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS3\n", __func__);
224 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
225 break;
226 case DP_TRAINING_PATTERN_SEQUENCE_4:
227 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS4\n", __func__);
228 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
229 break;
230 case DP_128b_132b_TPS1:
231 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS1\n", __func__);
232 dpcd_tr_pattern = DPCD_128b_132b_TPS1;
233 break;
234 case DP_128b_132b_TPS2:
235 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2\n", __func__);
236 dpcd_tr_pattern = DPCD_128b_132b_TPS2;
237 break;
238 case DP_128b_132b_TPS2_CDS:
239 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2 CDS\n",
240 __func__);
241 dpcd_tr_pattern = DPCD_128b_132b_TPS2_CDS;
242 break;
243 case DP_TRAINING_PATTERN_VIDEOIDLE:
244 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern videoidle\n", __func__);
245 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
246 break;
247 default:
248 ASSERT(0);
249 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
250 __func__, pattern);
251 break;
252 }
253
254 return dpcd_tr_pattern;
255 }
256
dp_get_nibble_at_index(const uint8_t * buf,uint32_t index)257 uint8_t dp_get_nibble_at_index(const uint8_t *buf,
258 uint32_t index)
259 {
260 uint8_t nibble;
261 nibble = buf[index / 2];
262
263 if (index % 2)
264 nibble >>= 4;
265 else
266 nibble &= 0x0F;
267
268 return nibble;
269 }
270
dp_wait_for_training_aux_rd_interval(struct dc_link * link,uint32_t wait_in_micro_secs)271 void dp_wait_for_training_aux_rd_interval(
272 struct dc_link *link,
273 uint32_t wait_in_micro_secs)
274 {
275 usleep_range_state(wait_in_micro_secs, wait_in_micro_secs, TASK_UNINTERRUPTIBLE);
276
277 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
278 __func__,
279 wait_in_micro_secs);
280 }
281
282 /* maximum pre emphasis level allowed for each voltage swing level*/
283 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
284 PRE_EMPHASIS_LEVEL3,
285 PRE_EMPHASIS_LEVEL2,
286 PRE_EMPHASIS_LEVEL1,
287 PRE_EMPHASIS_DISABLED };
288
get_max_pre_emphasis_for_voltage_swing(enum dc_voltage_swing voltage)289 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
290 enum dc_voltage_swing voltage)
291 {
292 enum dc_pre_emphasis pre_emphasis;
293 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
294
295 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
296 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
297
298 return pre_emphasis;
299
300 }
301
maximize_lane_settings(const struct link_training_settings * lt_settings,struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])302 static void maximize_lane_settings(const struct link_training_settings *lt_settings,
303 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
304 {
305 uint32_t lane;
306 struct dc_lane_settings max_requested;
307
308 max_requested.VOLTAGE_SWING = lane_settings[0].VOLTAGE_SWING;
309 max_requested.PRE_EMPHASIS = lane_settings[0].PRE_EMPHASIS;
310 max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET;
311
312 /* Determine what the maximum of the requested settings are*/
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) {
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING)
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING;
316
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS)
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS;
319 if (lane_settings[lane].FFE_PRESET.settings.level >
320 max_requested.FFE_PRESET.settings.level)
321 max_requested.FFE_PRESET.settings.level =
322 lane_settings[lane].FFE_PRESET.settings.level;
323 }
324
325 /* make sure the requested settings are
326 * not higher than maximum settings*/
327 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
328 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
329
330 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
331 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
332
333 /* Note, we are not checking
334 * if max_requested.FFE_PRESET.settings.level > DP_FFE_PRESET_MAX_LEVEL,
335 * since FFE_PRESET.settings.level is 4 bits and DP_FFE_PRESET_MAX_LEVEL equals 15,
336 * so FFE_PRESET.settings.level will never be greater than 15.
337 */
338
339 /* make sure the pre-emphasis matches the voltage swing*/
340 if (max_requested.PRE_EMPHASIS >
341 get_max_pre_emphasis_for_voltage_swing(
342 max_requested.VOLTAGE_SWING))
343 max_requested.PRE_EMPHASIS =
344 get_max_pre_emphasis_for_voltage_swing(
345 max_requested.VOLTAGE_SWING);
346
347 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
348 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING;
349 lane_settings[lane].PRE_EMPHASIS = max_requested.PRE_EMPHASIS;
350 lane_settings[lane].FFE_PRESET = max_requested.FFE_PRESET;
351 }
352 }
353
dp_hw_to_dpcd_lane_settings(const struct link_training_settings * lt_settings,const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])354 void dp_hw_to_dpcd_lane_settings(
355 const struct link_training_settings *lt_settings,
356 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
357 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
358 {
359 uint8_t lane = 0;
360
361 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
362 if (link_dp_get_encoding_format(<_settings->link_settings) ==
363 DP_8b_10b_ENCODING) {
364 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET =
365 (uint8_t)(hw_lane_settings[lane].VOLTAGE_SWING);
366 dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET =
367 (uint8_t)(hw_lane_settings[lane].PRE_EMPHASIS);
368 dpcd_lane_settings[lane].bits.MAX_SWING_REACHED =
369 (hw_lane_settings[lane].VOLTAGE_SWING ==
370 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
371 dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED =
372 (hw_lane_settings[lane].PRE_EMPHASIS ==
373 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
374 } else if (link_dp_get_encoding_format(<_settings->link_settings) ==
375 DP_128b_132b_ENCODING) {
376 dpcd_lane_settings[lane].tx_ffe.PRESET_VALUE =
377 hw_lane_settings[lane].FFE_PRESET.settings.level;
378 }
379 }
380 }
381
get_dpcd_link_rate(const struct dc_link_settings * link_settings)382 uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)
383 {
384 uint8_t link_rate = 0;
385 enum dp_link_encoding encoding = link_dp_get_encoding_format(link_settings);
386
387 if (encoding == DP_128b_132b_ENCODING)
388 switch (link_settings->link_rate) {
389 case LINK_RATE_UHBR10:
390 link_rate = 0x1;
391 break;
392 case LINK_RATE_UHBR20:
393 link_rate = 0x2;
394 break;
395 case LINK_RATE_UHBR13_5:
396 link_rate = 0x4;
397 break;
398 default:
399 link_rate = 0;
400 break;
401 }
402 else if (encoding == DP_8b_10b_ENCODING)
403 link_rate = (uint8_t) link_settings->link_rate;
404 else
405 link_rate = 0;
406
407 return link_rate;
408 }
409
410 /* Only used for channel equalization */
dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)411 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
412 {
413 unsigned int aux_rd_interval_us = 400;
414
415 switch (dpcd_aux_read_interval) {
416 case 0x01:
417 aux_rd_interval_us = 4000;
418 break;
419 case 0x02:
420 aux_rd_interval_us = 8000;
421 break;
422 case 0x03:
423 aux_rd_interval_us = 12000;
424 break;
425 case 0x04:
426 aux_rd_interval_us = 16000;
427 break;
428 case 0x05:
429 aux_rd_interval_us = 32000;
430 break;
431 case 0x06:
432 aux_rd_interval_us = 64000;
433 break;
434 default:
435 break;
436 }
437
438 return aux_rd_interval_us;
439 }
440
dp_get_cr_failure(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)441 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
442 union lane_status *dpcd_lane_status)
443 {
444 enum link_training_result result = LINK_TRAINING_SUCCESS;
445
446 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
447 result = LINK_TRAINING_CR_FAIL_LANE0;
448 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
449 result = LINK_TRAINING_CR_FAIL_LANE1;
450 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
451 result = LINK_TRAINING_CR_FAIL_LANE23;
452 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
453 result = LINK_TRAINING_CR_FAIL_LANE23;
454 return result;
455 }
456
is_repeater(const struct link_training_settings * lt_settings,uint32_t offset)457 bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset)
458 {
459 return (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
460 }
461
dp_is_max_vs_reached(const struct link_training_settings * lt_settings)462 bool dp_is_max_vs_reached(
463 const struct link_training_settings *lt_settings)
464 {
465 uint32_t lane;
466 for (lane = 0; lane <
467 (uint32_t)(lt_settings->link_settings.lane_count);
468 lane++) {
469 if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET
470 == VOLTAGE_SWING_MAX_LEVEL)
471 return true;
472 }
473 return false;
474
475 }
476
dp_is_cr_done(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)477 bool dp_is_cr_done(enum dc_lane_count ln_count,
478 union lane_status *dpcd_lane_status)
479 {
480 bool done = true;
481 uint32_t lane;
482 /*LANEx_CR_DONE bits All 1's?*/
483 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
484 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
485 done = false;
486 }
487 return done;
488
489 }
490
dp_is_ch_eq_done(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)491 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
492 union lane_status *dpcd_lane_status)
493 {
494 bool done = true;
495 uint32_t lane;
496 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
497 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
498 done = false;
499 return done;
500 }
501
dp_is_symbol_locked(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)502 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
503 union lane_status *dpcd_lane_status)
504 {
505 bool locked = true;
506 uint32_t lane;
507 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
508 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
509 locked = false;
510 return locked;
511 }
512
dp_is_interlane_aligned(union lane_align_status_updated align_status)513 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
514 {
515 return align_status.bits.INTERLANE_ALIGN_DONE == 1;
516 }
517
dp_check_interlane_aligned(union lane_align_status_updated align_status,struct dc_link * link,uint8_t retries)518 bool dp_check_interlane_aligned(union lane_align_status_updated align_status,
519 struct dc_link *link,
520 uint8_t retries)
521 {
522 /* Take into consideration corner case for DP 1.4a LL Compliance CTS as USB4
523 * has to share encoders unlike DP and USBC
524 */
525 return (dp_is_interlane_aligned(align_status) ||
526 (link->skip_fallback_on_link_loss && retries));
527 }
528
dp_get_eq_aux_rd_interval(const struct dc_link * link,const struct link_training_settings * lt_settings,uint32_t offset,uint8_t retries)529 uint32_t dp_get_eq_aux_rd_interval(
530 const struct dc_link *link,
531 const struct link_training_settings *lt_settings,
532 uint32_t offset,
533 uint8_t retries)
534 {
535 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
536 if (offset == 0 && retries == 1 && lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
537 return max(lt_settings->eq_pattern_time, (uint32_t) DPIA_CLK_SYNC_DELAY);
538 else
539 return dpia_get_eq_aux_rd_interval(link, lt_settings, offset);
540 } else if (is_repeater(lt_settings, offset))
541 return dp_translate_training_aux_read_interval(
542 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
543 else
544 return lt_settings->eq_pattern_time;
545 }
546
dp_check_dpcd_reqeust_status(const struct dc_link * link,enum dc_status status)547 bool dp_check_dpcd_reqeust_status(const struct dc_link *link,
548 enum dc_status status)
549 {
550 return (status != DC_OK && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA);
551 }
552
dp_check_link_loss_status(struct dc_link * link,const struct link_training_settings * link_training_setting)553 enum link_training_result dp_check_link_loss_status(
554 struct dc_link *link,
555 const struct link_training_settings *link_training_setting)
556 {
557 enum link_training_result status = LINK_TRAINING_SUCCESS;
558 union lane_status lane_status;
559 union lane_align_status_updated dpcd_lane_status_updated;
560 uint8_t dpcd_buf[6] = {0};
561 uint32_t lane;
562
563 core_link_read_dpcd(
564 link,
565 DP_SINK_COUNT,
566 (uint8_t *)(dpcd_buf),
567 sizeof(dpcd_buf));
568
569 /*parse lane status*/
570 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
571 /*
572 * check lanes status
573 */
574 lane_status.raw = dp_get_nibble_at_index(&dpcd_buf[2], lane);
575 dpcd_lane_status_updated.raw = dpcd_buf[4];
576
577 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
578 !lane_status.bits.CR_DONE_0 ||
579 !lane_status.bits.SYMBOL_LOCKED_0 ||
580 !dp_is_interlane_aligned(dpcd_lane_status_updated)) {
581 /* if one of the channel equalization, clock
582 * recovery or symbol lock is dropped
583 * consider it as (link has been
584 * dropped) dp sink status has changed
585 */
586 status = LINK_TRAINING_LINK_LOSS;
587 break;
588 }
589 }
590
591 return status;
592 }
593
dp_get_lane_status_and_lane_adjust(struct dc_link * link,const struct link_training_settings * link_training_setting,union lane_status ln_status[LANE_COUNT_DP_MAX],union lane_align_status_updated * ln_align,union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],uint32_t offset)594 enum dc_status dp_get_lane_status_and_lane_adjust(
595 struct dc_link *link,
596 const struct link_training_settings *link_training_setting,
597 union lane_status ln_status[LANE_COUNT_DP_MAX],
598 union lane_align_status_updated *ln_align,
599 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
600 uint32_t offset)
601 {
602 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
603 uint8_t lane_adjust_offset = 4;
604 unsigned int lane01_adjust_address;
605 uint8_t dpcd_buf[6] = {0};
606 uint32_t lane;
607 enum dc_status status;
608
609 if (is_repeater(link_training_setting, offset)) {
610 lane01_status_address =
611 DP_LANE0_1_STATUS_PHY_REPEATER1 +
612 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
613 lane_adjust_offset = 3;
614 }
615
616 status = core_link_read_dpcd(
617 link,
618 lane01_status_address,
619 (uint8_t *)(dpcd_buf),
620 sizeof(dpcd_buf));
621
622 if (status != DC_OK) {
623 DC_LOG_HW_LINK_TRAINING("%s:\n Failed to read from address 0x%X,"
624 " keep current lane status and lane adjust unchanged",
625 __func__,
626 lane01_status_address);
627 return status;
628 }
629
630 for (lane = 0; lane <
631 (uint32_t)(link_training_setting->link_settings.lane_count);
632 lane++) {
633
634 ln_status[lane].raw =
635 dp_get_nibble_at_index(&dpcd_buf[0], lane);
636 ln_adjust[lane].raw =
637 dp_get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
638 }
639
640 ln_align->raw = dpcd_buf[2];
641
642 if (is_repeater(link_training_setting, offset)) {
643 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
644 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
645 __func__,
646 offset,
647 lane01_status_address, dpcd_buf[0],
648 lane01_status_address + 1, dpcd_buf[1]);
649
650 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
651 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
652
653 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
654 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
655 __func__,
656 offset,
657 lane01_adjust_address,
658 dpcd_buf[lane_adjust_offset],
659 lane01_adjust_address + 1,
660 dpcd_buf[lane_adjust_offset + 1]);
661 } else {
662 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
663 __func__,
664 lane01_status_address, dpcd_buf[0],
665 lane01_status_address + 1, dpcd_buf[1]);
666
667 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
668
669 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
670 __func__,
671 lane01_adjust_address,
672 dpcd_buf[lane_adjust_offset],
673 lane01_adjust_address + 1,
674 dpcd_buf[lane_adjust_offset + 1]);
675 }
676
677 return status;
678 }
679
override_lane_settings(const struct link_training_settings * lt_settings,struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])680 static void override_lane_settings(const struct link_training_settings *lt_settings,
681 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
682 {
683 uint32_t lane;
684
685 if (lt_settings->voltage_swing == NULL &&
686 lt_settings->pre_emphasis == NULL &&
687 lt_settings->ffe_preset == NULL &&
688 lt_settings->post_cursor2 == NULL)
689
690 return;
691
692 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
693 if (lt_settings->voltage_swing)
694 lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
695 if (lt_settings->pre_emphasis)
696 lane_settings[lane].PRE_EMPHASIS = *lt_settings->pre_emphasis;
697 if (lt_settings->post_cursor2)
698 lane_settings[lane].POST_CURSOR2 = *lt_settings->post_cursor2;
699 if (lt_settings->ffe_preset)
700 lane_settings[lane].FFE_PRESET = *lt_settings->ffe_preset;
701 }
702 }
703
dp_get_lttpr_mode_override(struct dc_link * link,enum lttpr_mode * override)704 void dp_get_lttpr_mode_override(struct dc_link *link, enum lttpr_mode *override)
705 {
706 if (!dp_is_lttpr_present(link))
707 return;
708
709 if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_TRANSPARENT) {
710 *override = LTTPR_MODE_TRANSPARENT;
711 } else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_TRANSPARENT) {
712 *override = LTTPR_MODE_NON_TRANSPARENT;
713 } else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_LTTPR) {
714 *override = LTTPR_MODE_NON_LTTPR;
715 }
716 DC_LOG_DC("lttpr_mode_override chose LTTPR_MODE = %d\n", (uint8_t)(*override));
717 }
718
override_training_settings(struct dc_link * link,const struct dc_link_training_overrides * overrides,struct link_training_settings * lt_settings)719 void override_training_settings(
720 struct dc_link *link,
721 const struct dc_link_training_overrides *overrides,
722 struct link_training_settings *lt_settings)
723 {
724 uint32_t lane;
725
726 /* Override link spread */
727 if (!link->dp_ss_off && overrides->downspread != NULL)
728 lt_settings->link_settings.link_spread = *overrides->downspread ?
729 LINK_SPREAD_05_DOWNSPREAD_30KHZ
730 : LINK_SPREAD_DISABLED;
731
732 /* Override lane settings */
733 if (overrides->voltage_swing != NULL)
734 lt_settings->voltage_swing = overrides->voltage_swing;
735 if (overrides->pre_emphasis != NULL)
736 lt_settings->pre_emphasis = overrides->pre_emphasis;
737 if (overrides->post_cursor2 != NULL)
738 lt_settings->post_cursor2 = overrides->post_cursor2;
739 if (link->wa_flags.force_dp_ffe_preset && !dp_is_lttpr_present(link))
740 lt_settings->ffe_preset = &link->forced_dp_ffe_preset;
741 if (overrides->ffe_preset != NULL)
742 lt_settings->ffe_preset = overrides->ffe_preset;
743 /* Override HW lane settings with BIOS forced values if present */
744 if ((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
745 lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
746 lt_settings->voltage_swing = &link->bios_forced_drive_settings.VOLTAGE_SWING;
747 lt_settings->pre_emphasis = &link->bios_forced_drive_settings.PRE_EMPHASIS;
748 lt_settings->always_match_dpcd_with_hw_lane_settings = false;
749 }
750 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
751 lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
752 lt_settings->voltage_swing != NULL ?
753 *lt_settings->voltage_swing :
754 VOLTAGE_SWING_LEVEL0;
755 lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
756 lt_settings->pre_emphasis != NULL ?
757 *lt_settings->pre_emphasis
758 : PRE_EMPHASIS_DISABLED;
759 lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
760 lt_settings->post_cursor2 != NULL ?
761 *lt_settings->post_cursor2
762 : POST_CURSOR2_DISABLED;
763 }
764
765 if (lt_settings->always_match_dpcd_with_hw_lane_settings)
766 dp_hw_to_dpcd_lane_settings(lt_settings,
767 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
768
769 /* Override training timings */
770 if (overrides->cr_pattern_time != NULL)
771 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
772 if (overrides->eq_pattern_time != NULL)
773 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
774 if (overrides->pattern_for_cr != NULL)
775 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
776 if (overrides->pattern_for_eq != NULL)
777 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
778 if (overrides->enhanced_framing != NULL)
779 lt_settings->enhanced_framing = *overrides->enhanced_framing;
780 if (link->preferred_training_settings.fec_enable != NULL)
781 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
782
783 /* Check DP tunnel LTTPR mode debug option. */
784 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)
785 lt_settings->lttpr_mode = LTTPR_MODE_NON_LTTPR;
786
787 dp_get_lttpr_mode_override(link, <_settings->lttpr_mode);
788
789 }
790
decide_cr_training_pattern(const struct dc_link_settings * link_settings)791 enum dc_dp_training_pattern decide_cr_training_pattern(
792 const struct dc_link_settings *link_settings)
793 {
794 switch (link_dp_get_encoding_format(link_settings)) {
795 case DP_8b_10b_ENCODING:
796 default:
797 return DP_TRAINING_PATTERN_SEQUENCE_1;
798 case DP_128b_132b_ENCODING:
799 return DP_128b_132b_TPS1;
800 }
801 }
802
decide_eq_training_pattern(struct dc_link * link,const struct dc_link_settings * link_settings)803 enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
804 const struct dc_link_settings *link_settings)
805 {
806 struct link_encoder *link_enc;
807 struct encoder_feature_support *enc_caps;
808 struct dpcd_caps *rx_caps = &link->dpcd_caps;
809 enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
810
811 link_enc = link_enc_cfg_get_link_enc(link);
812 ASSERT(link_enc);
813 enc_caps = &link_enc->features;
814
815 switch (link_dp_get_encoding_format(link_settings)) {
816 case DP_8b_10b_ENCODING:
817 if (enc_caps->flags.bits.IS_TPS4_CAPABLE &&
818 rx_caps->max_down_spread.bits.TPS4_SUPPORTED)
819 pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
820 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE &&
821 rx_caps->max_ln_count.bits.TPS3_SUPPORTED)
822 pattern = DP_TRAINING_PATTERN_SEQUENCE_3;
823 else
824 pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
825 break;
826 case DP_128b_132b_ENCODING:
827 pattern = DP_128b_132b_TPS2;
828 break;
829 default:
830 pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
831 break;
832 }
833 return pattern;
834 }
835
dp_decide_lttpr_mode(struct dc_link * link,struct dc_link_settings * link_setting)836 enum lttpr_mode dp_decide_lttpr_mode(struct dc_link *link,
837 struct dc_link_settings *link_setting)
838 {
839 enum dp_link_encoding encoding = link_dp_get_encoding_format(link_setting);
840
841 if (encoding == DP_8b_10b_ENCODING)
842 return dp_decide_8b_10b_lttpr_mode(link);
843 else if (encoding == DP_128b_132b_ENCODING)
844 return dp_decide_128b_132b_lttpr_mode(link);
845
846 ASSERT(0);
847 return LTTPR_MODE_NON_LTTPR;
848 }
849
dp_decide_lane_settings(const struct link_training_settings * lt_settings,const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],union dpcd_training_lane * dpcd_lane_settings)850 void dp_decide_lane_settings(
851 const struct link_training_settings *lt_settings,
852 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
853 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
854 union dpcd_training_lane *dpcd_lane_settings)
855 {
856 uint32_t lane;
857
858 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
859 if (link_dp_get_encoding_format(<_settings->link_settings) ==
860 DP_8b_10b_ENCODING) {
861 hw_lane_settings[lane].VOLTAGE_SWING =
862 (enum dc_voltage_swing)(ln_adjust[lane].bits.
863 VOLTAGE_SWING_LANE);
864 hw_lane_settings[lane].PRE_EMPHASIS =
865 (enum dc_pre_emphasis)(ln_adjust[lane].bits.
866 PRE_EMPHASIS_LANE);
867 } else if (link_dp_get_encoding_format(<_settings->link_settings) ==
868 DP_128b_132b_ENCODING) {
869 hw_lane_settings[lane].FFE_PRESET.raw =
870 ln_adjust[lane].tx_ffe.PRESET_VALUE;
871 }
872 }
873 dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
874
875 if (lt_settings->disallow_per_lane_settings) {
876 /* we find the maximum of the requested settings across all lanes*/
877 /* and set this maximum for all lanes*/
878 maximize_lane_settings(lt_settings, hw_lane_settings);
879 override_lane_settings(lt_settings, hw_lane_settings);
880
881 if (lt_settings->always_match_dpcd_with_hw_lane_settings)
882 dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
883 }
884
885 }
886
dp_decide_training_settings(struct dc_link * link,const struct dc_link_settings * link_settings,struct link_training_settings * lt_settings)887 void dp_decide_training_settings(
888 struct dc_link *link,
889 const struct dc_link_settings *link_settings,
890 struct link_training_settings *lt_settings)
891 {
892 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
893 decide_8b_10b_training_settings(link, link_settings, lt_settings);
894 else if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING)
895 decide_128b_132b_training_settings(link, link_settings, lt_settings);
896 }
897
898
configure_lttpr_mode_transparent(struct dc_link * link)899 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
900 {
901 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
902
903 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
904 return core_link_write_dpcd(link,
905 DP_PHY_REPEATER_MODE,
906 (uint8_t *)&repeater_mode,
907 sizeof(repeater_mode));
908 }
909
configure_lttpr_mode_non_transparent(struct dc_link * link,const struct link_training_settings * lt_settings)910 static enum dc_status configure_lttpr_mode_non_transparent(
911 struct dc_link *link,
912 const struct link_training_settings *lt_settings)
913 {
914 /* aux timeout is already set to extended */
915 /* RESET/SET lttpr mode to enable non transparent mode */
916 uint8_t repeater_cnt;
917 uint32_t aux_interval_address;
918 uint8_t repeater_id;
919 enum dc_status result = DC_ERROR_UNEXPECTED;
920 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
921 const struct dc *dc = link->dc;
922
923 enum dp_link_encoding encoding = dc->link_srv->dp_get_encoding_format(<_settings->link_settings);
924
925 if (encoding == DP_8b_10b_ENCODING) {
926 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
927 result = core_link_write_dpcd(link,
928 DP_PHY_REPEATER_MODE,
929 (uint8_t *)&repeater_mode,
930 sizeof(repeater_mode));
931
932 }
933
934 if (result == DC_OK) {
935 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
936 }
937
938 if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
939
940 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
941
942 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
943 result = core_link_write_dpcd(link,
944 DP_PHY_REPEATER_MODE,
945 (uint8_t *)&repeater_mode,
946 sizeof(repeater_mode));
947
948 if (result == DC_OK) {
949 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
950 }
951
952 if (encoding == DP_8b_10b_ENCODING) {
953 repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
954
955 /* Driver does not need to train the first hop. Skip DPCD read and clear
956 * AUX_RD_INTERVAL for DPTX-to-DPIA hop.
957 */
958 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && repeater_cnt > 0 && repeater_cnt < MAX_REPEATER_CNT)
959 link->dpcd_caps.lttpr_caps.aux_rd_interval[--repeater_cnt] = 0;
960
961 for (repeater_id = repeater_cnt; repeater_id > 0 && repeater_id < MAX_REPEATER_CNT; repeater_id--) {
962 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
963 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
964 core_link_read_dpcd(
965 link,
966 aux_interval_address,
967 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
968 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
969 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
970 }
971 }
972 }
973
974 return result;
975 }
976
dpcd_configure_lttpr_mode(struct dc_link * link,struct link_training_settings * lt_settings)977 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
978 {
979 enum dc_status status = DC_OK;
980
981 if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
982 status = configure_lttpr_mode_transparent(link);
983
984 else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
985 status = configure_lttpr_mode_non_transparent(link, lt_settings);
986
987 return status;
988 }
989
repeater_training_done(struct dc_link * link,uint32_t offset)990 void repeater_training_done(struct dc_link *link, uint32_t offset)
991 {
992 union dpcd_training_pattern dpcd_pattern = {0};
993
994 const uint32_t dpcd_base_lt_offset =
995 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
996 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
997 /* Set training not in progress*/
998 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
999
1000 core_link_write_dpcd(
1001 link,
1002 dpcd_base_lt_offset,
1003 &dpcd_pattern.raw,
1004 1);
1005
1006 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1007 __func__,
1008 offset,
1009 dpcd_base_lt_offset,
1010 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1011 }
1012
dpcd_exit_training_mode(struct dc_link * link,enum dp_link_encoding encoding)1013 static enum link_training_result dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding)
1014 {
1015 enum dc_status status;
1016 uint8_t sink_status = 0;
1017 uint8_t i;
1018
1019 /* clear training pattern set */
1020 status = dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1021
1022 if (dp_check_dpcd_reqeust_status(link, status))
1023 return LINK_TRAINING_ABORT;
1024
1025 if (encoding == DP_128b_132b_ENCODING) {
1026 /* poll for intra-hop disable */
1027 for (i = 0; i < 10; i++) {
1028 if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
1029 (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
1030 break;
1031 fsleep(1000);
1032 }
1033 }
1034
1035 return LINK_TRAINING_SUCCESS;
1036 }
1037
dpcd_configure_channel_coding(struct dc_link * link,struct link_training_settings * lt_settings)1038 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1039 struct link_training_settings *lt_settings)
1040 {
1041 enum dp_link_encoding encoding =
1042 link_dp_get_encoding_format(
1043 <_settings->link_settings);
1044 enum dc_status status;
1045
1046 status = core_link_write_dpcd(
1047 link,
1048 DP_MAIN_LINK_CHANNEL_CODING_SET,
1049 (uint8_t *) &encoding,
1050 1);
1051 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1052 __func__,
1053 DP_MAIN_LINK_CHANNEL_CODING_SET,
1054 encoding);
1055
1056 return status;
1057 }
1058
dpcd_set_training_pattern(struct dc_link * link,enum dc_dp_training_pattern training_pattern)1059 enum dc_status dpcd_set_training_pattern(
1060 struct dc_link *link,
1061 enum dc_dp_training_pattern training_pattern)
1062 {
1063 enum dc_status status;
1064 union dpcd_training_pattern dpcd_pattern = {0};
1065
1066 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
1067 dp_training_pattern_to_dpcd_training_pattern(
1068 link, training_pattern);
1069
1070 status = core_link_write_dpcd(
1071 link,
1072 DP_TRAINING_PATTERN_SET,
1073 &dpcd_pattern.raw,
1074 1);
1075
1076 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
1077 __func__,
1078 DP_TRAINING_PATTERN_SET,
1079 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1080
1081 return status;
1082 }
1083
dpcd_set_link_settings(struct dc_link * link,const struct link_training_settings * lt_settings)1084 enum dc_status dpcd_set_link_settings(
1085 struct dc_link *link,
1086 const struct link_training_settings *lt_settings)
1087 {
1088 uint8_t rate;
1089 enum dc_status status;
1090
1091 union down_spread_ctrl downspread = {0};
1092 union lane_count_set lane_count_set = {0};
1093
1094 downspread.raw = (uint8_t)
1095 (lt_settings->link_settings.link_spread);
1096
1097 lane_count_set.bits.LANE_COUNT_SET =
1098 lt_settings->link_settings.lane_count;
1099
1100 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1101 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1102
1103
1104 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1105 lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
1106 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
1107 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
1108 }
1109
1110 status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1111 &downspread.raw, sizeof(downspread));
1112 if (status != DC_OK)
1113 DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_DOWNSPREAD_CTRL) failed\n", __func__, __LINE__);
1114
1115 status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
1116 &lane_count_set.raw, 1);
1117 if (status != DC_OK)
1118 DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LANE_COUNT_SET) failed\n", __func__, __LINE__);
1119
1120 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
1121 lt_settings->link_settings.use_link_rate_set == true) {
1122 rate = 0;
1123 /* WA for some MUX chips that will power down with eDP and lose supported
1124 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
1125 * MUX chip gets link rate set back before link training.
1126 */
1127 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1128 uint8_t supported_link_rates[16] = {0};
1129
1130 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1131 supported_link_rates, sizeof(supported_link_rates));
1132 }
1133 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
1134 if (status != DC_OK)
1135 DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LINK_BW_SET) failed\n", __func__, __LINE__);
1136
1137 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
1138 <_settings->link_settings.link_rate_set, 1);
1139 if (status != DC_OK)
1140 DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LINK_RATE_SET) failed\n", __func__, __LINE__);
1141 } else {
1142 rate = get_dpcd_link_rate(<_settings->link_settings);
1143
1144 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
1145 if (status != DC_OK)
1146 DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LINK_BW_SET) failed\n", __func__, __LINE__);
1147 }
1148
1149 if (rate) {
1150 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
1151 __func__,
1152 DP_LINK_BW_SET,
1153 lt_settings->link_settings.link_rate,
1154 DP_LANE_COUNT_SET,
1155 lt_settings->link_settings.lane_count,
1156 lt_settings->enhanced_framing,
1157 DP_DOWNSPREAD_CTRL,
1158 lt_settings->link_settings.link_spread);
1159 } else {
1160 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
1161 __func__,
1162 DP_LINK_RATE_SET,
1163 lt_settings->link_settings.link_rate_set,
1164 DP_LANE_COUNT_SET,
1165 lt_settings->link_settings.lane_count,
1166 lt_settings->enhanced_framing,
1167 DP_DOWNSPREAD_CTRL,
1168 lt_settings->link_settings.link_spread);
1169 }
1170
1171 return status;
1172 }
1173
dpcd_set_lane_settings(struct dc_link * link,const struct link_training_settings * link_training_setting,uint32_t offset)1174 enum dc_status dpcd_set_lane_settings(
1175 struct dc_link *link,
1176 const struct link_training_settings *link_training_setting,
1177 uint32_t offset)
1178 {
1179 unsigned int lane0_set_address;
1180 enum dc_status status;
1181 lane0_set_address = DP_TRAINING_LANE0_SET;
1182
1183 if (is_repeater(link_training_setting, offset))
1184 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
1185 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1186
1187 status = core_link_write_dpcd(link,
1188 lane0_set_address,
1189 (uint8_t *)(link_training_setting->dpcd_lane_settings),
1190 link_training_setting->link_settings.lane_count);
1191
1192 if (is_repeater(link_training_setting, offset)) {
1193 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
1194 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1195 __func__,
1196 offset,
1197 lane0_set_address,
1198 link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1199 link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1200 link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1201 link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1202
1203 } else {
1204 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1205 __func__,
1206 lane0_set_address,
1207 link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1208 link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1209 link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1210 link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1211 }
1212
1213 return status;
1214 }
1215
dpcd_set_lt_pattern_and_lane_settings(struct dc_link * link,const struct link_training_settings * lt_settings,enum dc_dp_training_pattern pattern,uint32_t offset)1216 void dpcd_set_lt_pattern_and_lane_settings(
1217 struct dc_link *link,
1218 const struct link_training_settings *lt_settings,
1219 enum dc_dp_training_pattern pattern,
1220 uint32_t offset)
1221 {
1222 uint32_t dpcd_base_lt_offset;
1223 uint8_t dpcd_lt_buffer[5] = {0};
1224 union dpcd_training_pattern dpcd_pattern = {0};
1225 uint32_t size_in_bytes;
1226 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
1227 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
1228
1229 if (is_repeater(lt_settings, offset))
1230 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1231 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1232
1233 /*****************************************************************
1234 * DpcdAddress_TrainingPatternSet
1235 *****************************************************************/
1236 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
1237 dp_training_pattern_to_dpcd_training_pattern(link, pattern);
1238
1239 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
1240 dp_initialize_scrambling_data_symbols(link, pattern);
1241
1242 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
1243 = dpcd_pattern.raw;
1244
1245 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1246 dpia_set_tps_notification(
1247 link,
1248 lt_settings,
1249 dpcd_pattern.v1_4.TRAINING_PATTERN_SET,
1250 offset);
1251
1252 if (is_repeater(lt_settings, offset)) {
1253 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
1254 __func__,
1255 offset,
1256 dpcd_base_lt_offset,
1257 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1258 } else {
1259 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
1260 __func__,
1261 dpcd_base_lt_offset,
1262 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1263 }
1264
1265 /* concatenate everything into one buffer*/
1266 size_in_bytes = lt_settings->link_settings.lane_count *
1267 sizeof(lt_settings->dpcd_lane_settings[0]);
1268
1269 // 0x00103 - 0x00102
1270 memmove(
1271 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
1272 lt_settings->dpcd_lane_settings,
1273 size_in_bytes);
1274
1275 if (is_repeater(lt_settings, offset)) {
1276 if (link_dp_get_encoding_format(<_settings->link_settings) ==
1277 DP_128b_132b_ENCODING)
1278 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1279 " 0x%X TX_FFE_PRESET_VALUE = %x\n",
1280 __func__,
1281 offset,
1282 dpcd_base_lt_offset,
1283 lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1284 else if (link_dp_get_encoding_format(<_settings->link_settings) ==
1285 DP_8b_10b_ENCODING)
1286 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1287 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1288 __func__,
1289 offset,
1290 dpcd_base_lt_offset,
1291 lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1292 lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1293 lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1294 lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1295 } else {
1296 if (link_dp_get_encoding_format(<_settings->link_settings) ==
1297 DP_128b_132b_ENCODING)
1298 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
1299 __func__,
1300 dpcd_base_lt_offset,
1301 lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1302 else if (link_dp_get_encoding_format(<_settings->link_settings) ==
1303 DP_8b_10b_ENCODING)
1304 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1305 __func__,
1306 dpcd_base_lt_offset,
1307 lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1308 lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1309 lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1310 lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1311 }
1312 if (edp_workaround) {
1313 /* for eDP write in 2 parts because the 5-byte burst is
1314 * causing issues on some eDP panels (EPR#366724)
1315 */
1316 core_link_write_dpcd(
1317 link,
1318 DP_TRAINING_PATTERN_SET,
1319 &dpcd_pattern.raw,
1320 sizeof(dpcd_pattern.raw));
1321
1322 core_link_write_dpcd(
1323 link,
1324 DP_TRAINING_LANE0_SET,
1325 (uint8_t *)(lt_settings->dpcd_lane_settings),
1326 size_in_bytes);
1327
1328 } else if (link_dp_get_encoding_format(<_settings->link_settings) ==
1329 DP_128b_132b_ENCODING) {
1330 core_link_write_dpcd(
1331 link,
1332 dpcd_base_lt_offset,
1333 dpcd_lt_buffer,
1334 sizeof(dpcd_lt_buffer));
1335 } else
1336 /* write it all in (1 + number-of-lanes)-byte burst*/
1337 core_link_write_dpcd(
1338 link,
1339 dpcd_base_lt_offset,
1340 dpcd_lt_buffer,
1341 size_in_bytes + sizeof(dpcd_pattern.raw));
1342 }
1343
start_clock_recovery_pattern_early(struct dc_link * link,const struct link_resource * link_res,struct link_training_settings * lt_settings,uint32_t offset)1344 void start_clock_recovery_pattern_early(struct dc_link *link,
1345 const struct link_resource *link_res,
1346 struct link_training_settings *lt_settings,
1347 uint32_t offset)
1348 {
1349 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1350 __func__);
1351 dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
1352 dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
1353 udelay(400);
1354 }
1355
dp_set_hw_test_pattern(struct dc_link * link,const struct link_resource * link_res,enum dp_test_pattern test_pattern,uint8_t * custom_pattern,uint32_t custom_pattern_size)1356 void dp_set_hw_test_pattern(
1357 struct dc_link *link,
1358 const struct link_resource *link_res,
1359 enum dp_test_pattern test_pattern,
1360 uint8_t *custom_pattern,
1361 uint32_t custom_pattern_size)
1362 {
1363 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1364 struct encoder_set_dp_phy_pattern_param pattern_param = {0};
1365
1366 pattern_param.dp_phy_pattern = test_pattern;
1367 pattern_param.custom_pattern = custom_pattern;
1368 pattern_param.custom_pattern_size = custom_pattern_size;
1369 pattern_param.dp_panel_mode = dp_get_panel_mode(link);
1370
1371 if (link_hwss->ext.set_dp_link_test_pattern)
1372 link_hwss->ext.set_dp_link_test_pattern(link, link_res, &pattern_param);
1373 }
1374
dp_set_hw_training_pattern(struct dc_link * link,const struct link_resource * link_res,enum dc_dp_training_pattern pattern,uint32_t offset)1375 bool dp_set_hw_training_pattern(
1376 struct dc_link *link,
1377 const struct link_resource *link_res,
1378 enum dc_dp_training_pattern pattern,
1379 uint32_t offset)
1380 {
1381 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
1382
1383 switch (pattern) {
1384 case DP_TRAINING_PATTERN_SEQUENCE_1:
1385 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
1386 break;
1387 case DP_TRAINING_PATTERN_SEQUENCE_2:
1388 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
1389 break;
1390 case DP_TRAINING_PATTERN_SEQUENCE_3:
1391 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
1392 break;
1393 case DP_TRAINING_PATTERN_SEQUENCE_4:
1394 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1395 break;
1396 case DP_128b_132b_TPS1:
1397 test_pattern = DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE;
1398 break;
1399 case DP_128b_132b_TPS2:
1400 test_pattern = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE;
1401 break;
1402 default:
1403 break;
1404 }
1405
1406 dp_set_hw_test_pattern(link, link_res, test_pattern, NULL, 0);
1407
1408 return true;
1409 }
1410
perform_post_lt_adj_req_sequence(struct dc_link * link,const struct link_resource * link_res,struct link_training_settings * lt_settings)1411 static bool perform_post_lt_adj_req_sequence(
1412 struct dc_link *link,
1413 const struct link_resource *link_res,
1414 struct link_training_settings *lt_settings)
1415 {
1416 enum dc_lane_count lane_count =
1417 lt_settings->link_settings.lane_count;
1418
1419 uint32_t adj_req_count;
1420 uint32_t adj_req_timer;
1421 bool req_drv_setting_changed;
1422 uint32_t lane;
1423 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
1424 union lane_align_status_updated dpcd_lane_status_updated = {0};
1425 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
1426
1427 req_drv_setting_changed = false;
1428 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
1429 adj_req_count++) {
1430
1431 req_drv_setting_changed = false;
1432
1433 for (adj_req_timer = 0;
1434 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
1435 adj_req_timer++) {
1436
1437 dp_get_lane_status_and_lane_adjust(
1438 link,
1439 lt_settings,
1440 dpcd_lane_status,
1441 &dpcd_lane_status_updated,
1442 dpcd_lane_adjust,
1443 DPRX);
1444
1445 if (dpcd_lane_status_updated.bits.
1446 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
1447 return true;
1448
1449 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1450 return false;
1451
1452 if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
1453 !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
1454 !dp_is_interlane_aligned(dpcd_lane_status_updated))
1455 return false;
1456
1457 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
1458
1459 if (lt_settings->
1460 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET !=
1461 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
1462 lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET !=
1463 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
1464
1465 req_drv_setting_changed = true;
1466 break;
1467 }
1468 }
1469
1470 if (req_drv_setting_changed) {
1471 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
1472 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1473
1474 dp_set_drive_settings(link,
1475 link_res,
1476 lt_settings);
1477 break;
1478 }
1479
1480 msleep(1);
1481 }
1482
1483 if (!req_drv_setting_changed) {
1484 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
1485 __func__);
1486
1487 ASSERT(0);
1488 return true;
1489 }
1490 }
1491 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
1492 __func__);
1493
1494 ASSERT(0);
1495 return true;
1496
1497 }
1498
dp_transition_to_video_idle(struct dc_link * link,const struct link_resource * link_res,struct link_training_settings * lt_settings,enum link_training_result status)1499 static enum link_training_result dp_transition_to_video_idle(
1500 struct dc_link *link,
1501 const struct link_resource *link_res,
1502 struct link_training_settings *lt_settings,
1503 enum link_training_result status)
1504 {
1505 union lane_count_set lane_count_set = {0};
1506
1507 /* 4. mainlink output idle pattern*/
1508 dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1509
1510 /*
1511 * 5. post training adjust if required
1512 * If the upstream DPTX and downstream DPRX both support TPS4,
1513 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1514 */
1515 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1516 lt_settings->pattern_for_eq >= DP_TRAINING_PATTERN_SEQUENCE_4) {
1517 /* delay 5ms after Main Link output idle pattern and then check
1518 * DPCD 0202h.
1519 */
1520 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1521 msleep(5);
1522 if (!link->skip_fallback_on_link_loss)
1523 status = dp_check_link_loss_status(link, lt_settings);
1524 }
1525 return status;
1526 }
1527
1528 if (status == LINK_TRAINING_SUCCESS &&
1529 perform_post_lt_adj_req_sequence(link, link_res, lt_settings) == false)
1530 status = LINK_TRAINING_LQA_FAIL;
1531
1532 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1533 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1534 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1535
1536 core_link_write_dpcd(
1537 link,
1538 DP_LANE_COUNT_SET,
1539 &lane_count_set.raw,
1540 sizeof(lane_count_set));
1541
1542 return status;
1543 }
1544
dp_perform_link_training(struct dc_link * link,const struct link_resource * link_res,const struct dc_link_settings * link_settings,bool skip_video_pattern)1545 enum link_training_result dp_perform_link_training(
1546 struct dc_link *link,
1547 const struct link_resource *link_res,
1548 const struct dc_link_settings *link_settings,
1549 bool skip_video_pattern)
1550 {
1551 enum link_training_result status = LINK_TRAINING_SUCCESS;
1552 struct link_training_settings lt_settings = {0};
1553 enum dp_link_encoding encoding =
1554 link_dp_get_encoding_format(link_settings);
1555
1556 /* decide training settings */
1557 dp_decide_training_settings(
1558 link,
1559 link_settings,
1560 <_settings);
1561
1562 override_training_settings(
1563 link,
1564 &link->preferred_training_settings,
1565 <_settings);
1566
1567 /* reset previous training states */
1568 dpcd_exit_training_mode(link, encoding);
1569
1570 /* configure link prior to entering training mode */
1571 dpcd_configure_lttpr_mode(link, <_settings);
1572 dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);
1573 dpcd_configure_channel_coding(link, <_settings);
1574
1575 /* enter training mode:
1576 * Per DP specs starting from here, DPTX device shall not issue
1577 * Non-LT AUX transactions inside training mode.
1578 */
1579 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && encoding == DP_8b_10b_ENCODING)
1580 status = dp_perform_fixed_vs_pe_training_sequence(link, link_res, <_settings);
1581 else if (encoding == DP_8b_10b_ENCODING)
1582 status = dp_perform_8b_10b_link_training(link, link_res, <_settings);
1583 else if (encoding == DP_128b_132b_ENCODING)
1584 status = dp_perform_128b_132b_link_training(link, link_res, <_settings);
1585 else
1586 ASSERT(0);
1587
1588 /* exit training mode */
1589 if ((dpcd_exit_training_mode(link, encoding) != LINK_TRAINING_SUCCESS || status == LINK_TRAINING_ABORT) &&
1590 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1591 dpia_training_abort(link, <_settings, 0);
1592
1593 /* switch to video idle */
1594 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1595 status = dp_transition_to_video_idle(link,
1596 link_res,
1597 <_settings,
1598 status);
1599
1600 /* dump debug data */
1601 dp_log_training_result(link, <_settings, status);
1602 if (status != LINK_TRAINING_SUCCESS)
1603 link->ctx->dc->debug_data.ltFailCount++;
1604 return status;
1605 }
1606
perform_link_training_with_retries(const struct dc_link_settings * link_setting,bool skip_video_pattern,int attempts,struct pipe_ctx * pipe_ctx,enum signal_type signal,bool do_fallback)1607 bool perform_link_training_with_retries(
1608 const struct dc_link_settings *link_setting,
1609 bool skip_video_pattern,
1610 int attempts,
1611 struct pipe_ctx *pipe_ctx,
1612 enum signal_type signal,
1613 bool do_fallback)
1614 {
1615 int j;
1616 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1617 struct dc_stream_state *stream = pipe_ctx->stream;
1618 struct dc_link *link = stream->link;
1619 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1620 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1621 struct dc_link_settings cur_link_settings = *link_setting;
1622 struct dc_link_settings max_link_settings = *link_setting;
1623 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1624 int fail_count = 0;
1625 bool is_link_bw_low = false; /* link bandwidth < stream bandwidth */
1626 bool is_link_bw_min = /* RBR x 1 */
1627 (cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1628 (cur_link_settings.lane_count <= LANE_COUNT_ONE);
1629
1630 dp_trace_commit_lt_init(link);
1631
1632
1633 if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
1634 /* We need to do this before the link training to ensure the idle
1635 * pattern in SST mode will be sent right after the link training
1636 */
1637 link_hwss->setup_stream_encoder(pipe_ctx);
1638
1639 dp_trace_set_lt_start_timestamp(link, false);
1640 j = 0;
1641 while (j < attempts && fail_count < (attempts * 10)) {
1642
1643 DC_LOG_HW_LINK_TRAINING("%s: Beginning link(%d) training attempt %u of %d @ rate(%d) x lane(%d) @ spread = %x\n",
1644 __func__, link->link_index, (unsigned int)j + 1, attempts,
1645 cur_link_settings.link_rate, cur_link_settings.lane_count,
1646 cur_link_settings.link_spread);
1647
1648 dp_enable_link_phy(
1649 link,
1650 &pipe_ctx->link_res,
1651 signal,
1652 pipe_ctx->clock_source->id,
1653 &cur_link_settings);
1654
1655 if (stream->sink_patches.dppowerup_delay > 0) {
1656 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1657
1658 msleep(delay_dp_power_up_in_ms);
1659 }
1660
1661 edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);
1662
1663 dp_set_panel_mode(link, panel_mode);
1664
1665 if (link->aux_access_disabled) {
1666 dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings);
1667 return true;
1668 } else {
1669 if (!link->dc->config.consolidated_dpia_dp_lt && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
1670 status = dpia_perform_link_training(
1671 link,
1672 &pipe_ctx->link_res,
1673 &cur_link_settings,
1674 skip_video_pattern);
1675
1676 /* Transmit idle pattern once training successful. */
1677 if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
1678 dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1679 // Update verified link settings to current one
1680 // Because DPIA LT might fallback to lower link setting.
1681 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1682 link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
1683 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
1684 dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link);
1685 }
1686 }
1687 } else {
1688 status = dp_perform_link_training(
1689 link,
1690 &pipe_ctx->link_res,
1691 &cur_link_settings,
1692 skip_video_pattern);
1693 }
1694
1695 dp_trace_lt_total_count_increment(link, false);
1696 dp_trace_lt_result_update(link, status, false);
1697 dp_trace_set_lt_end_timestamp(link, false);
1698 if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
1699 // Update verified link settings to current one
1700 // Because DPIA LT might fallback to lower link setting.
1701 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1702 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1703 link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
1704 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
1705 dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link);
1706 }
1707 return true;
1708 }
1709 }
1710
1711 fail_count++;
1712 dp_trace_lt_fail_count_update(link, fail_count, false);
1713 if (link->ep_type == DISPLAY_ENDPOINT_PHY) {
1714 /* latest link training still fail or link training is aborted
1715 * skip delay and keep PHY on
1716 */
1717 if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT))
1718 break;
1719 }
1720
1721 if (j == (attempts - 1)) {
1722 DC_LOG_WARNING(
1723 "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",
1724 __func__, link->link_index, (unsigned int)j + 1, attempts,
1725 cur_link_settings.link_rate, cur_link_settings.lane_count,
1726 cur_link_settings.link_spread, status);
1727 } else {
1728 DC_LOG_HW_LINK_TRAINING(
1729 "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",
1730 __func__, link->link_index, (unsigned int)j + 1, attempts,
1731 cur_link_settings.link_rate, cur_link_settings.lane_count,
1732 cur_link_settings.link_spread, status);
1733 }
1734
1735 dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
1736
1737 /* Abort link training if failure due to sink being unplugged. */
1738 if (status == LINK_TRAINING_ABORT) {
1739 enum dc_connection_type type = dc_connection_none;
1740
1741 if (link_detect_connection_type(link, &type) && type == dc_connection_none) {
1742 DC_LOG_HW_LINK_TRAINING("%s: Aborting training because sink unplugged\n", __func__);
1743 break;
1744 }
1745 }
1746
1747 /* Try to train again at original settings if:
1748 * - not falling back between training attempts;
1749 * - aborted previous attempt due to reasons other than sink unplug;
1750 * - successfully trained but at a link rate lower than that required by stream;
1751 * - reached minimum link bandwidth.
1752 */
1753 if (!do_fallback || (status == LINK_TRAINING_ABORT) ||
1754 (status == LINK_TRAINING_SUCCESS && is_link_bw_low) ||
1755 is_link_bw_min) {
1756 j++;
1757 cur_link_settings = *link_setting;
1758 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1759 is_link_bw_low = false;
1760 is_link_bw_min = (cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1761 (cur_link_settings.lane_count <= LANE_COUNT_ONE);
1762
1763 } else if (do_fallback) { /* Try training at lower link bandwidth if doing fallback. */
1764 uint32_t req_bw;
1765 uint32_t link_bw;
1766 enum dc_link_encoding_format link_encoding = DC_LINK_ENCODING_UNSPECIFIED;
1767
1768 decide_fallback_link_setting(link, &max_link_settings,
1769 &cur_link_settings, status);
1770
1771 if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
1772 link_encoding = DC_LINK_ENCODING_DP_8b_10b;
1773 else if (link_dp_get_encoding_format(&cur_link_settings) == DP_128b_132b_ENCODING)
1774 link_encoding = DC_LINK_ENCODING_DP_128b_132b;
1775
1776 /* Flag if reduced link bandwidth no longer meets stream requirements or fallen back to
1777 * minimum link bandwidth.
1778 */
1779 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, link_encoding);
1780 link_bw = dp_link_bandwidth_kbps(link, &cur_link_settings);
1781 is_link_bw_low = (req_bw > link_bw);
1782 is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1783 (cur_link_settings.lane_count <= LANE_COUNT_ONE));
1784
1785 if (is_link_bw_low) {
1786 DC_LOG_WARNING(
1787 "%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n",
1788 __func__, link->link_index, req_bw, link_bw);
1789
1790 return false;
1791 }
1792 }
1793
1794 msleep(delay_between_attempts);
1795 }
1796
1797 return false;
1798 }
1799
1800