1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Register map for Exynos5 DP */ 4 5 #ifndef CPU_SAMSUNG_EXYNOS5250_DP_H 6 #define CPU_SAMSUNG_EXYNOS5250_DP_H 7 8 #include <soc/cpu.h> 9 10 /* DSIM register map */ 11 struct exynos5_dp { 12 u8 res1[0x10]; 13 u32 dp_tx_version; 14 u32 dp_tx_sw_reset; 15 u32 func_en_1; 16 u32 func_en_2; 17 u32 video_ctl_1; 18 u32 video_ctl_2; 19 u32 video_ctl_3; 20 u32 video_ctl_4; 21 u32 clr_blue_cb; 22 u32 clr_green_y; 23 u32 clr_red_cr; 24 u32 video_ctl_8; 25 u8 res2[0x4]; 26 u32 video_ctl_10; 27 u32 total_line_l; 28 u32 total_line_h; 29 u32 active_line_l; 30 u32 active_line_h; 31 u32 v_f_porch; 32 u32 vsync; 33 u32 v_b_porch; 34 u32 total_pixel_l; 35 u32 total_pixel_h; 36 u32 active_pixel_l; 37 u32 active_pixel_h; 38 u32 h_f_porch_l; 39 u32 h_f_porch_h; 40 u32 hsync_l; 41 u32 hysnc_h; 42 u32 h_b_porch_l; 43 u32 h_b_porch_h; 44 u32 vid_status; 45 u32 total_line_sta_l; 46 u32 total_line_sta_h; 47 u32 active_line_sta_l; 48 u32 active_line_sta_h; 49 u32 v_f_porch_sta; 50 u32 vsync_sta; 51 u32 v_b_porch_sta; 52 u32 total_pixel_sta_l; 53 u32 total_pixel_sta_h; 54 u32 active_pixel_sta_l; 55 u32 active_pixel_sta_h; 56 u32 h_f_porch_sta_l; 57 u32 h_f_porch_sta_h; 58 u32 hsync_sta_l; 59 u32 hsync_sta_h; 60 u32 h_b_porch_sta_l; 61 u32 h_b_porch__sta_h; 62 u8 res3[0x288]; 63 u32 lane_map; 64 u8 res4[0x10]; 65 u32 analog_ctl_1; 66 u32 analog_ctl_2; 67 u32 analog_ctl_3; 68 u32 pll_filter_ctl_1; 69 u32 tx_amp_tuning_ctl; 70 u8 res5[0xc]; 71 u32 aux_hw_retry_ctl; 72 u8 res6[0x2c]; 73 u32 int_state; 74 u32 common_int_sta_1; 75 u32 common_int_sta_2; 76 u32 common_int_sta_3; 77 u32 common_int_sta_4; 78 u8 res7[0x8]; 79 u32 dp_int_sta; 80 u32 common_int_mask_1; 81 u32 common_int_mask_2; 82 u32 common_int_mask_3; 83 u32 common_int_mask_4; 84 u8 res8[0x08]; 85 u32 int_sta_mask; 86 u32 int_ctl; 87 u8 res9[0x200]; 88 u32 sys_ctl_1; 89 u32 sys_ctl_2; 90 u32 sys_ctl_3; 91 u32 sys_ctl_4; 92 u32 dp_vid_ctl; 93 u8 res10[0x2c]; 94 u32 pkt_send_ctl; 95 u8 res11[0x4]; 96 u32 dp_hdcp_ctl; 97 u8 res12[0x34]; 98 u32 link_bw_set; 99 u32 lane_count_set; 100 u32 dp_training_ptn_set; 101 u32 ln0_link_trn_ctl; 102 u32 ln1_link_trn_ctl; 103 u32 ln2_link_trn_ctl; 104 u32 ln3_link_trn_ctl; 105 u32 dp_dn_spread; 106 u32 dp_hw_link_training; 107 u8 res13[0x1c]; 108 u32 dp_debug_ctl; 109 u32 dp_hpd_deglitch_l; 110 u32 dp_hpd_deglitch_h; 111 u8 res14[0x14]; 112 u32 dp_link_debug_ctl; 113 u8 res15[0x1c]; 114 u32 m_vid_0; 115 u32 m_vid_1; 116 u32 m_vid_2; 117 u32 n_vid_0; 118 u32 n_vid_1; 119 u32 n_vid_2; 120 u32 m_vid_mon; 121 u32 dp_pll_ctl; 122 u32 dp_phy_pd; 123 u32 dp_phy_test; 124 u8 res16[0x8]; 125 u32 dp_video_fifo_thrd; 126 u8 res17[0x8]; 127 u32 dp_audio_margin; 128 u32 dp_dn_spread_ctl_1; 129 u32 dp_dn_spread_ctl_2; 130 u8 res18[0x18]; 131 u32 dp_m_cal_ctl; 132 u32 m_vid_gen_filter_th; 133 u8 res19[0x14]; 134 u32 m_aud_gen_filter_th; 135 u32 aux_ch_sta; 136 u32 aux_err_num; 137 u32 aux_ch_defer_dtl; 138 u32 aux_rx_comm; 139 u32 buf_data_ctl; 140 u32 aux_ch_ctl_1; 141 u32 aux_addr_7_0; 142 u32 aux_addr_15_8; 143 u32 aux_addr_19_16; 144 u32 aux_ch_ctl_2; 145 u8 res20[0x18]; 146 u32 buf_data_0; 147 u8 res21[0x3c]; 148 u32 soc_general_ctl; 149 }; 150 check_member(exynos5_dp, soc_general_ctl, 0x800); 151 152 static struct exynos5_dp * const exynos_dp0 = (void *)EXYNOS5_DP0_BASE; 153 static struct exynos5_dp * const exynos_dp1 = (void *)EXYNOS5_DP1_BASE; 154 155 /* DP_TX_SW_RESET */ 156 #define RESET_DP_TX (1 << 0) 157 158 /* DP_FUNC_EN_1 */ 159 #define MASTER_VID_FUNC_EN_N (1 << 7) 160 #define SLAVE_VID_FUNC_EN_N (1 << 5) 161 #define AUD_FIFO_FUNC_EN_N (1 << 4) 162 #define AUD_FUNC_EN_N (1 << 3) 163 #define HDCP_FUNC_EN_N (1 << 2) 164 #define CRC_FUNC_EN_N (1 << 1) 165 #define SW_FUNC_EN_N (1 << 0) 166 167 /* DP_FUNC_EN_2 */ 168 #define SSC_FUNC_EN_N (1 << 7) 169 #define AUX_FUNC_EN_N (1 << 2) 170 #define SERDES_FIFO_FUNC_EN_N (1 << 1) 171 #define LS_CLK_DOMAIN_FUNC_EN_N (1 << 0) 172 173 /* DP_VIDEO_CTL_1 */ 174 #define VIDEO_EN (1 << 7) 175 #define HDCP_VIDEO_MUTE (1 << 6) 176 177 /* DP_VIDEO_CTL_1 */ 178 #define IN_D_RANGE_MASK (1 << 7) 179 #define IN_D_RANGE_SHIFT (7) 180 #define IN_D_RANGE_CEA (1 << 7) 181 #define IN_D_RANGE_VESA (0 << 7) 182 #define IN_BPC_MASK (7 << 4) 183 #define IN_BPC_SHIFT (4) 184 #define IN_BPC_12_BITS (3 << 4) 185 #define IN_BPC_10_BITS (2 << 4) 186 #define IN_BPC_8_BITS (1 << 4) 187 #define IN_BPC_6_BITS (0 << 4) 188 #define IN_COLOR_F_MASK (3 << 0) 189 #define IN_COLOR_F_SHIFT (0) 190 #define IN_COLOR_F_YCBCR444 (2 << 0) 191 #define IN_COLOR_F_YCBCR422 (1 << 0) 192 #define IN_COLOR_F_RGB (0 << 0) 193 194 /* DP_VIDEO_CTL_3 */ 195 #define IN_YC_COEFFI_MASK (1 << 7) 196 #define IN_YC_COEFFI_SHIFT (7) 197 #define IN_YC_COEFFI_ITU709 (1 << 7) 198 #define IN_YC_COEFFI_ITU601 (0 << 7) 199 #define VID_CHK_UPDATE_TYPE_MASK (1 << 4) 200 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 201 #define VID_CHK_UPDATE_TYPE_1 (1 << 4) 202 #define VID_CHK_UPDATE_TYPE_0 (0 << 4) 203 204 /* DP_VIDEO_CTL_10 */ 205 #define FORMAT_SEL (1 << 4) 206 #define INTERACE_SCAN_CFG (1 << 2) 207 #define VSYNC_POLARITY_CFG (1 << 1) 208 #define HSYNC_POLARITY_CFG (1 << 0) 209 210 /* DP_LANE_MAP */ 211 #define LANE3_MAP_LOGIC_LANE_0 (0 << 6) 212 #define LANE3_MAP_LOGIC_LANE_1 (1 << 6) 213 #define LANE3_MAP_LOGIC_LANE_2 (2 << 6) 214 #define LANE3_MAP_LOGIC_LANE_3 (3 << 6) 215 #define LANE2_MAP_LOGIC_LANE_0 (0 << 4) 216 #define LANE2_MAP_LOGIC_LANE_1 (1 << 4) 217 #define LANE2_MAP_LOGIC_LANE_2 (2 << 4) 218 #define LANE2_MAP_LOGIC_LANE_3 (3 << 4) 219 #define LANE1_MAP_LOGIC_LANE_0 (0 << 2) 220 #define LANE1_MAP_LOGIC_LANE_1 (1 << 2) 221 #define LANE1_MAP_LOGIC_LANE_2 (2 << 2) 222 #define LANE1_MAP_LOGIC_LANE_3 (3 << 2) 223 #define LANE0_MAP_LOGIC_LANE_0 (0 << 0) 224 #define LANE0_MAP_LOGIC_LANE_1 (1 << 0) 225 #define LANE0_MAP_LOGIC_LANE_2 (2 << 0) 226 #define LANE0_MAP_LOGIC_LANE_3 (3 << 0) 227 228 /* DP_AUX_HW_RETRY_CTL */ 229 #define AUX_BIT_PERIOD_SHIFT 8 230 #define AUX_BIT_PERIOD_MASK 7 231 232 #define AUX_HW_RETRY_INTERVAL_SHIFT 3 233 #define AUX_HW_RETRY_INTERVAL_600_US 0 234 #define AUX_HW_RETRY_INTERVAL_800_US 1 235 #define AUX_HW_RETRY_INTERVAL_1000_US 2 236 #define AUX_HW_RETRY_INTERVAL_1800_US 3 237 #define AUX_HW_RETRY_COUNT_SHIFT 0 238 #define AUX_HW_RETRY_COUNT_MASK 7 239 240 /* DP_COMMON_INT_STA_1 */ 241 #define VSYNC_DET (1 << 7) 242 #define PLL_LOCK_CHG (1 << 6) 243 #define SPDIF_ERR (1 << 5) 244 #define SPDIF_UNSTBL (1 << 4) 245 #define VID_FORMAT_CHG (1 << 3) 246 #define AUD_CLK_CHG (1 << 2) 247 #define VID_CLK_CHG (1 << 1) 248 #define SW_INT (1 << 0) 249 250 /* DP_COMMON_INT_STA_2 */ 251 #define ENC_EN_CHG (1 << 6) 252 #define HW_BKSV_RDY (1 << 3) 253 #define HW_SHA_DONE (1 << 2) 254 #define HW_AUTH_STATE_CHG (1 << 1) 255 #define HW_AUTH_DONE (1 << 0) 256 257 /* DP_COMMON_INT_STA_3 */ 258 #define AFIFO_UNDER (1 << 7) 259 #define AFIFO_OVER (1 << 6) 260 #define R0_CHK_FLAG (1 << 5) 261 262 /* DP_COMMON_INT_STA_4 */ 263 #define PSR_ACTIVE (1 << 7) 264 #define PSR_INACTIVE (1 << 6) 265 #define SPDIF_BI_PHASE_ERR (1 << 5) 266 #define HOTPLUG_CHG (1 << 2) 267 #define HPD_LOST (1 << 1) 268 #define PLUG (1 << 0) 269 270 /* DP_INT_STA */ 271 #define INT_HPD (1 << 6) 272 #define HW_TRAINING_FINISH (1 << 5) 273 #define RPLY_RECEIV (1 << 1) 274 #define AUX_ERR (1 << 0) 275 276 /* DP_INT_CTL */ 277 #define INT_POL0 (1 << 0) 278 #define INT_POL1 (1 << 1) 279 #define SOFT_INT_CTRL (1 << 2) 280 281 /* DP_SYS_CTL_1 */ 282 #define DET_STA (1 << 2) 283 #define FORCE_DET (1 << 1) 284 #define DET_CTRL (1 << 0) 285 286 /* DP_SYS_CTL_2 */ 287 #define CHA_CRI_SHIFT 4 288 #define CHA_CRI_MASK 0xf 289 #define CHA_STA (1 << 2) 290 #define FORCE_CHA (1 << 1) 291 #define CHA_CTRL (1 << 0) 292 293 /* DP_SYS_CTL_3 */ 294 #define HPD_STATUS (1 << 6) 295 #define F_HPD (1 << 5) 296 #define HPD_CTRL (1 << 4) 297 #define HDCP_RDY (1 << 3) 298 #define STRM_VALID (1 << 2) 299 #define F_VALID (1 << 1) 300 #define VALID_CTRL (1 << 0) 301 302 /* DP_SYS_CTL_4 */ 303 #define FIX_M_AUD (1 << 4) 304 #define ENHANCED (1 << 3) 305 #define FIX_M_VID (1 << 2) 306 #define M_VID_UPDATE_CTRL (3 << 0) 307 308 /* DP_TRAINING_PTN_SET */ 309 #define SCRAMBLER_TYPE (1 << 9) 310 #define HW_LINK_TRAINING_PATTERN (1 << 8) 311 #define SCRAMBLING_DISABLE (1 << 5) 312 #define SCRAMBLING_ENABLE (0 << 5) 313 #define LINK_QUAL_PATTERN_SET_MASK (3 << 2) 314 #define LINK_QUAL_PATTERN_SET_PRBS7 (3 << 2) 315 #define LINK_QUAL_PATTERN_SET_D10_2 (1 << 2) 316 #define LINK_QUAL_PATTERN_SET_DISABLE (0 << 2) 317 #define SW_TRAINING_PATTERN_SET_MASK (3 << 0) 318 #define SW_TRAINING_PATTERN_SET_PTN2 (2 << 0) 319 #define SW_TRAINING_PATTERN_SET_PTN1 (1 << 0) 320 #define SW_TRAINING_PATTERN_SET_NORMAL (0 << 0) 321 322 /* DP_LN0_LINK_TRAINING_CTL */ 323 #define PRE_EMPHASIS_SET_SHIFT (3) 324 325 /* DP_DEBUG_CTL */ 326 #define PLL_LOCK (1 << 4) 327 #define F_PLL_LOCK (1 << 3) 328 #define PLL_LOCK_CTRL (1 << 2) 329 #define PN_INV (1 << 0) 330 331 /* DP_M_VID */ 332 #define M_VID_0_VALUE_SHIFT 0 333 #define M_VID_1_VALUE_SHIFT 8 334 #define M_VID_2_VALUE_SHIFT 16 335 336 /* DP_M_VID */ 337 #define N_VID_0_VALUE_SHIFT 0 338 #define N_VID_1_VALUE_SHIFT 8 339 #define N_VID_2_VALUE_SHIFT 16 340 341 /* DP_PLL_CTL */ 342 #define DP_PLL_PD (1 << 7) 343 #define DP_PLL_RESET (1 << 6) 344 #define DP_PLL_LOOP_BIT_DEFAULT (1 << 4) 345 #define DP_PLL_REF_BIT_1_1250V (5 << 0) 346 #define DP_PLL_REF_BIT_1_2500V (7 << 0) 347 348 /* DP_PHY_PD */ 349 #define DP_PHY_PD (1 << 5) 350 #define AUX_PD (1 << 4) 351 #define CH3_PD (1 << 3) 352 #define CH2_PD (1 << 2) 353 #define CH1_PD (1 << 1) 354 #define CH0_PD (1 << 0) 355 356 /* DP_PHY_TEST */ 357 #define MACRO_RST (1 << 5) 358 #define CH1_TEST (1 << 1) 359 #define CH0_TEST (1 << 0) 360 361 /* DP_AUX_CH_STA */ 362 #define AUX_BUSY (1 << 4) 363 #define AUX_STATUS_MASK (0xf << 0) 364 365 /* DP_AUX_CH_DEFER_CTL */ 366 #define DEFER_CTRL_EN (1 << 7) 367 #define DEFER_COUNT_SHIFT 0 368 #define DEFER_COUNT_MASK 0x7f 369 370 /* DP_AUX_RX_COMM */ 371 #define AUX_RX_COMM_I2C_DEFER (2 << 2) 372 #define AUX_RX_COMM_AUX_DEFER (2 << 0) 373 374 /* DP_BUFFER_DATA_CTL */ 375 #define BUF_CLR (1 << 7) 376 377 /* Maximum number of tries for Aux Transaction */ 378 #define MAX_AUX_RETRY_COUNT 10 379 380 /* DP_AUX_CH_CTL_1 */ 381 #define AUX_LENGTH_SHIFT 4 382 #define AUX_LENGTH_MASK 0xf 383 384 #define AUX_TX_COMM_MASK (0xf << 0) 385 #define AUX_TX_COMM_DP_TRANSACTION (1 << 3) 386 #define AUX_TX_COMM_I2C_TRANSACTION (0 << 3) 387 #define AUX_TX_COMM_MOT (1 << 2) 388 #define AUX_TX_COMM_WRITE (0 << 0) 389 #define AUX_TX_COMM_READ (1 << 0) 390 391 /* DP_AUX_ADDR_7_0 */ 392 #define AUX_ADDR_7_0_SHIFT 0 393 #define AUX_ADDR_7_0_MASK 0xff 394 395 /* DP_AUX_ADDR_15_8 */ 396 #define AUX_ADDR_15_8_SHIFT 8 397 #define AUX_ADDR_15_8_MASK 0xff 398 399 /* DP_AUX_ADDR_19_16 */ 400 #define AUX_ADDR_19_16_SHIFT 16 401 #define AUX_ADDR_19_16_MASK 0x0f 402 403 /* DP_AUX_CH_CTL_2 */ 404 #define ADDR_ONLY (1 << 1) 405 #define AUX_EN (1 << 0) 406 407 /* DP_SOC_GENERAL_CTL */ 408 #define AUDIO_MODE_SPDIF_MODE (1 << 8) 409 #define AUDIO_MODE_MASTER_MODE (0 << 8) 410 #define MASTER_VIDEO_INTERLACE_EN (1 << 4) 411 #define VIDEO_MASTER_CLK_SEL (1 << 2) 412 #define VIDEO_MASTER_MODE_EN (1 << 1) 413 #define VIDEO_MODE_MASK (1 << 0) 414 #define VIDEO_MODE_SLAVE_MODE (1 << 0) 415 #define VIDEO_MODE_MASTER_MODE (0 << 0) 416 417 #define HW_TRAINING_ERROR_CODE (7<<4) 418 #define HW_TRAINING_EN (1<<0) 419 420 /* I2C EDID Chip ID, Slave Address */ 421 #define I2C_EDID_DEVICE_ADDR 0x50 422 #define I2C_E_EDID_DEVICE_ADDR 0x30 423 424 #define EDID_BLOCK_LENGTH 0x80 425 #define EDID_HEADER_PATTERN 0x00 426 #define EDID_EXTENSION_FLAG 0x7e 427 #define EDID_CHECKSUM 0x7f 428 429 /* Definition for DPCD Register */ 430 #define DPCD_ADDR_DPCD_REV 0x0000 431 #define DPCD_ADDR_MAX_LINK_RATE 0x0001 432 #define DPCD_ADDR_MAX_LANE_COUNT 0x0002 433 #define DPCD_ADDR_LINK_BW_SET 0x0100 434 #define DPCD_ADDR_LANE_COUNT_SET 0x0101 435 #define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102 436 #define DPCD_ADDR_TRAINING_LANE0_SET 0x0103 437 #define DPCD_ADDR_LANE0_1_STATUS 0x0202 438 #define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204 439 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206 440 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207 441 #define DPCD_ADDR_TEST_REQUEST 0x0218 442 #define DPCD_ADDR_TEST_RESPONSE 0x0260 443 #define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261 444 #define DPCD_ADDR_SINK_POWER_STATE 0x0600 445 446 /* DPCD_ADDR_MAX_LANE_COUNT */ 447 #define DPCD_MAX_LANE_COUNT_MASK 0x1f 448 449 /* DPCD_ADDR_LANE_COUNT_SET */ 450 #define DPCD_ENHANCED_FRAME_EN (1 << 7) 451 #define DPCD_LANE_COUNT_SET_MASK 0x1f 452 453 /* DPCD_ADDR_TRAINING_PATTERN_SET */ 454 #define DPCD_SCRAMBLING_DISABLED (1 << 5) 455 #define DPCD_SCRAMBLING_ENABLED (0 << 5) 456 #define DPCD_TRAINING_PATTERN_2 (2 << 0) 457 #define DPCD_TRAINING_PATTERN_1 (1 << 0) 458 #define DPCD_TRAINING_PATTERN_DISABLED (0 << 0) 459 460 /* DPCD_ADDR_LANE0_1_STATUS */ 461 #define DPCD_LANE_SYMBOL_LOCKED (1 << 2) 462 #define DPCD_LANE_CHANNEL_EQ_DONE (1 << 1) 463 #define DPCD_LANE_CR_DONE (1 << 0) 464 #define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE | \ 465 DPCD_LANE_CHANNEL_EQ_DONE | \ 466 DPCD_LANE_SYMBOL_LOCKED) 467 468 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */ 469 #define DPCD_LINK_STATUS_UPDATED (1 << 7) 470 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 471 #define DPCD_INTERLANE_ALIGN_DONE (1 << 0) 472 473 /* DPCD_ADDR_TEST_REQUEST */ 474 #define DPCD_TEST_EDID_READ (1 << 2) 475 476 /* DPCD_ADDR_TEST_RESPONSE */ 477 #define DPCD_TEST_EDID_CHECKSUM_WRITE (1 << 2) 478 479 /* DPCD_ADDR_SINK_POWER_STATE */ 480 #define DPCD_SET_POWER_STATE_D0 (1 << 0) 481 #define DPCD_SET_POWER_STATE_D4 (2 << 0) 482 483 /* Allow DP Gating clock and set FIMD source to 267 Mhz for DP */ 484 void clock_init_dp_clock(void); 485 486 #endif 487