1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _MT8173_SOC_DDP_H_ 4 #define _MT8173_SOC_DDP_H_ 5 6 #include <soc/addressmap.h> 7 #include <soc/ddp_common.h> 8 #include <types.h> 9 10 struct mmsys_cfg_regs { 11 u32 mmsys_inten; 12 u32 mmsys_intsta; 13 u32 mjc_apb_tx_con; 14 u32 pwm_apb_err_addr; 15 u8 reserved0[12]; 16 u32 isp_mout_en; 17 u32 mdp_rdma0_mout_en; 18 u32 mdp_prz0_mout_en; 19 u32 mdp_prz1_mout_en; 20 u32 mdp_prz2_mout_en; 21 u32 mdp_tdshp0_mout_en; 22 u32 mdp_tdshp1_mout_en; 23 u32 mdp0_mout_en; 24 u32 mdp1_mout_en; 25 u32 disp_ovl0_mout_en; 26 u32 disp_ovl1_mout_en; 27 u32 disp_od_mout_en; 28 u32 disp_gamma_mout_en; 29 u32 disp_ufoe_mout_en; 30 u32 mmsys_mout_rst; 31 u32 mdp_prz0_sel_in; 32 u32 mdp_prz1_sel_in; 33 u32 mdp_prz2_sel_in; 34 u32 mdp_tdshp0_sel_in; 35 u32 mdp_tdshp1_sel_in; 36 u32 mdp0_sel_in; 37 u32 mdp1_sel_in; 38 u32 mdp_crop_sel_in; 39 u32 mdp_wdma_sel_in; 40 u32 mdp_wrot0_sel_in; 41 u32 mdp_wrot1_sel_in; 42 u32 disp_color0_sel_in; 43 u32 disp_color1_sel_in; 44 u32 disp_aal_sel_in; 45 u32 disp_path0_sel_in; 46 u32 disp_path1_sel_in; 47 u32 disp_wdma0_sel_in; 48 u32 disp_wdma1_sel_in; 49 u32 disp_ufoe_sel_in; 50 u32 dsi0_sel_in; 51 u32 dsi1_sel_in; 52 u32 dpi_sel_in; 53 u32 disp_rdma0_sout_sel_in; 54 u32 disp_rdma1_sout_sel_in; 55 u32 disp_rdma2_sout_sel_in; 56 u32 disp_color0_sout_sel_in; 57 u32 disp_color1_sout_sel_in; 58 u32 disp_path0_sout_sel_in; 59 u32 disp_path1_sout_sel_in; 60 u8 reserved1[36]; 61 u32 mmsys_misc; 62 u8 reserved2[12]; 63 u32 mmsys_cg_con0; 64 u32 mmsys_cg_set0; 65 u32 mmsys_cg_clr0; 66 u8 reserved3[4]; 67 u32 mmsys_cg_con1; 68 u32 mmsys_cg_set1; 69 u32 mmsys_cg_clr1; 70 u8 reserved4[4]; 71 u32 mmsys_hw_dcm_dis0; 72 u32 mmsys_hw_dcm_dis_set0; 73 u32 mmsys_hw_dcm_dis_clr0; 74 u8 reserved5[4]; 75 u32 mmsys_hw_dcm_dis1; 76 u32 mmsys_hw_dcm_dis_set1; 77 u32 mmsys_hw_dcm_dis_clr1; 78 u8 reserved6[4]; 79 u32 mmsys_sw0_rst_b; 80 u32 mmsys_sw1_rst_b; 81 u8 reserved7[8]; 82 u32 mmsys_lcm_rst_b; 83 u8 reserved8[20]; 84 u32 smi_n21mux_cfg_wr; 85 u32 smi_n21mux_cfg_rd; 86 u32 ela2gmc_base_addr; 87 u32 ela2gmc_base_addr_end; 88 u32 ela2gmc_final_addr; 89 u32 ela2gmc_status; 90 u8 reserved9[128]; 91 u32 disp_fake_eng_en; 92 u32 disp_fake_eng_rst; 93 u32 disp_fake_eng_con0; 94 u32 disp_fake_eng_con1; 95 u32 disp_fake_eng_rd_addr; 96 u32 disp_fake_eng_wr_addr; 97 u32 disp_fake_eng_state; 98 u8 reserved10[1508]; 99 u32 mmsys_mbist_con; 100 u32 mmsys_mbist_done; 101 u32 mmsys_mbist_holdb; 102 u32 mmsys_mbist_mode; 103 u32 mmsys_mbist_fail0; 104 u32 mmsys_mbist_fail1; 105 u32 mmsys_mbist_fail2; 106 u8 reserved11[4]; 107 u32 mmsys_mbist_bsel[4]; 108 u32 mmsys_mem_delsel[6]; 109 u8 reserved12[56]; 110 u32 mmsys_debug_out_sel; 111 u8 reserved13[12]; 112 u32 mmsys_dummy; 113 u8 reserved14[12]; 114 u32 mmsys_mbist_rp_rst_b; 115 u32 mmsys_mbist_rp_fail; 116 u32 mmsys_mbist_rp_ok; 117 u8 reserved15[4]; 118 u32 disp_dl_valid_0; 119 u32 disp_dl_valid_1; 120 u32 disp_dl_ready_0; 121 u32 disp_dl_ready_1; 122 u32 mdp_dl_valid_0; 123 u32 mdp_dl_valid_1; 124 u32 mdp_dl_ready_0; 125 u32 mdp_dl_ready_1; 126 u32 smi_larb0_greq; 127 u8 reserved16[48]; 128 u32 hdmi_en; 129 }; 130 131 check_member(mmsys_cfg_regs, mmsys_sw1_rst_b, 0x144); 132 check_member(mmsys_cfg_regs, hdmi_en, 0x904); 133 static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE; 134 135 /* DISP_REG_CONFIG_MMSYS_CG_CON0 136 Configures free-run clock gating 0 137 0: Enable clock 138 1: Clock gating */ 139 enum { 140 CG_CON0_SMI_COMMON = BIT(0), 141 CG_CON0_SMI_LARB0 = BIT(1), 142 CG_CON0_CAM_MDP = BIT(2), 143 CG_CON0_MDP_RDMA0 = BIT(3), 144 CG_CON0_MDP_RDMA1 = BIT(4), 145 CG_CON0_MDP_RSZ0 = BIT(5), 146 CG_CON0_MDP_RSZ1 = BIT(6), 147 CG_CON0_MDP_RSZ2 = BIT(7), 148 CG_CON0_MDP_TDSHP0 = BIT(8), 149 CG_CON0_MDP_TDSHP1 = BIT(9), 150 CG_CON0_MDP_CROP = BIT(10), 151 CG_CON0_MDP_WDMA = BIT(11), 152 CG_CON0_MDP_WROT0 = BIT(12), 153 CG_CON0_MDP_WROT1 = BIT(13), 154 CG_CON0_FAKE_ENG = BIT(14), 155 CG_CON0_MUTEX_32K = BIT(15), 156 CG_CON0_DISP_OVL0 = BIT(16), 157 CG_CON0_DISP_OVL1 = BIT(17), 158 CG_CON0_DISP_RDMA0 = BIT(18), 159 CG_CON0_DISP_RDMA1 = BIT(19), 160 CG_CON0_DISP_RDMA2 = BIT(20), 161 CG_CON0_DISP_WDMA0 = BIT(21), 162 CG_CON0_DISP_WDMA1 = BIT(22), 163 CG_CON0_DISP_COLOR0 = BIT(23), 164 CG_CON0_DISP_COLOR1 = BIT(24), 165 CG_CON0_DISP_AAL = BIT(25), 166 CG_CON0_DISP_GAMMA = BIT(26), 167 CG_CON0_DISP_UFOE = BIT(27), 168 CG_CON0_DISP_SPLIT0 = BIT(28), 169 CG_CON0_DISP_SPLIT1 = BIT(29), 170 CG_CON0_DISP_MERGE = BIT(30), 171 CG_CON0_DISP_OD = BIT(31), 172 CG_CON0_ALL = 0xffffffff 173 }; 174 175 /* DISP_REG_CONFIG_MMSYS_CG_CON1 176 Configures free-run clock gating 1 177 0: Enable clock 178 1: Clock gating */ 179 enum { 180 CG_CON1_DISP_PWM0_MM = BIT(0), 181 CG_CON1_DISP_PWM0_26M = BIT(1), 182 CG_CON1_DISP_PWM1_MM = BIT(2), 183 CG_CON1_DISP_PWM1_26M = BIT(3), 184 CG_CON1_DSI0_ENGINE = BIT(4), 185 CG_CON1_DSI0_DIGITAL = BIT(5), 186 CG_CON1_DSI1_ENGINE = BIT(6), 187 CG_CON1_DSI1_DIGITAL = BIT(7), 188 CG_CON1_DPI_PIXEL = BIT(8), 189 CG_CON1_DPI_ENGINE = BIT(9), 190 191 CG_CON1_ALL = 0xffffffff 192 }; 193 194 enum { 195 OVL0_MOUT_EN_COLOR0 = BIT(0), 196 OD_MOUT_EN_RDMA0 = BIT(0), 197 UFOE_MOUT_EN_DSI0 = BIT(0), 198 UFOE_MOUT_EN_SPLIT1 = BIT(1), 199 }; 200 201 enum { 202 COLOR0_SEL_IN_OVL0 = 1, 203 DSI0_SEL_IN_UFOE = 0, 204 DSI0_SEL_IN_SPLIT1 = 1, 205 DSI1_SEL_IN_SPLIT1 = 0, 206 }; 207 208 /* MMSYS_SW1_RST_B */ 209 enum { 210 MMSYS_SW1_RST_DSI0_B = BIT(2), 211 MMSYS_SW1_RST_DSI1_B = BIT(3), 212 }; 213 214 struct disp_mutex_regs { 215 u32 inten; 216 u32 intsta; 217 u8 reserved0[24]; 218 struct { 219 u32 en; 220 u32 dummy; 221 u32 rst; 222 u32 mod; 223 u32 sof; 224 u32 reserved[3]; 225 } mutex[6]; 226 u8 reserved1[32]; 227 u32 debug_out_sel; 228 }; 229 230 check_member(disp_mutex_regs, debug_out_sel, 0x100); 231 static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; 232 233 enum { 234 MUTEX_MOD_DISP_OVL0 = BIT(11), 235 MUTEX_MOD_DISP_RDMA0 = BIT(13), 236 MUTEX_MOD_DISP_COLOR0 = BIT(18), 237 MUTEX_MOD_DISP_AAL = BIT(20), 238 MUTEX_MOD_DISP_UFOE = BIT(22), 239 MUTEX_MOD_DISP_OD = BIT(25), 240 MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_RDMA0 | 241 MUTEX_MOD_DISP_COLOR0 | MUTEX_MOD_DISP_AAL | 242 MUTEX_MOD_DISP_UFOE | MUTEX_MOD_DISP_OD, 243 }; 244 245 struct disp_od_regs { 246 u32 en; 247 u32 reset; 248 u32 inten; 249 u32 ints; 250 u32 status; 251 u8 reserved0[12]; 252 u32 cfg; 253 u32 input_count; 254 u32 output_count; 255 u32 chks_um; 256 u32 size; 257 u8 reserved1[12]; 258 u32 hsync_width; 259 u32 vsync_width; 260 u32 misc; 261 }; 262 263 check_member(disp_od_regs, misc, 0x48); 264 static struct disp_od_regs *const disp_od = (void *)DISP_OD_BASE; 265 266 enum { 267 OD_RELAY_MODE = BIT(0), 268 }; 269 270 struct disp_ufoe_regs { 271 u32 start; 272 u32 inten; 273 u32 intsta; 274 u32 dbuf; 275 u8 reserved0[4]; 276 u32 crc; 277 u32 sw_scratch; 278 u8 reserved1[4]; 279 u32 cr0p6_pad; 280 u8 reserved2[4]; 281 u32 ck_on; 282 u8 reserved3[36]; 283 u32 frame_width; 284 u32 frame_height; 285 u32 outen; 286 u8 reserved4[148]; 287 u32 r0_crc; 288 u8 reserved5[12]; 289 u32 cfg[5]; 290 u8 reserved6[12]; 291 u32 ro[5]; 292 u8 reserved7[12]; 293 u32 dbg[8]; 294 }; 295 296 check_member(disp_ufoe_regs, dbg[7], 0x15C); 297 static struct disp_ufoe_regs *const disp_ufoe = (void *)DISP_UFOE_BASE; 298 299 enum { 300 UFO_BYPASS = BIT(2), 301 UFO_LR = BIT(3) | BIT(0), 302 }; 303 304 void mtk_ddp_init(void); 305 void mtk_ddp_mode_set(const struct edid *edid); 306 307 #endif 308