1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_QMI_H
8 #define ATH12K_QMI_H
9
10 #include <linux/mutex.h>
11 #include <linux/soc/qcom/qmi.h>
12
13 #define ATH12K_HOST_VERSION_STRING "WIN"
14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000
15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64
16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000
17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128
18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45
19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01
20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02
21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1
22
23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07
24 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
25 #define ATH12K_QMI_RESP_LEN_MAX 8192
26 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52
27 #define ATH12K_QMI_CALDB_SIZE 0x480000
28 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20
29 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3
30 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
31 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0
32
33 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035
34 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037
35 #define QMI_WLFW_FW_READY_IND_V01 0x0038
36
37 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144
38 #define ATH12K_FIRMWARE_MODE_OFF 4
39 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0
40
41 #define ATH12K_BOARD_ID_DEFAULT 0xFF
42
43 struct ath12k_base;
44
45 enum ath12k_qmi_file_type {
46 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0,
47 ATH12K_QMI_FILE_TYPE_CALDATA = 2,
48 ATH12K_QMI_FILE_TYPE_EEPROM = 3,
49 ATH12K_QMI_MAX_FILE_TYPE = 4,
50 };
51
52 enum ath12k_qmi_bdf_type {
53 ATH12K_QMI_BDF_TYPE_BIN = 0,
54 ATH12K_QMI_BDF_TYPE_ELF = 1,
55 ATH12K_QMI_BDF_TYPE_REGDB = 4,
56 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5,
57 };
58
59 enum ath12k_qmi_event_type {
60 ATH12K_QMI_EVENT_SERVER_ARRIVE,
61 ATH12K_QMI_EVENT_SERVER_EXIT,
62 ATH12K_QMI_EVENT_REQUEST_MEM,
63 ATH12K_QMI_EVENT_FW_MEM_READY,
64 ATH12K_QMI_EVENT_FW_READY,
65 ATH12K_QMI_EVENT_REGISTER_DRIVER,
66 ATH12K_QMI_EVENT_UNREGISTER_DRIVER,
67 ATH12K_QMI_EVENT_RECOVERY,
68 ATH12K_QMI_EVENT_FORCE_FW_ASSERT,
69 ATH12K_QMI_EVENT_POWER_UP,
70 ATH12K_QMI_EVENT_POWER_DOWN,
71 ATH12K_QMI_EVENT_HOST_CAP,
72 ATH12K_QMI_EVENT_MAX,
73 };
74
75 struct ath12k_qmi_driver_event {
76 struct list_head list;
77 enum ath12k_qmi_event_type type;
78 void *data;
79 };
80
81 struct ath12k_qmi_ce_cfg {
82 const struct ce_pipe_config *tgt_ce;
83 int tgt_ce_len;
84 const struct service_to_pipe *svc_to_ce_map;
85 int svc_to_ce_map_len;
86 const u8 *shadow_reg;
87 int shadow_reg_len;
88 u32 *shadow_reg_v3;
89 int shadow_reg_v3_len;
90 };
91
92 struct ath12k_qmi_event_msg {
93 struct list_head list;
94 enum ath12k_qmi_event_type type;
95 };
96
97 struct target_mem_chunk {
98 u32 size;
99 u32 type;
100 u32 prev_size;
101 u32 prev_type;
102 dma_addr_t paddr;
103 union {
104 void __iomem *ioaddr;
105 void *addr;
106 } v;
107 };
108
109 struct target_info {
110 u32 chip_id;
111 u32 chip_family;
112 u32 board_id;
113 u32 soc_id;
114 u32 fw_version;
115 u32 eeprom_caldata;
116 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
117 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
118 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
119 };
120
121 struct m3_mem_region {
122 u32 size;
123 dma_addr_t paddr;
124 void *vaddr;
125 };
126
127 struct dev_mem_info {
128 u64 start;
129 u64 size;
130 };
131
132 struct ath12k_qmi {
133 struct ath12k_base *ab;
134 struct qmi_handle handle;
135 struct sockaddr_qrtr sq;
136 struct work_struct event_work;
137 struct workqueue_struct *event_wq;
138 struct list_head event_list;
139 spinlock_t event_lock; /* spinlock for qmi event list */
140 struct ath12k_qmi_ce_cfg ce_cfg;
141 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
142 u32 mem_seg_count;
143 u32 target_mem_mode;
144 bool target_mem_delayed;
145 u8 cal_done;
146
147 /* protected with struct ath12k_qmi::event_lock */
148 bool block_event;
149
150 u8 num_radios;
151 struct target_info target;
152 struct m3_mem_region m3_mem;
153 unsigned int service_ins_id;
154 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
155 };
156
157 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261
158 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034
159 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7
160 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034
161 #define QMI_WLFW_MAX_NUM_GPIO_V01 32
162 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64
163 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3
164
165 struct qmi_wlanfw_host_ddr_range {
166 u64 start;
167 u64 size;
168 };
169
170 enum ath12k_qmi_target_mem {
171 HOST_DDR_REGION_TYPE = 0x1,
172 BDF_MEM_REGION_TYPE = 0x2,
173 M3_DUMP_REGION_TYPE = 0x3,
174 CALDB_MEM_REGION_TYPE = 0x4,
175 MLO_GLOBAL_MEM_REGION_TYPE = 0x8,
176 PAGEABLE_MEM_REGION_TYPE = 0x9,
177 };
178
179 enum qmi_wlanfw_host_build_type {
180 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
181 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
182 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
183 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
184 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
185 };
186
187 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
188 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
189
190 struct wlfw_host_mlo_chip_info_s_v01 {
191 u8 chip_id;
192 u8 num_local_links;
193 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
194 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
195 };
196
197 enum ath12k_qmi_cnss_feature {
198 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
199 CNSS_QDSS_CFG_MISS_V01 = 3,
200 CNSS_PCIE_PERST_NO_PULL_V01 = 4,
201 CNSS_MAX_FEATURE_V01 = 64,
202 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
203 };
204
205 struct qmi_wlanfw_host_cap_req_msg_v01 {
206 u8 num_clients_valid;
207 u32 num_clients;
208 u8 wake_msi_valid;
209 u32 wake_msi;
210 u8 gpios_valid;
211 u32 gpios_len;
212 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
213 u8 nm_modem_valid;
214 u8 nm_modem;
215 u8 bdf_support_valid;
216 u8 bdf_support;
217 u8 bdf_cache_support_valid;
218 u8 bdf_cache_support;
219 u8 m3_support_valid;
220 u8 m3_support;
221 u8 m3_cache_support_valid;
222 u8 m3_cache_support;
223 u8 cal_filesys_support_valid;
224 u8 cal_filesys_support;
225 u8 cal_cache_support_valid;
226 u8 cal_cache_support;
227 u8 cal_done_valid;
228 u8 cal_done;
229 u8 mem_bucket_valid;
230 u32 mem_bucket;
231 u8 mem_cfg_mode_valid;
232 u8 mem_cfg_mode;
233 u8 cal_duration_valid;
234 u16 cal_duraiton;
235 u8 platform_name_valid;
236 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
237 u8 ddr_range_valid;
238 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
239 u8 host_build_type_valid;
240 enum qmi_wlanfw_host_build_type host_build_type;
241 u8 mlo_capable_valid;
242 u8 mlo_capable;
243 u8 mlo_chip_id_valid;
244 u16 mlo_chip_id;
245 u8 mlo_group_id_valid;
246 u8 mlo_group_id;
247 u8 max_mlo_peer_valid;
248 u16 max_mlo_peer;
249 u8 mlo_num_chips_valid;
250 u8 mlo_num_chips;
251 u8 mlo_chip_info_valid;
252 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
253 u8 feature_list_valid;
254 u64 feature_list;
255
256 };
257
258 struct qmi_wlanfw_host_cap_resp_msg_v01 {
259 struct qmi_response_type_v01 resp;
260 };
261
262 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0
263 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057
264 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18
265 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057
266
267 struct qmi_wlanfw_phy_cap_req_msg_v01 {
268 };
269
270 struct qmi_wlanfw_phy_cap_resp_msg_v01 {
271 struct qmi_response_type_v01 resp;
272 u8 num_phy_valid;
273 u8 num_phy;
274 u8 board_id_valid;
275 u32 board_id;
276 u8 single_chip_mlo_support_valid;
277 u8 single_chip_mlo_support;
278 };
279
280 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54
281 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020
282 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18
283 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020
284 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c
285
286 struct qmi_wlanfw_ind_register_req_msg_v01 {
287 u8 fw_ready_enable_valid;
288 u8 fw_ready_enable;
289 u8 initiate_cal_download_enable_valid;
290 u8 initiate_cal_download_enable;
291 u8 initiate_cal_update_enable_valid;
292 u8 initiate_cal_update_enable;
293 u8 msa_ready_enable_valid;
294 u8 msa_ready_enable;
295 u8 pin_connect_result_enable_valid;
296 u8 pin_connect_result_enable;
297 u8 client_id_valid;
298 u32 client_id;
299 u8 request_mem_enable_valid;
300 u8 request_mem_enable;
301 u8 fw_mem_ready_enable_valid;
302 u8 fw_mem_ready_enable;
303 u8 fw_init_done_enable_valid;
304 u8 fw_init_done_enable;
305 u8 rejuvenate_enable_valid;
306 u32 rejuvenate_enable;
307 u8 xo_cal_enable_valid;
308 u8 xo_cal_enable;
309 u8 cal_done_enable_valid;
310 u8 cal_done_enable;
311 };
312
313 struct qmi_wlanfw_ind_register_resp_msg_v01 {
314 struct qmi_response_type_v01 resp;
315 u8 fw_status_valid;
316 u64 fw_status;
317 };
318
319 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824
320 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888
321 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7
322 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035
323 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036
324 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036
325 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2
326 #define QMI_WLANFW_MAX_STR_LEN_V01 16
327
328 struct qmi_wlanfw_mem_cfg_s_v01 {
329 u64 offset;
330 u32 size;
331 u8 secure_flag;
332 };
333
334 enum qmi_wlanfw_mem_type_enum_v01 {
335 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
336 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
337 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
338 QMI_WLANFW_MEM_BDF_V01 = 2,
339 QMI_WLANFW_MEM_M3_V01 = 3,
340 QMI_WLANFW_MEM_CAL_V01 = 4,
341 QMI_WLANFW_MEM_DPD_V01 = 5,
342 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
343 };
344
345 struct qmi_wlanfw_mem_seg_s_v01 {
346 u32 size;
347 enum qmi_wlanfw_mem_type_enum_v01 type;
348 u32 mem_cfg_len;
349 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
350 };
351
352 struct qmi_wlanfw_request_mem_ind_msg_v01 {
353 u32 mem_seg_len;
354 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
355 };
356
357 struct qmi_wlanfw_mem_seg_resp_s_v01 {
358 u64 addr;
359 u32 size;
360 enum qmi_wlanfw_mem_type_enum_v01 type;
361 u8 restore;
362 };
363
364 struct qmi_wlanfw_respond_mem_req_msg_v01 {
365 u32 mem_seg_len;
366 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
367 };
368
369 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
370 struct qmi_response_type_v01 resp;
371 };
372
373 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
374 char placeholder;
375 };
376
377 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
378 char placeholder;
379 };
380
381 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0
382 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207
383 #define QMI_WLANFW_CAP_REQ_V01 0x0024
384 #define QMI_WLANFW_CAP_RESP_V01 0x0024
385
386 enum qmi_wlanfw_pipedir_enum_v01 {
387 QMI_WLFW_PIPEDIR_NONE_V01 = 0,
388 QMI_WLFW_PIPEDIR_IN_V01 = 1,
389 QMI_WLFW_PIPEDIR_OUT_V01 = 2,
390 QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
391 };
392
393 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
394 __le32 pipe_num;
395 __le32 pipe_dir;
396 __le32 nentries;
397 __le32 nbytes_max;
398 __le32 flags;
399 };
400
401 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
402 __le32 service_id;
403 __le32 pipe_dir;
404 __le32 pipe_num;
405 };
406
407 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
408 u16 id;
409 u16 offset;
410 };
411
412 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
413 u32 addr;
414 };
415
416 struct qmi_wlanfw_memory_region_info_s_v01 {
417 u64 region_addr;
418 u32 size;
419 u8 secure_flag;
420 };
421
422 struct qmi_wlanfw_rf_chip_info_s_v01 {
423 u32 chip_id;
424 u32 chip_family;
425 };
426
427 struct qmi_wlanfw_rf_board_info_s_v01 {
428 u32 board_id;
429 };
430
431 struct qmi_wlanfw_soc_info_s_v01 {
432 u32 soc_id;
433 };
434
435 struct qmi_wlanfw_fw_version_info_s_v01 {
436 u32 fw_version;
437 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
438 };
439
440 struct qmi_wlanfw_dev_mem_info_s_v01 {
441 u64 start;
442 u64 size;
443 };
444
445 enum qmi_wlanfw_cal_temp_id_enum_v01 {
446 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
447 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
448 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
449 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
450 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
451 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
452 };
453
454 enum qmi_wlanfw_rd_card_chain_cap_v01 {
455 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
456 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
457 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
458 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
459 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
460 };
461
462 struct qmi_wlanfw_cap_resp_msg_v01 {
463 struct qmi_response_type_v01 resp;
464 u8 chip_info_valid;
465 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
466 u8 board_info_valid;
467 struct qmi_wlanfw_rf_board_info_s_v01 board_info;
468 u8 soc_info_valid;
469 struct qmi_wlanfw_soc_info_s_v01 soc_info;
470 u8 fw_version_info_valid;
471 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
472 u8 fw_build_id_valid;
473 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
474 u8 num_macs_valid;
475 u8 num_macs;
476 u8 voltage_mv_valid;
477 u32 voltage_mv;
478 u8 time_freq_hz_valid;
479 u32 time_freq_hz;
480 u8 otp_version_valid;
481 u32 otp_version;
482 u8 eeprom_caldata_read_timeout_valid;
483 u32 eeprom_caldata_read_timeout;
484 u8 fw_caps_valid;
485 u64 fw_caps;
486 u8 rd_card_chain_cap_valid;
487 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
488 u8 dev_mem_info_valid;
489 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
490 };
491
492 struct qmi_wlanfw_cap_req_msg_v01 {
493 char placeholder;
494 };
495
496 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182
497 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7
498 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025
499 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025
500 /* TODO: Need to check with MCL and FW team that data can be pointer and
501 * can be last element in structure
502 */
503 struct qmi_wlanfw_bdf_download_req_msg_v01 {
504 u8 valid;
505 u8 file_id_valid;
506 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
507 u8 total_size_valid;
508 u32 total_size;
509 u8 seg_id_valid;
510 u32 seg_id;
511 u8 data_valid;
512 u32 data_len;
513 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
514 u8 end_valid;
515 u8 end;
516 u8 bdf_type_valid;
517 u8 bdf_type;
518
519 };
520
521 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
522 struct qmi_response_type_v01 resp;
523 };
524
525 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18
526 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
527 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C
528 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C
529
530 struct qmi_wlanfw_m3_info_req_msg_v01 {
531 u64 addr;
532 u32 size;
533 };
534
535 struct qmi_wlanfw_m3_info_resp_msg_v01 {
536 struct qmi_response_type_v01 resp;
537 };
538
539 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11
540 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7
541 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803
542 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7
543 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022
544 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022
545 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023
546 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023
547 #define QMI_WLANFW_MAX_STR_LEN_V01 16
548 #define QMI_WLANFW_MAX_NUM_CE_V01 12
549 #define QMI_WLANFW_MAX_NUM_SVC_V01 24
550 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24
551 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60
552
553 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
554 u32 mode;
555 u8 hw_debug_valid;
556 u8 hw_debug;
557 };
558
559 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
560 struct qmi_response_type_v01 resp;
561 };
562
563 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
564 u8 host_version_valid;
565 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
566 u8 tgt_cfg_valid;
567 u32 tgt_cfg_len;
568 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
569 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
570 u8 svc_cfg_valid;
571 u32 svc_cfg_len;
572 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
573 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
574 u8 shadow_reg_valid;
575 u32 shadow_reg_len;
576 struct qmi_wlanfw_shadow_reg_cfg_s_v01
577 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
578 u8 shadow_reg_v3_valid;
579 u32 shadow_reg_v3_len;
580 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
581 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
582 };
583
584 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
585 struct qmi_response_type_v01 resp;
586 };
587
588 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F
589 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F
590 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7
591 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7
592
593 struct qmi_wlanfw_wlan_ini_req_msg_v01 {
594 /* Must be set to true if enable_fwlog is being passed */
595 u8 enable_fwlog_valid;
596 u8 enable_fwlog;
597 };
598
599 struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
600 struct qmi_response_type_v01 resp;
601 };
602
ath12k_qmi_set_event_block(struct ath12k_qmi * qmi,bool block)603 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block)
604 {
605 lockdep_assert_held(&qmi->event_lock);
606
607 qmi->block_event = block;
608 }
609
ath12k_qmi_get_event_block(struct ath12k_qmi * qmi)610 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi)
611 {
612 lockdep_assert_held(&qmi->event_lock);
613
614 return qmi->block_event;
615 }
616
617 int ath12k_qmi_firmware_start(struct ath12k_base *ab,
618 u32 mode);
619 void ath12k_qmi_firmware_stop(struct ath12k_base *ab);
620 void ath12k_qmi_deinit_service(struct ath12k_base *ab);
621 int ath12k_qmi_init_service(struct ath12k_base *ab);
622 void ath12k_qmi_free_resource(struct ath12k_base *ab);
623 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab);
624
625 #endif
626